Timing Report

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Design Name MXSE
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Sun Mar 27 10:09:02 2022
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 20.100 ns.
Max. Clock Frequency (fSYSTEM) 49.751 MHz.
Limited by Cycle Time for CLK_FSB
Clock to Setup (tCYC) 20.100 ns.
Pad to Pad Delay (tPD) 11.000 ns.
Setup to Clock at the Pad (tSU) 16.600 ns.
Clock Pad to Output Pad Delay (tCO) 14.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_CLK_IOB 142.8 0.0 0 0
TS_CLK_FSB 40.0 20.1 287 0
TS_CLK2X_IOB 66.6 11.0 105 0


Constraint: TS_CLK_IOB

Description: PERIOD:CLK_IOB:142.857nS:HIGH:71.428nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS_CLK_FSB

Description: PERIOD:CLK_FSB:40.000nS:HIGH:20.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
cs/nOverlay1.Q to fsb/VPA.D 40.000 20.100 19.900
cs/nOverlay1.Q to nDTACK_FSB.D 40.000 20.100 19.900
fsb/Ready0r.Q to fsb/VPA.D 40.000 20.100 19.900


Constraint: TS_CLK2X_IOB

Description: PERIOD:CLK2X_IOB:66.666nS:HIGH:33.333nS
Path Requirement (ns) Delay (ns) Slack (ns)
IOBERR.Q to IOBERR.D 66.600 11.000 55.600
iobm/BERRrf.Q to IOBERR.D 33.300 11.000 22.300
iobm/BERRrr.Q to IOBERR.D 66.600 11.000 55.600



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK_IOB 111.111 Limited by Clock Pulse Width for CLK_IOB
CLK_FSB 49.751 Limited by Cycle Time for CLK_FSB
CLK2X_IOB 90.909 Limited by Cycle Time for CLK2X_IOB

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK_IOB
Source Pad Setup to clk (edge) Hold to clk (edge)
E_IOB 6.500 0.000

Setup/Hold Times for Clock CLK_FSB
Source Pad Setup to clk (edge) Hold to clk (edge)
A_FSB<10> 7.900 0.000
A_FSB<11> 7.900 0.000
A_FSB<12> 7.900 0.000
A_FSB<13> 7.900 0.000
A_FSB<14> 7.900 0.000
A_FSB<15> 7.900 0.000
A_FSB<16> 7.900 0.000
A_FSB<17> 7.900 0.000
A_FSB<18> 7.900 0.000
A_FSB<19> 7.900 0.000
A_FSB<20> 15.600 0.000
A_FSB<21> 16.600 0.000
A_FSB<22> 16.600 0.000
A_FSB<23> 16.600 0.000
A_FSB<8> 7.900 0.000
A_FSB<9> 7.900 0.000
SW<1> 7.900 0.000
nAS_FSB 15.600 0.000
nIPL2 6.500 0.000
nLDS_FSB 6.500 0.000
nRES 6.500 0.000
nUDS_FSB 6.500 0.000
nWE_FSB 7.900 0.000

Setup/Hold Times for Clock CLK2X_IOB
Source Pad Setup to clk (edge) Hold to clk (edge)
CLK_IOB 7.500 0.000
nBERR_IOB 7.500 0.000
nBG_IOB 6.500 0.000
nDTACK_IOB 6.500 0.000
nRES 6.500 0.000
nVPA_IOB 6.500 0.000


Clock to Pad Timing

Clock CLK_FSB to Pad
Destination Pad Clock (edge) to Pad
RA<1> 14.500
RA<2> 14.500
RA<4> 14.500
RA<5> 14.500
RA<8> 14.500
nBERR_FSB 14.500
nRAMUWE 14.500
nRAS 14.500
nROMCS 14.500
RA<0> 13.500
RA<3> 13.500
RA<6> 13.500
RA<7> 13.500
RA<9> 13.500
nADoutLE0 13.500
nRAMLWE 13.500
nVPA_FSB 13.500
nADoutLE1 5.800
nBR_IOB 5.800
nCAS 5.800
nDTACK_FSB 5.800

Clock CLK2X_IOB to Pad
Destination Pad Clock (edge) to Pad
nAS_IOB 14.500
nLDS_IOB 14.500
nUDS_IOB 14.500
nVMA_IOB 14.500
nADoutLE0 13.500
nAoutOE 5.800
nDinLE 5.800
nDoutOE 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock CLK_FSB
Source Destination Delay
cs/nOverlay1.Q fsb/VPA.D 20.100
cs/nOverlay1.Q nDTACK_FSB.D 20.100
fsb/Ready0r.Q fsb/VPA.D 20.100
fsb/Ready0r.Q nDTACK_FSB.D 20.100
ram/RAMReady.Q fsb/VPA.D 20.100
ram/RAMReady.Q nDTACK_FSB.D 20.100
TimeoutB.Q fsb/VPA.D 19.100
TimeoutB.Q nDTACK_FSB.D 19.100
fsb/ASrf.Q fsb/VPA.D 19.100
BERR_IOBS.Q fsb/VPA.D 11.400
BERR_IOBS.Q nDTACK_FSB.D 11.400
IORW0.Q IORW0.D 11.400
TimeoutA.Q fsb/VPA.D 11.400
TimeoutA.Q nDTACK_FSB.D 11.400
cnt/RefCnt<5>.Q ram/RAMDIS1.D 11.400
cnt/RefCnt<5>.Q ram/RAMReady.D 11.400
cnt/RefCnt<5>.Q ram/RASEL.D 11.400
cnt/RefCnt<5>.Q ram/RS_FSM_FFd2.D 11.400
cnt/RefCnt<6>.Q ram/RAMDIS1.D 11.400
cnt/RefCnt<6>.Q ram/RAMReady.D 11.400
cnt/RefCnt<6>.Q ram/RASEL.D 11.400
cnt/RefCnt<6>.Q ram/RS_FSM_FFd2.D 11.400
cnt/RefCnt<7>.Q ram/RAMDIS1.D 11.400
cnt/RefCnt<7>.Q ram/RAMReady.D 11.400
cnt/RefCnt<7>.Q ram/RASEL.D 11.400
cnt/RefCnt<7>.Q ram/RS_FSM_FFd2.D 11.400
cnt/RefDone.Q ram/RAMDIS1.D 11.400
cnt/RefDone.Q ram/RAMReady.D 11.400
cnt/RefDone.Q ram/RASEL.D 11.400
cnt/RefDone.Q ram/RS_FSM_FFd2.D 11.400
cs/nOverlay1.Q iobs/IORW1.D 11.400
cs/nOverlay1.Q iobs/Once.D 11.400
cs/nOverlay1.Q ram/RAMDIS1.D 11.400
cs/nOverlay1.Q ram/RASEL.D 11.400
cs/nOverlay1.Q ram/RS_FSM_FFd2.D 11.400
fsb/ASrf.Q ram/RASEL.D 11.400
fsb/ASrf.Q ram/RS_FSM_FFd2.D 11.400
fsb/BERR0r.Q fsb/VPA.D 11.400
fsb/BERR0r.Q nDTACK_FSB.D 11.400
fsb/BERR1r.Q fsb/VPA.D 11.400
fsb/BERR1r.Q nDTACK_FSB.D 11.400
fsb/Ready1r.Q fsb/VPA.D 11.400
fsb/Ready1r.Q nDTACK_FSB.D 11.400
fsb/Ready2r.Q fsb/VPA.D 11.400
fsb/Ready2r.Q nDTACK_FSB.D 11.400
fsb/VPA.Q fsb/VPA.D 11.400
iobs/IOReady.Q fsb/VPA.D 11.400
iobs/IOReady.Q nDTACK_FSB.D 11.400
iobs/Once.Q IORW0.D 11.400
iobs/Once.Q iobs/Once.D 11.400
iobs/PS_FSM_FFd1.Q IORW0.D 11.400
iobs/PS_FSM_FFd2.Q IORW0.D 11.400
nADoutLE1.Q IORW0.D 11.400
nBR_IOB.Q fsb/VPA.D 11.400
nBR_IOB.Q nDTACK_FSB.D 11.400
nDTACK_FSB.Q nDTACK_FSB.D 11.400
ram/Once.Q ram/RASEL.D 11.400
ram/RS_FSM_FFd1.Q ram/RAMDIS1.D 11.400
ram/RS_FSM_FFd1.Q ram/RASEL.D 11.400
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd2.D 11.400
ram/RS_FSM_FFd2.Q ram/RASEL.D 11.400
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd2.D 11.400
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd2.D 11.400
TimeoutA.Q fsb/Ready2r.D 11.000
cnt/RefCnt<5>.Q ram/RAMDIS2.D 11.000
cnt/RefCnt<5>.Q ram/RS_FSM_FFd3.D 11.000
cnt/RefCnt<6>.Q ram/RAMDIS2.D 11.000
cnt/RefCnt<6>.Q ram/RS_FSM_FFd3.D 11.000
cnt/RefCnt<7>.Q ram/RAMDIS2.D 11.000
cnt/RefCnt<7>.Q ram/RS_FSM_FFd3.D 11.000
cnt/RefDone.Q ram/RAMDIS2.D 11.000
cnt/RefDone.Q ram/RS_FSM_FFd3.D 11.000
cs/nOverlay1.Q IOREQ.D 11.000
cs/nOverlay1.Q fsb/Ready1r.D 11.000
cs/nOverlay1.Q fsb/Ready2r.D 11.000
cs/nOverlay1.Q iobs/Load1.D 11.000
cs/nOverlay1.Q iobs/PS_FSM_FFd2.D 11.000
cs/nOverlay1.Q ram/RAMDIS2.D 11.000
cs/nOverlay1.Q ram/RAMReady.D 11.000
cs/nOverlay1.Q ram/RS_FSM_FFd3.D 11.000
fsb/ASrf.Q IORW0.D 11.000
fsb/ASrf.Q fsb/Ready2r.D 11.000
fsb/ASrf.Q iobs/IORW1.D 11.000
fsb/ASrf.Q nDTACK_FSB.D 11.000
fsb/ASrf.Q ram/RAMDIS1.D 11.000
fsb/ASrf.Q ram/RAMDIS2.D 11.000
fsb/ASrf.Q ram/RAMReady.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd3.D 11.000
fsb/Ready1r.Q fsb/Ready1r.D 11.000
fsb/Ready2r.Q fsb/Ready2r.D 11.000
iobs/IORW1.Q IORW0.D 11.000
iobs/IOReady.Q fsb/Ready1r.D 11.000
iobs/PS_FSM_FFd1.Q iobs/IORW1.D 11.000
iobs/PS_FSM_FFd1.Q iobs/Once.D 11.000
iobs/PS_FSM_FFd1.Q iobs/PS_FSM_FFd2.D 11.000
iobs/PS_FSM_FFd2.Q IOREQ.D 11.000
iobs/PS_FSM_FFd2.Q iobs/IORW1.D 11.000
iobs/PS_FSM_FFd2.Q iobs/PS_FSM_FFd2.D 11.000
nADoutLE1.Q IOREQ.D 11.000
nADoutLE1.Q fsb/Ready1r.D 11.000
nADoutLE1.Q fsb/VPA.D 11.000
nADoutLE1.Q iobs/Once.D 11.000
nADoutLE1.Q iobs/PS_FSM_FFd2.D 11.000
nADoutLE1.Q nDTACK_FSB.D 11.000
ram/BACTr.Q ram/RAMDIS1.D 11.000
ram/BACTr.Q ram/RAMReady.D 11.000
ram/BACTr.Q ram/RASEL.D 11.000
ram/BACTr.Q ram/RS_FSM_FFd2.D 11.000
ram/Once.Q ram/RAMDIS1.D 11.000
ram/Once.Q ram/RAMDIS2.D 11.000
ram/Once.Q ram/RAMReady.D 11.000
ram/RAMDIS2.Q ram/RAMDIS2.D 11.000
ram/RS_FSM_FFd1.Q ram/RAMDIS2.D 11.000
ram/RS_FSM_FFd1.Q ram/RAMReady.D 11.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd3.D 11.000
ram/RS_FSM_FFd2.Q ram/RAMDIS1.D 11.000
ram/RS_FSM_FFd2.Q ram/RAMDIS2.D 11.000
ram/RS_FSM_FFd2.Q ram/RAMReady.D 11.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd3.D 11.000
ram/RS_FSM_FFd3.Q ram/RAMDIS1.D 11.000
ram/RS_FSM_FFd3.Q ram/RAMDIS2.D 11.000
ram/RS_FSM_FFd3.Q ram/RAMReady.D 11.000
ram/RS_FSM_FFd3.Q ram/RASEL.D 11.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd3.D 11.000
BERR_IOBS.Q BERR_IOBS.D 10.000
BERR_IOBS.Q fsb/BERR1r.D 10.000
IPL2r0.Q IPL2r1.D 10.000
IPL2r0.Q nBR_IOB.CE 10.000
IPL2r1.Q nBR_IOB.CE 10.000
RESDone.Q nBR_IOB.CE 10.000
RESr0.Q RESDone.CE 10.000
RESr0.Q RESr1.D 10.000
RESr0.Q nBR_IOB.CE 10.000
RESr1.Q RESDone.CE 10.000
RESr1.Q RESr2.D 10.000
RESr1.Q nBR_IOB.CE 10.000
RESr2.Q RESDone.CE 10.000
RESr2.Q nBR_IOB.CE 10.000
RefAck.Q cnt/RefDone.D 10.000
TimeoutA.Q TimeoutA.D 10.000
TimeoutB.Q TimeoutB.D 10.000
TimeoutB.Q fsb/BERR0r.D 10.000
cnt/RefCnt<0>.Q TimeoutA.D 10.000
cnt/RefCnt<0>.Q TimeoutB.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<1>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<2>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<3>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<0>.Q cnt/RefDone.D 10.000
cnt/RefCnt<0>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<1>.Q TimeoutA.D 10.000
cnt/RefCnt<1>.Q TimeoutB.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<2>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<3>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<1>.Q cnt/RefDone.D 10.000
cnt/RefCnt<1>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<2>.Q TimeoutA.D 10.000
cnt/RefCnt<2>.Q TimeoutB.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<3>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<2>.Q cnt/RefDone.D 10.000
cnt/RefCnt<2>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<3>.Q TimeoutA.D 10.000
cnt/RefCnt<3>.Q TimeoutB.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<3>.Q cnt/RefDone.D 10.000
cnt/RefCnt<3>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<4>.Q TimeoutA.D 10.000
cnt/RefCnt<4>.Q TimeoutB.D 10.000
cnt/RefCnt<4>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<4>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<4>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<4>.Q cnt/RefDone.D 10.000
cnt/RefCnt<4>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<5>.Q TimeoutA.D 10.000
cnt/RefCnt<5>.Q TimeoutB.D 10.000
cnt/RefCnt<5>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<5>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<5>.Q cnt/RefDone.D 10.000
cnt/RefCnt<5>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<6>.Q TimeoutA.D 10.000
cnt/RefCnt<6>.Q TimeoutB.D 10.000
cnt/RefCnt<6>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<6>.Q cnt/RefDone.D 10.000
cnt/RefCnt<6>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<7>.Q TimeoutB.D 10.000
cnt/RefCnt<7>.Q cnt/RefDone.D 10.000
cnt/RefCnt<7>.Q cnt/TimeoutBPre.D 10.000
cnt/RefDone.Q cnt/RefDone.D 10.000
cnt/TimeoutBPre.Q TimeoutB.D 10.000
cnt/TimeoutBPre.Q cnt/TimeoutBPre.D 10.000
cs/nOverlay0.Q cs/nOverlay0.D 10.000
cs/nOverlay0.Q cs/nOverlay1.D 10.000
cs/nOverlay1.Q IORW0.D 10.000
cs/nOverlay1.Q fsb/Ready0r.D 10.000
cs/nOverlay1.Q ram/Once.D 10.000
cs/nOverlay1.Q ram/RS_FSM_FFd1.D 10.000
fsb/ASrf.Q BERR_IOBS.D 10.000
fsb/ASrf.Q IOREQ.D 10.000
fsb/ASrf.Q TimeoutA.D 10.000
fsb/ASrf.Q TimeoutB.D 10.000
fsb/ASrf.Q cnt/TimeoutBPre.D 10.000
fsb/ASrf.Q cs/nOverlay0.D 10.000
fsb/ASrf.Q cs/nOverlay1.CE 10.000
fsb/ASrf.Q fsb/BERR0r.D 10.000
fsb/ASrf.Q fsb/BERR1r.D 10.000
fsb/ASrf.Q fsb/Ready0r.D 10.000
fsb/ASrf.Q fsb/Ready1r.D 10.000
fsb/ASrf.Q iobs/IOReady.D 10.000
fsb/ASrf.Q iobs/Load1.D 10.000
fsb/ASrf.Q iobs/Once.D 10.000
fsb/ASrf.Q iobs/PS_FSM_FFd2.D 10.000
fsb/ASrf.Q ram/BACTr.D 10.000
fsb/ASrf.Q ram/Once.D 10.000
fsb/ASrf.Q ram/RS_FSM_FFd1.D 10.000
fsb/BERR0r.Q fsb/BERR0r.D 10.000
fsb/BERR1r.Q fsb/BERR1r.D 10.000
fsb/Ready0r.Q fsb/Ready0r.D 10.000
iobs/Clear1.Q nADoutLE1.D 10.000
iobs/IOACTr.Q BERR_IOBS.D 10.000
iobs/IOACTr.Q IOREQ.D 10.000
iobs/IOACTr.Q iobs/IOReady.D 10.000
iobs/IOACTr.Q iobs/PS_FSM_FFd1.D 10.000
iobs/IOACTr.Q iobs/PS_FSM_FFd2.D 10.000
iobs/IOL1.Q IOL0.D 10.000
iobs/IORW1.Q iobs/IORW1.D 10.000
iobs/IOReady.Q iobs/IOReady.D 10.000
iobs/IOU1.Q IOU0.D 10.000
iobs/Load1.Q iobs/IOL1.CE 10.000
iobs/Load1.Q iobs/IOU1.CE 10.000
iobs/Load1.Q nADoutLE1.D 10.000
iobs/Once.Q BERR_IOBS.D 10.000
iobs/Once.Q IOREQ.D 10.000
iobs/Once.Q iobs/IORW1.D 10.000
iobs/Once.Q iobs/IOReady.D 10.000
iobs/Once.Q iobs/Load1.D 10.000
iobs/Once.Q iobs/PS_FSM_FFd2.D 10.000
iobs/PS_FSM_FFd1.Q ALE0S.D 10.000
iobs/PS_FSM_FFd1.Q IOL0.CE 10.000
iobs/PS_FSM_FFd1.Q IOREQ.D 10.000
iobs/PS_FSM_FFd1.Q IOU0.CE 10.000
iobs/PS_FSM_FFd1.Q iobs/Clear1.D 10.000
iobs/PS_FSM_FFd1.Q iobs/Load1.D 10.000
iobs/PS_FSM_FFd1.Q iobs/PS_FSM_FFd1.D 10.000
iobs/PS_FSM_FFd2.Q ALE0S.D 10.000
iobs/PS_FSM_FFd2.Q BERR_IOBS.D 10.000
iobs/PS_FSM_FFd2.Q IOL0.CE 10.000
iobs/PS_FSM_FFd2.Q IOU0.CE 10.000
iobs/PS_FSM_FFd2.Q iobs/Clear1.D 10.000
iobs/PS_FSM_FFd2.Q iobs/IOReady.D 10.000
iobs/PS_FSM_FFd2.Q iobs/Load1.D 10.000
iobs/PS_FSM_FFd2.Q iobs/Once.D 10.000
iobs/PS_FSM_FFd2.Q iobs/PS_FSM_FFd1.D 10.000
nADoutLE1.Q BERR_IOBS.D 10.000
nADoutLE1.Q IOL0.D 10.000
nADoutLE1.Q IOU0.D 10.000
nADoutLE1.Q iobs/Clear1.D 10.000
nADoutLE1.Q iobs/IORW1.D 10.000
nADoutLE1.Q iobs/IOReady.D 10.000
nADoutLE1.Q iobs/Load1.D 10.000
nADoutLE1.Q nADoutLE1.D 10.000
ram/Once.Q ram/Once.D 10.000
ram/Once.Q ram/RS_FSM_FFd1.D 10.000
ram/Once.Q ram/RS_FSM_FFd3.D 10.000
ram/RAMReady.Q fsb/Ready0r.D 10.000
ram/RASEL.Q nCAS.D 10.000
ram/RS_FSM_FFd1.Q RefAck.D 10.000
ram/RS_FSM_FFd1.Q ram/Once.D 10.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd1.D 10.000
ram/RS_FSM_FFd2.Q RefAck.D 10.000
ram/RS_FSM_FFd2.Q ram/Once.D 10.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd1.D 10.000
ram/RS_FSM_FFd3.Q ram/Once.D 10.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd1.D 10.000

Clock to Setup for clock CLK2X_IOB
Source Destination Delay
IOBERR.Q IOBERR.D 11.000
iobm/BERRrf.Q IOBERR.D 11.000
iobm/BERRrr.Q IOBERR.D 11.000
iobm/DTACKrf.Q IOACT.D 11.000
iobm/DTACKrf.Q IOBERR.D 11.000
iobm/DTACKrr.Q IOACT.D 11.000
iobm/DTACKrr.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd1.Q IOACT.D 11.000
iobm/IOS_FSM_FFd1.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd2.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd3.Q IOACT.D 11.000
iobm/IOS_FSM_FFd3.Q IOBERR.D 11.000
iobm/RESrf.Q IOACT.D 11.000
iobm/RESrf.Q IOBERR.D 11.000
iobm/RESrr.Q IOACT.D 11.000
iobm/RESrr.Q IOBERR.D 11.000
IOACT.Q nVMA_IOB.D 10.000
iobm/BERRrf.Q IOACT.D 10.000
iobm/BERRrf.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/BERRrr.Q IOACT.D 10.000
iobm/BERRrr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/BGr0.Q iobm/BGr1.D 10.000
iobm/BGr0.Q nAoutOE.D 10.000
iobm/BGr1.Q nAoutOE.D 10.000
iobm/DTACKrf.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/DTACKrr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/ES<0>.Q iobm/ES<0>.D 10.000
iobm/ES<0>.Q iobm/ES<1>.D 10.000
iobm/ES<0>.Q iobm/ES<2>.D 10.000
iobm/ES<0>.Q iobm/ES<3>.D 10.000
iobm/ES<0>.Q iobm/ES<4>.D 10.000
iobm/ES<0>.Q iobm/ETACK.D 10.000
iobm/ES<0>.Q nVMA_IOB.D 10.000
iobm/ES<1>.Q iobm/ES<0>.D 10.000
iobm/ES<1>.Q iobm/ES<1>.D 10.000
iobm/ES<1>.Q iobm/ES<2>.D 10.000
iobm/ES<1>.Q iobm/ES<3>.D 10.000
iobm/ES<1>.Q iobm/ES<4>.D 10.000
iobm/ES<1>.Q iobm/ETACK.D 10.000
iobm/ES<1>.Q nVMA_IOB.D 10.000
iobm/ES<2>.Q iobm/ES<0>.D 10.000
iobm/ES<2>.Q iobm/ES<2>.D 10.000
iobm/ES<2>.Q iobm/ES<3>.D 10.000
iobm/ES<2>.Q iobm/ES<4>.D 10.000
iobm/ES<2>.Q iobm/ETACK.D 10.000
iobm/ES<2>.Q nVMA_IOB.D 10.000
iobm/ES<3>.Q iobm/ES<0>.D 10.000
iobm/ES<3>.Q iobm/ES<2>.D 10.000
iobm/ES<3>.Q iobm/ES<3>.D 10.000
iobm/ES<3>.Q iobm/ES<4>.D 10.000
iobm/ES<3>.Q iobm/ETACK.D 10.000
iobm/ES<3>.Q nVMA_IOB.D 10.000
iobm/ES<4>.Q iobm/ES<0>.D 10.000
iobm/ES<4>.Q iobm/ES<2>.D 10.000
iobm/ES<4>.Q iobm/ES<4>.D 10.000
iobm/ES<4>.Q iobm/ETACK.D 10.000
iobm/ES<4>.Q nVMA_IOB.D 10.000
iobm/ETACK.Q IOACT.D 10.000
iobm/ETACK.Q IOBERR.D 10.000
iobm/ETACK.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/Er2.Q iobm/ES<0>.D 10.000
iobm/Er2.Q iobm/ES<1>.D 10.000
iobm/Er2.Q iobm/ES<2>.D 10.000
iobm/Er2.Q iobm/ES<3>.D 10.000
iobm/Er2.Q iobm/ES<4>.D 10.000
iobm/IOREQr.Q ALE0M.D 10.000
iobm/IOREQr.Q IOACT.D 10.000
iobm/IOREQr.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd1.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd1.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd1.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd1.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd1.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd2.Q IOACT.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd2.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd2.Q nDoutOE.D 10.000
iobm/IOS_FSM_FFd2.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd3.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nDoutOE.D 10.000
iobm/IOS_FSM_FFd3.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nUDS_IOB.D 10.000
iobm/RESrf.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/RESrr.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/VPArf.Q nVMA_IOB.D 10.000
iobm/VPArr.Q nVMA_IOB.D 10.000
nAS_IOB.Q nAoutOE.D 10.000
nAoutOE.Q ALE0M.D 10.000
nAoutOE.Q IOACT.D 10.000
nAoutOE.Q iobm/IOS_FSM_FFd3.D 10.000
nAoutOE.Q nAoutOE.D 10.000
nVMA_IOB.Q iobm/ETACK.D 10.000
nVMA_IOB.Q nVMA_IOB.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
A_FSB<11> RA<1> 11.000
A_FSB<12> RA<2> 11.000
A_FSB<14> RA<4> 11.000
A_FSB<15> RA<5> 11.000
A_FSB<20> nBERR_FSB 11.000
A_FSB<20> nROMCS 11.000
A_FSB<21> RA<8> 11.000
A_FSB<21> nBERR_FSB 11.000
A_FSB<21> nRAS 11.000
A_FSB<21> nROMCS 11.000
A_FSB<22> RA<8> 11.000
A_FSB<22> nBERR_FSB 11.000
A_FSB<22> nRAS 11.000
A_FSB<22> nROMCS 11.000
A_FSB<23> RA<8> 11.000
A_FSB<23> nBERR_FSB 11.000
A_FSB<23> nRAS 11.000
A_FSB<23> nROMCS 11.000
A_FSB<2> RA<1> 11.000
A_FSB<3> RA<2> 11.000
A_FSB<5> RA<4> 11.000
A_FSB<6> RA<5> 11.000
A_FSB<9> RA<8> 11.000
SW<1> nROMCS 11.000
nAS_FSB nRAMUWE 11.000
nAS_FSB nRAS 11.000
nUDS_FSB nRAMUWE 11.000
nWE_FSB nRAMUWE 11.000
A_FSB<10> RA<0> 10.000
A_FSB<13> RA<3> 10.000
A_FSB<16> RA<6> 10.000
A_FSB<17> RA<7> 10.000
A_FSB<18> RA<8> 10.000
A_FSB<19> RA<11> 10.000
A_FSB<19> RA<9> 10.000
A_FSB<1> RA<0> 10.000
A_FSB<20> RA<9> 10.000
A_FSB<20> nDinOE 10.000
A_FSB<21> RA<10> 10.000
A_FSB<21> nDinOE 10.000
A_FSB<22> nDinOE 10.000
A_FSB<23> nDinOE 10.000
A_FSB<4> RA<3> 10.000
A_FSB<7> RA<6> 10.000
A_FSB<8> RA<7> 10.000
SW<0> CLK20EN 10.000
SW<0> CLK25EN 10.000
SW<1> nDinOE 10.000
nAS_FSB nBERR_FSB 10.000
nAS_FSB nDinOE 10.000
nAS_FSB nOE 10.000
nAS_FSB nRAMLWE 10.000
nAS_FSB nROMWE 10.000
nAS_FSB nVPA_FSB 10.000
nLDS_FSB nRAMLWE 10.000
nWE_FSB nDinOE 10.000
nWE_FSB nOE 10.000
nWE_FSB nRAMLWE 10.000
nWE_FSB nROMWE 10.000



Number of paths analyzed: 392
Number of Timing errors: 0
Analysis Completed: Sun Mar 27 10:09:05 2022