Timing Report

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Design Name MXSE
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Mon Feb 07 00:05:04 2022
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 19.100 ns.
Max. Clock Frequency (fSYSTEM) 52.356 MHz.
Limited by Cycle Time for CLK_FSB
Clock to Setup (tCYC) 19.100 ns.
Pad to Pad Delay (tPD) 11.000 ns.
Setup to Clock at the Pad (tSU) 15.600 ns.
Clock Pad to Output Pad Delay (tCO) 14.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 19.1 398 398
AUTO_TS_P2P 0.0 14.5 79 79
AUTO_TS_P2F 0.0 17.4 216 216
AUTO_TS_F2P 0.0 12.7 35 35


Constraint: TS1000

Description: PERIOD:PERIOD_CLK_IOB:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_CLK_FSB:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_CLK2X_IOB:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
cs/nOverlay1.Q to nDTACK_FSB.D 0.000 19.100 -19.100
fsb/ASrf.Q to fsb/VPA.D 0.000 19.100 -19.100
BERR_IOBS.Q to fsb/VPA.D 0.000 11.400 -11.400


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK_FSB to nBERR_FSB 0.000 14.500 -14.500
CLK_FSB to nRAS 0.000 14.500 -14.500
CLK_FSB to nROMCS 0.000 14.500 -14.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A_FSB<22> to nDTACK_FSB.D 0.000 17.400 -17.400
nAS_FSB to fsb/VPA.D 0.000 17.400 -17.400
A_FSB<10> to fsb/VPA.D 0.000 9.700 -9.700


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
BERR_IOBS.Q to nBERR_FSB 0.000 12.700 -12.700
RefAck.Q to nRAS 0.000 12.700 -12.700
cs/nOverlay1.Q to nRAS 0.000 12.700 -12.700



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK_IOB 111.111 Limited by Clock Pulse Width for CLK_IOB
CLK_FSB 52.356 Limited by Cycle Time for CLK_FSB
CLK2X_IOB 90.909 Limited by Cycle Time for CLK2X_IOB

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK_IOB
Source Pad Setup to clk (edge) Hold to clk (edge)
E_IOB 6.500 0.000

Setup/Hold Times for Clock CLK_FSB
Source Pad Setup to clk (edge) Hold to clk (edge)
A_FSB<10> 7.900 0.000
A_FSB<11> 7.900 0.000
A_FSB<12> 7.900 0.000
A_FSB<13> 7.900 0.000
A_FSB<14> 7.900 0.000
A_FSB<15> 7.900 0.000
A_FSB<16> 7.900 0.000
A_FSB<17> 7.900 0.000
A_FSB<18> 7.900 0.000
A_FSB<19> 7.900 0.000
A_FSB<20> 7.900 0.000
A_FSB<21> 7.900 0.000
A_FSB<22> 15.600 0.000
A_FSB<23> 7.900 0.000
A_FSB<8> 7.900 0.000
A_FSB<9> 7.900 0.000
nAS_FSB 15.600 0.000
nLDS_FSB 6.500 0.000
nUDS_FSB 6.500 0.000
nWE_FSB 7.900 0.000

Setup/Hold Times for Clock CLK2X_IOB
Source Pad Setup to clk (edge) Hold to clk (edge)
CLK_IOB 7.500 0.000
nBERR_IOB 7.500 0.000
nDTACK_IOB 6.500 0.000
nRES 6.500 0.000
nVPA_IOB 6.500 0.000


Clock to Pad Timing

Clock CLK_FSB to Pad
Destination Pad Clock (edge) to Pad
nBERR_FSB 14.500
nRAS 14.500
nROMCS 14.500
RA<0> 13.500
RA<1> 13.500
RA<2> 13.500
RA<3> 13.500
RA<4> 13.500
RA<5> 13.500
RA<6> 13.500
RA<7> 13.500
RA<8> 13.500
RA<9> 13.500
nADoutLE0 13.500
nRAMLWE 13.500
nRAMUWE 13.500
nVPA_FSB 13.500
nADoutLE1 5.800
nCAS 5.800
nDTACK_FSB 5.800

Clock CLK2X_IOB to Pad
Destination Pad Clock (edge) to Pad
nADoutLE0 13.500
nAS_IOB 5.800
nDinLE 5.800
nDoutOE 5.800
nLDS_IOB 5.800
nUDS_IOB 5.800
nVMA_IOB 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock CLK_FSB
Source Destination Delay
cs/nOverlay1.Q nDTACK_FSB.D 19.100
fsb/ASrf.Q fsb/VPA.D 19.100
BERR_IOBS.Q fsb/VPA.D 11.400
BERR_IOBS.Q nDTACK_FSB.D 11.400
IORW0.Q IORW0.D 11.400
TimeoutA.Q fsb/VPA.D 11.400
TimeoutA.Q nDTACK_FSB.D 11.400
TimeoutB.Q fsb/VPA.D 11.400
TimeoutB.Q nDTACK_FSB.D 11.400
cnt/RefCnt<5>.Q ram/RAMDIS1.D 11.400
cnt/RefCnt<5>.Q ram/RAMReady.D 11.400
cnt/RefCnt<5>.Q ram/RASEL.D 11.400
cnt/RefCnt<6>.Q ram/RAMDIS1.D 11.400
cnt/RefCnt<6>.Q ram/RAMReady.D 11.400
cnt/RefCnt<6>.Q ram/RASEL.D 11.400
cnt/RefCnt<7>.Q ram/RAMDIS1.D 11.400
cnt/RefCnt<7>.Q ram/RAMReady.D 11.400
cnt/RefCnt<7>.Q ram/RASEL.D 11.400
cnt/RefDone.Q ram/RAMDIS1.D 11.400
cnt/RefDone.Q ram/RAMReady.D 11.400
cnt/RefDone.Q ram/RASEL.D 11.400
cs/nOverlay1.Q IORW0.D 11.400
cs/nOverlay1.Q fsb/Ready1r.D 11.400
cs/nOverlay1.Q fsb/VPA.D 11.400
cs/nOverlay1.Q iobs/IORW1.D 11.400
cs/nOverlay1.Q iobs/Once.D 11.400
cs/nOverlay1.Q iobs/PS_FSM_FFd2.D 11.400
cs/nOverlay1.Q ram/RAMDIS1.D 11.400
cs/nOverlay1.Q ram/RASEL.D 11.400
fsb/ASrf.Q IORW0.D 11.400
fsb/ASrf.Q ram/RASEL.D 11.400
fsb/BERR0r.Q fsb/VPA.D 11.400
fsb/BERR0r.Q nDTACK_FSB.D 11.400
fsb/BERR1r.Q fsb/VPA.D 11.400
fsb/BERR1r.Q nDTACK_FSB.D 11.400
fsb/Ready1r.Q fsb/Ready1r.D 11.400
fsb/Ready1r.Q fsb/VPA.D 11.400
fsb/Ready1r.Q nDTACK_FSB.D 11.400
fsb/Ready2r.Q fsb/VPA.D 11.400
fsb/Ready2r.Q nDTACK_FSB.D 11.400
fsb/VPA.Q fsb/VPA.D 11.400
iobs/IOReady.Q fsb/Ready1r.D 11.400
iobs/IOReady.Q fsb/VPA.D 11.400
iobs/IOReady.Q nDTACK_FSB.D 11.400
iobs/Once.Q IORW0.D 11.400
iobs/Once.Q iobs/Once.D 11.400
iobs/PS_FSM_FFd1.Q IORW0.D 11.400
iobs/PS_FSM_FFd1.Q iobs/PS_FSM_FFd2.D 11.400
iobs/PS_FSM_FFd2.Q IORW0.D 11.400
iobs/PS_FSM_FFd2.Q iobs/PS_FSM_FFd2.D 11.400
nADoutLE1.Q IORW0.D 11.400
nADoutLE1.Q fsb/Ready1r.D 11.400
nADoutLE1.Q iobs/PS_FSM_FFd2.D 11.400
nADoutLE1.Q nDTACK_FSB.D 11.400
nDTACK_FSB.Q nDTACK_FSB.D 11.400
ram/Once.Q ram/RASEL.D 11.400
ram/RS_FSM_FFd1.Q ram/RAMDIS1.D 11.400
ram/RS_FSM_FFd1.Q ram/RASEL.D 11.400
ram/RS_FSM_FFd2.Q ram/RASEL.D 11.400
BERR_IOBS.Q BERR_IOBS.D 11.000
TimeoutA.Q fsb/Ready2r.D 11.000
cnt/RefCnt<5>.Q ram/RAMDIS2.D 11.000
cnt/RefCnt<5>.Q ram/RS_FSM_FFd2.D 11.000
cnt/RefCnt<5>.Q ram/RS_FSM_FFd3.D 11.000
cnt/RefCnt<6>.Q ram/RAMDIS2.D 11.000
cnt/RefCnt<6>.Q ram/RS_FSM_FFd2.D 11.000
cnt/RefCnt<6>.Q ram/RS_FSM_FFd3.D 11.000
cnt/RefCnt<7>.Q ram/RAMDIS2.D 11.000
cnt/RefCnt<7>.Q ram/RS_FSM_FFd2.D 11.000
cnt/RefCnt<7>.Q ram/RS_FSM_FFd3.D 11.000
cnt/RefDone.Q ram/RAMDIS2.D 11.000
cnt/RefDone.Q ram/RS_FSM_FFd2.D 11.000
cnt/RefDone.Q ram/RS_FSM_FFd3.D 11.000
cs/nOverlay0.Q cs/nOverlay0.D 11.000
cs/nOverlay1.Q IOREQ.D 11.000
cs/nOverlay1.Q fsb/Ready2r.D 11.000
cs/nOverlay1.Q iobs/Load1.D 11.000
cs/nOverlay1.Q ram/RAMDIS2.D 11.000
cs/nOverlay1.Q ram/RAMReady.D 11.000
cs/nOverlay1.Q ram/RS_FSM_FFd2.D 11.000
cs/nOverlay1.Q ram/RS_FSM_FFd3.D 11.000
fsb/ASrf.Q BERR_IOBS.D 11.000
fsb/ASrf.Q cs/nOverlay0.D 11.000
fsb/ASrf.Q fsb/Ready2r.D 11.000
fsb/ASrf.Q iobs/IORW1.D 11.000
fsb/ASrf.Q iobs/PS_FSM_FFd2.D 11.000
fsb/ASrf.Q ram/RAMDIS1.D 11.000
fsb/ASrf.Q ram/RAMDIS2.D 11.000
fsb/ASrf.Q ram/RAMReady.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd2.D 11.000
fsb/ASrf.Q ram/RS_FSM_FFd3.D 11.000
fsb/Ready0r.Q fsb/VPA.D 11.000
fsb/Ready0r.Q nDTACK_FSB.D 11.000
fsb/Ready2r.Q fsb/Ready2r.D 11.000
iobs/IOACTr.Q BERR_IOBS.D 11.000
iobs/IORW1.Q iobs/IORW1.D 11.000
iobs/Once.Q BERR_IOBS.D 11.000
iobs/PS_FSM_FFd1.Q iobs/IORW1.D 11.000
iobs/PS_FSM_FFd1.Q iobs/Once.D 11.000
iobs/PS_FSM_FFd2.Q BERR_IOBS.D 11.000
iobs/PS_FSM_FFd2.Q IOREQ.D 11.000
iobs/PS_FSM_FFd2.Q iobs/IORW1.D 11.000
iobs/PS_FSM_FFd2.Q iobs/Once.D 11.000
nADoutLE1.Q BERR_IOBS.D 11.000
nADoutLE1.Q IOREQ.D 11.000
nADoutLE1.Q fsb/VPA.D 11.000
nADoutLE1.Q iobs/Once.D 11.000
ram/BACTr.Q ram/RAMDIS1.D 11.000
ram/BACTr.Q ram/RAMReady.D 11.000
ram/BACTr.Q ram/RASEL.D 11.000
ram/Once.Q ram/RAMDIS1.D 11.000
ram/Once.Q ram/RAMDIS2.D 11.000
ram/Once.Q ram/RAMReady.D 11.000
ram/RAMDIS2.Q ram/RAMDIS2.D 11.000
ram/RAMReady.Q fsb/VPA.D 11.000
ram/RAMReady.Q nDTACK_FSB.D 11.000
ram/RS_FSM_FFd1.Q ram/RAMDIS2.D 11.000
ram/RS_FSM_FFd1.Q ram/RAMReady.D 11.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd2.D 11.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd3.D 11.000
ram/RS_FSM_FFd2.Q ram/RAMDIS1.D 11.000
ram/RS_FSM_FFd2.Q ram/RAMDIS2.D 11.000
ram/RS_FSM_FFd2.Q ram/RAMReady.D 11.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd2.D 11.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd3.D 11.000
ram/RS_FSM_FFd3.Q ram/RAMDIS1.D 11.000
ram/RS_FSM_FFd3.Q ram/RAMDIS2.D 11.000
ram/RS_FSM_FFd3.Q ram/RAMReady.D 11.000
ram/RS_FSM_FFd3.Q ram/RASEL.D 11.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd2.D 11.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd3.D 11.000
BERR_IOBS.Q fsb/BERR1r.D 10.000
RefAck.Q cnt/RefDone.D 10.000
TimeoutA.Q TimeoutA.D 10.000
TimeoutB.Q TimeoutB.D 10.000
TimeoutB.Q fsb/BERR0r.D 10.000
cnt/RefCnt<0>.Q TimeoutA.D 10.000
cnt/RefCnt<0>.Q TimeoutB.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<1>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<2>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<3>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<0>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<0>.Q cnt/RefDone.D 10.000
cnt/RefCnt<0>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<1>.Q TimeoutA.D 10.000
cnt/RefCnt<1>.Q TimeoutB.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<2>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<3>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<1>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<1>.Q cnt/RefDone.D 10.000
cnt/RefCnt<1>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<2>.Q TimeoutA.D 10.000
cnt/RefCnt<2>.Q TimeoutB.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<3>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<2>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<2>.Q cnt/RefDone.D 10.000
cnt/RefCnt<2>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<3>.Q TimeoutA.D 10.000
cnt/RefCnt<3>.Q TimeoutB.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<4>.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<3>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<3>.Q cnt/RefDone.D 10.000
cnt/RefCnt<3>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<4>.Q TimeoutA.D 10.000
cnt/RefCnt<4>.Q TimeoutB.D 10.000
cnt/RefCnt<4>.Q cnt/RefCnt<5>.D 10.000
cnt/RefCnt<4>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<4>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<4>.Q cnt/RefDone.D 10.000
cnt/RefCnt<4>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<5>.Q TimeoutA.D 10.000
cnt/RefCnt<5>.Q TimeoutB.D 10.000
cnt/RefCnt<5>.Q cnt/RefCnt<6>.D 10.000
cnt/RefCnt<5>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<5>.Q cnt/RefDone.D 10.000
cnt/RefCnt<5>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<6>.Q TimeoutA.D 10.000
cnt/RefCnt<6>.Q TimeoutB.D 10.000
cnt/RefCnt<6>.Q cnt/RefCnt<7>.D 10.000
cnt/RefCnt<6>.Q cnt/RefDone.D 10.000
cnt/RefCnt<6>.Q cnt/TimeoutBPre.D 10.000
cnt/RefCnt<7>.Q TimeoutB.D 10.000
cnt/RefCnt<7>.Q cnt/RefDone.D 10.000
cnt/RefCnt<7>.Q cnt/TimeoutBPre.D 10.000
cnt/RefDone.Q cnt/RefDone.D 10.000
cnt/TimeoutBPre.Q TimeoutB.D 10.000
cnt/TimeoutBPre.Q cnt/TimeoutBPre.D 10.000
cs/nOverlay0.Q cs/nOverlay1.D 10.000
cs/nOverlay1.Q fsb/Ready0r.D 10.000
cs/nOverlay1.Q ram/Once.D 10.000
cs/nOverlay1.Q ram/RS_FSM_FFd1.D 10.000
fsb/ASrf.Q IOREQ.D 10.000
fsb/ASrf.Q TimeoutA.D 10.000
fsb/ASrf.Q TimeoutB.D 10.000
fsb/ASrf.Q cnt/TimeoutBPre.D 10.000
fsb/ASrf.Q cs/nOverlay1.CE 10.000
fsb/ASrf.Q fsb/BERR0r.D 10.000
fsb/ASrf.Q fsb/BERR1r.D 10.000
fsb/ASrf.Q fsb/Ready0r.D 10.000
fsb/ASrf.Q fsb/Ready1r.D 10.000
fsb/ASrf.Q iobs/IOReady.D 10.000
fsb/ASrf.Q iobs/Load1.D 10.000
fsb/ASrf.Q iobs/Once.D 10.000
fsb/ASrf.Q nDTACK_FSB.D 10.000
fsb/ASrf.Q ram/BACTr.D 10.000
fsb/ASrf.Q ram/Once.D 10.000
fsb/ASrf.Q ram/RS_FSM_FFd1.D 10.000
fsb/BERR0r.Q fsb/BERR0r.D 10.000
fsb/BERR1r.Q fsb/BERR1r.D 10.000
fsb/Ready0r.Q fsb/Ready0r.D 10.000
iobs/Clear1.Q nADoutLE1.D 10.000
iobs/IOACTr.Q IOREQ.D 10.000
iobs/IOACTr.Q iobs/IOReady.D 10.000
iobs/IOACTr.Q iobs/PS_FSM_FFd1.D 10.000
iobs/IOACTr.Q iobs/PS_FSM_FFd2.D 10.000
iobs/IOL1.Q IOL0.D 10.000
iobs/IORW1.Q IORW0.D 10.000
iobs/IOReady.Q iobs/IOReady.D 10.000
iobs/IOU1.Q IOU0.D 10.000
iobs/Load1.Q iobs/IOL1.CE 10.000
iobs/Load1.Q iobs/IOU1.CE 10.000
iobs/Load1.Q nADoutLE1.D 10.000
iobs/Once.Q IOREQ.D 10.000
iobs/Once.Q iobs/IORW1.D 10.000
iobs/Once.Q iobs/IOReady.D 10.000
iobs/Once.Q iobs/Load1.D 10.000
iobs/Once.Q iobs/PS_FSM_FFd2.D 10.000
iobs/PS_FSM_FFd1.Q ALE0S.D 10.000
iobs/PS_FSM_FFd1.Q IOL0.CE 10.000
iobs/PS_FSM_FFd1.Q IOREQ.D 10.000
iobs/PS_FSM_FFd1.Q IOU0.CE 10.000
iobs/PS_FSM_FFd1.Q iobs/Clear1.D 10.000
iobs/PS_FSM_FFd1.Q iobs/Load1.D 10.000
iobs/PS_FSM_FFd1.Q iobs/PS_FSM_FFd1.D 10.000
iobs/PS_FSM_FFd2.Q ALE0S.D 10.000
iobs/PS_FSM_FFd2.Q IOL0.CE 10.000
iobs/PS_FSM_FFd2.Q IOU0.CE 10.000
iobs/PS_FSM_FFd2.Q iobs/Clear1.D 10.000
iobs/PS_FSM_FFd2.Q iobs/IOReady.D 10.000
iobs/PS_FSM_FFd2.Q iobs/Load1.D 10.000
iobs/PS_FSM_FFd2.Q iobs/PS_FSM_FFd1.D 10.000
nADoutLE1.Q IOL0.D 10.000
nADoutLE1.Q IOU0.D 10.000
nADoutLE1.Q iobs/Clear1.D 10.000
nADoutLE1.Q iobs/IORW1.D 10.000
nADoutLE1.Q iobs/IOReady.D 10.000
nADoutLE1.Q iobs/Load1.D 10.000
nADoutLE1.Q nADoutLE1.D 10.000
ram/BACTr.Q ram/RS_FSM_FFd2.D 10.000
ram/Once.Q ram/Once.D 10.000
ram/Once.Q ram/RS_FSM_FFd1.D 10.000
ram/Once.Q ram/RS_FSM_FFd3.D 10.000
ram/RAMReady.Q fsb/Ready0r.D 10.000
ram/RASEL.Q nCAS.D 10.000
ram/RS_FSM_FFd1.Q RefAck.D 10.000
ram/RS_FSM_FFd1.Q ram/Once.D 10.000
ram/RS_FSM_FFd1.Q ram/RS_FSM_FFd1.D 10.000
ram/RS_FSM_FFd2.Q RefAck.D 10.000
ram/RS_FSM_FFd2.Q ram/Once.D 10.000
ram/RS_FSM_FFd2.Q ram/RS_FSM_FFd1.D 10.000
ram/RS_FSM_FFd3.Q ram/Once.D 10.000
ram/RS_FSM_FFd3.Q ram/RS_FSM_FFd1.D 10.000

Clock to Setup for clock CLK2X_IOB
Source Destination Delay
IOACT.Q nVMA_IOB.D 11.000
IOBERR.Q IOBERR.D 11.000
iobm/BERRrf.Q IOBERR.D 11.000
iobm/BERRrr.Q IOBERR.D 11.000
iobm/DTACKrf.Q IOBERR.D 11.000
iobm/DTACKrr.Q IOBERR.D 11.000
iobm/ES<0>.Q nVMA_IOB.D 11.000
iobm/ES<1>.Q nVMA_IOB.D 11.000
iobm/ES<2>.Q nVMA_IOB.D 11.000
iobm/ES<3>.Q nVMA_IOB.D 11.000
iobm/ES<4>.Q nVMA_IOB.D 11.000
iobm/ETACK.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd1.Q IOACT.D 11.000
iobm/IOS_FSM_FFd1.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd2.Q IOACT.D 11.000
iobm/IOS_FSM_FFd2.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd3.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd4.Q IOACT.D 11.000
iobm/IOS_FSM_FFd4.Q IOBERR.D 11.000
iobm/IOS_FSM_FFd4.Q iobm/IOS_FSM_FFd3.D 11.000
iobm/RESrf.Q IOACT.D 11.000
iobm/RESrf.Q IOBERR.D 11.000
iobm/RESrf.Q iobm/IOS_FSM_FFd3.D 11.000
iobm/RESrr.Q IOACT.D 11.000
iobm/RESrr.Q IOBERR.D 11.000
iobm/RESrr.Q iobm/IOS_FSM_FFd3.D 11.000
iobm/VPArf.Q nVMA_IOB.D 11.000
iobm/VPArr.Q nVMA_IOB.D 11.000
nVMA_IOB.Q nVMA_IOB.D 11.000
iobm/BERRrf.Q IOACT.D 10.000
iobm/BERRrf.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/BERRrr.Q IOACT.D 10.000
iobm/BERRrr.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/DTACKrf.Q IOACT.D 10.000
iobm/DTACKrf.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/DTACKrr.Q IOACT.D 10.000
iobm/DTACKrr.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/ES<0>.Q iobm/ES<0>.D 10.000
iobm/ES<0>.Q iobm/ES<1>.D 10.000
iobm/ES<0>.Q iobm/ES<2>.D 10.000
iobm/ES<0>.Q iobm/ES<3>.D 10.000
iobm/ES<0>.Q iobm/ES<4>.D 10.000
iobm/ES<0>.Q iobm/ETACK.D 10.000
iobm/ES<1>.Q iobm/ES<0>.D 10.000
iobm/ES<1>.Q iobm/ES<1>.D 10.000
iobm/ES<1>.Q iobm/ES<2>.D 10.000
iobm/ES<1>.Q iobm/ES<3>.D 10.000
iobm/ES<1>.Q iobm/ES<4>.D 10.000
iobm/ES<1>.Q iobm/ETACK.D 10.000
iobm/ES<2>.Q iobm/ES<0>.D 10.000
iobm/ES<2>.Q iobm/ES<2>.D 10.000
iobm/ES<2>.Q iobm/ES<3>.D 10.000
iobm/ES<2>.Q iobm/ES<4>.D 10.000
iobm/ES<2>.Q iobm/ETACK.D 10.000
iobm/ES<3>.Q iobm/ES<0>.D 10.000
iobm/ES<3>.Q iobm/ES<2>.D 10.000
iobm/ES<3>.Q iobm/ES<3>.D 10.000
iobm/ES<3>.Q iobm/ES<4>.D 10.000
iobm/ES<3>.Q iobm/ETACK.D 10.000
iobm/ES<4>.Q iobm/ES<0>.D 10.000
iobm/ES<4>.Q iobm/ES<2>.D 10.000
iobm/ES<4>.Q iobm/ES<4>.D 10.000
iobm/ES<4>.Q iobm/ETACK.D 10.000
iobm/ETACK.Q IOACT.D 10.000
iobm/ETACK.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/Er2.Q iobm/ES<0>.D 10.000
iobm/Er2.Q iobm/ES<1>.D 10.000
iobm/Er2.Q iobm/ES<2>.D 10.000
iobm/Er2.Q iobm/ES<3>.D 10.000
iobm/Er2.Q iobm/ES<4>.D 10.000
iobm/IOREQr.Q ALE0M.D 10.000
iobm/IOREQr.Q IOACT.D 10.000
iobm/IOREQr.Q iobm/IOS_FSM_FFd4.D 10.000
iobm/IOS_FSM_FFd1.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd1.Q iobm/IOS_FSM_FFd4.D 10.000
iobm/IOS_FSM_FFd1.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd1.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd1.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd1.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd2.Q iobm/IOS_FSM_FFd4.D 10.000
iobm/IOS_FSM_FFd2.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q nDoutOE.D 10.000
iobm/IOS_FSM_FFd2.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd2.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd3.Q IOACT.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd3.D 10.000
iobm/IOS_FSM_FFd3.Q iobm/IOS_FSM_FFd4.D 10.000
iobm/IOS_FSM_FFd3.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd3.Q nDoutOE.D 10.000
iobm/IOS_FSM_FFd3.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd3.Q nUDS_IOB.D 10.000
iobm/IOS_FSM_FFd4.Q ALE0M.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/IOS_FSM_FFd1.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/IOS_FSM_FFd2.D 10.000
iobm/IOS_FSM_FFd4.Q iobm/IOS_FSM_FFd4.D 10.000
iobm/IOS_FSM_FFd4.Q nAS_IOB.D 10.000
iobm/IOS_FSM_FFd4.Q nDinLE.D 10.000
iobm/IOS_FSM_FFd4.Q nDoutOE.D 10.000
iobm/IOS_FSM_FFd4.Q nLDS_IOB.D 10.000
iobm/IOS_FSM_FFd4.Q nUDS_IOB.D 10.000
nVMA_IOB.Q iobm/ETACK.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
A_FSB<20> nBERR_FSB 11.000
A_FSB<20> nROMCS 11.000
A_FSB<21> nBERR_FSB 11.000
A_FSB<21> nRAS 11.000
A_FSB<21> nROMCS 11.000
A_FSB<22> nBERR_FSB 11.000
A_FSB<22> nRAS 11.000
A_FSB<23> nBERR_FSB 11.000
A_FSB<23> nRAS 11.000
A_FSB<23> nROMCS 11.000
nAS_FSB nRAS 11.000
A_FSB<10> RA<0> 10.000
A_FSB<11> RA<1> 10.000
A_FSB<12> RA<2> 10.000
A_FSB<13> RA<3> 10.000
A_FSB<14> RA<4> 10.000
A_FSB<15> RA<5> 10.000
A_FSB<16> RA<6> 10.000
A_FSB<17> RA<7> 10.000
A_FSB<18> RA<8> 10.000
A_FSB<19> RA<11> 10.000
A_FSB<19> RA<9> 10.000
A_FSB<1> RA<0> 10.000
A_FSB<20> RA<9> 10.000
A_FSB<20> nDinOE 10.000
A_FSB<21> RA<10> 10.000
A_FSB<21> nDinOE 10.000
A_FSB<22> nDinOE 10.000
A_FSB<22> nROMCS 10.000
A_FSB<23> nDinOE 10.000
A_FSB<2> RA<1> 10.000
A_FSB<3> RA<2> 10.000
A_FSB<4> RA<3> 10.000
A_FSB<5> RA<4> 10.000
A_FSB<6> RA<5> 10.000
A_FSB<7> RA<6> 10.000
A_FSB<8> RA<7> 10.000
A_FSB<9> RA<8> 10.000
nAS_FSB nBERR_FSB 10.000
nAS_FSB nDinOE 10.000
nAS_FSB nOE 10.000
nAS_FSB nRAMLWE 10.000
nAS_FSB nRAMUWE 10.000
nAS_FSB nROMWE 10.000
nAS_FSB nVPA_FSB 10.000
nLDS_FSB nRAMLWE 10.000
nUDS_FSB nRAMUWE 10.000
nWE_FSB nDinOE 10.000
nWE_FSB nOE 10.000
nWE_FSB nRAMLWE 10.000
nWE_FSB nRAMUWE 10.000
nWE_FSB nROMWE 10.000



Number of paths analyzed: 728
Number of Timing errors: 728
Analysis Completed: Mon Feb 07 00:05:04 2022