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Better CPLD stuff
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<html><body>
<pre>
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
idk
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Design Name: WarpSE Date: 3-20-2023, 11:54PM
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Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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121/144 ( 84%) 440 /720 ( 61%) 227/432 ( 53%) 96 /144 ( 67%) 72 /81 ( 89%)
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** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 25/54 26/90 11/11*
FB2 12/18 16/54 15/90 8/10
FB3 9/18 34/54 81/90 10/10*
FB4 18/18* 24/54 44/90 10/10*
FB5 16/18 30/54 77/90 8/10
FB6 18/18* 34/54 61/90 10/10*
FB7 18/18* 30/54 55/90 8/10
FB8 12/18 34/54 81/90 7/10
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----- ----- ----- -----
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121/144 227/432 440/720 72/81
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* - Resource is exhausted
** Global Control Resources **
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Signal 'C16M' mapped onto global clock net GCK1.
Signal 'C8M' mapped onto global clock net GCK2.
Signal 'FCLK' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
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Input : 33 33 | I/O : 66 73
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Output : 35 35 | GCK/IO : 3 3
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Bidirectional : 1 1 | GTS/IO : 3 4
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GCK : 3 3 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
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Total 72 72
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** Power Data **
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There are 121 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'WarpSE.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC
constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC
constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<1>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<2>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<3>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
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** 36 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
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nDTACK_FSB 11 26 FB3_9 28 I/O O STD FAST RESET
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nROMWE 1 2 FB3_17 34 I/O O STD FAST
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nAoutOE 1 3 FB4_2 87 I/O O STD FAST RESET
nDoutOE 1 2 FB4_5 89 I/O O STD FAST
nDinOE 2 6 FB4_6 90 I/O O STD FAST
nRES 1 1 FB4_8 91 I/O I/O STD FAST
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nVPA_FSB 1 2 FB4_11 93 I/O O STD FAST
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nROMCS 2 5 FB5_2 35 I/O O STD FAST
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nCAS 1 1 FB5_5 36 I/O O STD FAST RESET
nOE 1 2 FB5_6 37 I/O O STD FAST
RA<4> 2 3 FB5_9 40 I/O O STD FAST
RA<3> 2 3 FB5_11 41 I/O O STD FAST
RA<5> 2 3 FB5_12 42 I/O O STD FAST
RA<2> 2 3 FB5_14 43 I/O O STD FAST
RA<6> 2 3 FB5_15 46 I/O O STD FAST
nVMA_IOB 3 10 FB6_2 74 I/O O STD FAST RESET
nLDS_IOB 4 6 FB6_9 79 I/O O STD FAST RESET
nUDS_IOB 4 6 FB6_11 80 I/O O STD FAST RESET
nAS_IOB 3 4 FB6_12 81 I/O O STD FAST RESET
nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
RA<1> 2 3 FB7_2 50 I/O O STD FAST
RA<7> 2 3 FB7_5 52 I/O O STD FAST
RA<0> 2 3 FB7_6 53 I/O O STD FAST
RA<8> 7 7 FB7_8 54 I/O O STD FAST
RA<10> 1 1 FB7_9 55 I/O O STD FAST
RA<9> 2 3 FB7_11 56 I/O O STD FAST
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C25MEN 0 0 FB7_12 58 I/O O STD FAST
C20MEN 0 0 FB7_14 59 I/O O STD FAST
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RA<11> 1 1 FB8_2 63 I/O O STD FAST
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nRAS 3 7 FB8_5 64 I/O O STD FAST
nRAMLWE 1 4 FB8_6 65 I/O O STD FAST
nRAMUWE 1 4 FB8_8 66 I/O O STD FAST
nBERR_FSB 4 8 FB8_12 70 I/O O STD FAST RESET
nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET
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** 85 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
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iobm/nASr 1 2 FB1_1 STD RESET
iobm/VPArr 1 1 FB1_2 STD RESET
iobm/VPArf 1 1 FB1_3 STD RESET
iobm/RESrr 1 1 FB1_4 STD RESET
iobm/RESrf 1 1 FB1_5 STD RESET
iobm/IOREQr 1 1 FB1_6 STD RESET
iobm/Er2 1 1 FB1_7 STD RESET
iobm/Er 1 1 FB1_8 STD RESET
iobm/DTACKrr 1 1 FB1_9 STD RESET
iobm/DTACKrf 1 1 FB1_10 STD RESET
iobm/BERRrr 1 1 FB1_11 STD RESET
iobm/BERRrf 1 1 FB1_12 STD RESET
cnt/IPL2r 1 1 FB1_13 STD RESET
iobm/IOS_FSM_FFd1 2 3 FB1_14 STD RESET
iobm/BG 2 2 FB1_15 STD RESET
iobs/IOU0 3 5 FB1_16 STD RESET
iobs/IOL0 3 5 FB1_17 STD RESET
iobm/IOS_FSM_FFd3 3 6 FB1_18 STD RESET
ram/RegUrgentSync 1 1 FB2_7 STD RESET
ram/RefUrgent 1 2 FB2_8 STD RESET
ram/RefReqSync 1 1 FB2_9 STD RESET
ram/RefReq 1 2 FB2_10 STD RESET
ram/RefRAS 1 2 FB2_11 STD RESET
ram/BACTr 1 2 FB2_12 STD RESET
iobs/IOACTr 1 1 FB2_13 STD RESET
iobs/ALE0 1 2 FB2_14 STD RESET
fsb/ASrf 1 1 FB2_15 STD RESET
iobs/PS_FSM_FFd1 2 3 FB2_16 STD RESET
iobs/IOU1 2 2 FB2_17 STD RESET
iobs/IOL1 2 2 FB2_18 STD RESET
fsb/VPA 20 26 FB3_2 STD RESET
iobs/Clear1 1 3 FB3_5 STD RESET
fsb/Ready0r 3 8 FB3_6 STD RESET
iobs/IOReady 4 8 FB3_7 STD RESET
fsb/Ready1r 7 17 FB3_10 STD RESET
iobs/IORW1 16 19 FB3_12 STD RESET
iobs/IORW0 18 20 FB3_15 STD RESET
cnt/nRESout 2 4 FB4_1 STD RESET
cnt/TimerTC 2 5 FB4_3 STD RESET
cnt/Timer<0> 2 3 FB4_4 STD RESET
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
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cnt/PORS_FSM_FFd2 2 3 FB4_7 STD RESET
cnt/LTimer<0> 2 3 FB4_9 STD RESET
cnt/Timer<3> 3 6 FB4_10 STD RESET
cnt/Timer<2> 3 5 FB4_12 STD RESET
cnt/Timer<1> 3 4 FB4_13 STD RESET
cnt/RefUrgent 3 5 FB4_14 STD RESET
cnt/RefReq 4 5 FB4_15 STD RESET
cnt/LTimer<3> 4 6 FB4_16 STD RESET
cnt/LTimer<2> 4 5 FB4_17 STD RESET
cnt/LTimer<1> 4 4 FB4_18 STD RESET
ram/RASEL 17 13 FB5_1 STD RESET
ram/RefDone 2 4 FB5_3 STD RESET
cs/nOverlay1 2 3 FB5_4 STD RESET
ram/RS_FSM_FFd1 8 11 FB5_7 STD RESET
cs/nOverlay0 3 8 FB5_8 STD RESET
ram/RAMEN 9 13 FB5_10 STD RESET
ram/RS_FSM_FFd2 10 12 FB5_13 STD RESET
ram/RAMReady 12 13 FB5_17 STD RESET
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iobm/ETACK 1 6 FB6_1 STD RESET
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iobm/DoutOE 2 3 FB6_3 STD RESET
iobm/ALE0 2 4 FB6_4 STD RESET
iobm/ES<3> 3 6 FB6_5 STD RESET
iobm/ES<1> 3 4 FB6_6 STD RESET
iobm/ES<0> 3 7 FB6_7 STD RESET
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iobm/ES<4> 4 7 FB6_8 STD RESET
iobm/IOS_FSM_FFd2 5 11 FB6_10 STD RESET
iobm/ES<2> 5 7 FB6_13 STD RESET
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iobm/IOACT 6 12 FB6_16 STD RESET
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iobm/IOBERR 9 13 FB6_18 STD RESET
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cnt/LTimer<13> 3 15 FB7_1 STD RESET
cnt/LTimer<9> 4 12 FB7_3 STD RESET
cnt/LTimer<8> 4 11 FB7_4 STD RESET
cnt/LTimer<7> 4 10 FB7_7 STD RESET
cnt/LTimer<6> 4 9 FB7_10 STD RESET
cnt/LTimer<5> 4 8 FB7_13 STD RESET
cnt/LTimer<4> 4 7 FB7_15 STD RESET
cnt/LTimer<12> 4 15 FB7_16 STD RESET
cnt/LTimer<11> 4 14 FB7_17 STD RESET
cnt/LTimer<10> 4 13 FB7_18 STD RESET
cnt/PORS_FSM_FFd1 1 4 FB8_1 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
ram/RS_FSM_FFd3 9 11 FB8_3 STD RESET
iobs/PS_FSM_FFd2 14 19 FB8_7 STD RESET
iobs/Load1 14 18 FB8_10 STD RESET
iobs/IOREQ 14 19 FB8_14 STD RESET
iobs/Once 17 18 FB8_17 STD RESET
** 36 Inputs **
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Signal Loc Pin Pin Pin
Name No. Type Use
A_FSB<13> FB1_2 11 I/O I
A_FSB<14> FB1_3 12 I/O I
A_FSB<15> FB1_5 13 I/O I
A_FSB<16> FB1_6 14 I/O I
A_FSB<17> FB1_8 15 I/O I
A_FSB<18> FB1_9 16 I/O I
A_FSB<19> FB1_11 17 I/O I
A_FSB<20> FB1_12 18 I/O I
A_FSB<21> FB1_14 19 I/O I
A_FSB<22> FB1_15 20 I/O I
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C16M FB1_17 22 GCK/I/O GCK
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A_FSB<5> FB2_6 2 GTS/I/O I
A_FSB<6> FB2_8 3 GTS/I/O I
A_FSB<7> FB2_9 4 GTS/I/O I
A_FSB<8> FB2_11 6 I/O I
A_FSB<9> FB2_12 7 I/O I
A_FSB<10> FB2_14 8 I/O I
A_FSB<11> FB2_15 9 I/O I
A_FSB<12> FB2_17 10 I/O I
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C8M FB3_2 23 GCK/I/O GCK/I
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A_FSB<23> FB3_5 24 I/O I
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E FB3_6 25 I/O I
FCLK FB3_8 27 GCK/I/O GCK
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nWE_FSB FB3_11 29 I/O I
nLDS_FSB FB3_12 30 I/O I
nAS_FSB FB3_14 32 I/O I
nUDS_FSB FB3_15 33 I/O I
nIPL2 FB4_9 92 I/O I
A_FSB<1> FB4_12 94 I/O I
A_FSB<2> FB4_14 95 I/O I
A_FSB<3> FB4_15 96 I/O I
A_FSB<4> FB4_17 97 I/O I
nBERR_IOB FB6_5 76 I/O I
nVPA_IOB FB6_6 77 I/O I
nDTACK_IOB FB6_8 78 I/O I
nBG_IOB FB8_17 73 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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iobm/nASr 1 0 0 4 FB1_1 (b) (b)
iobm/VPArr 1 0 0 4 FB1_2 11 I/O I
iobm/VPArf 1 0 0 4 FB1_3 12 I/O I
iobm/RESrr 1 0 0 4 FB1_4 (b) (b)
iobm/RESrf 1 0 0 4 FB1_5 13 I/O I
iobm/IOREQr 1 0 0 4 FB1_6 14 I/O I
iobm/Er2 1 0 0 4 FB1_7 (b) (b)
iobm/Er 1 0 0 4 FB1_8 15 I/O I
iobm/DTACKrr 1 0 0 4 FB1_9 16 I/O I
iobm/DTACKrf 1 0 0 4 FB1_10 (b) (b)
iobm/BERRrr 1 0 0 4 FB1_11 17 I/O I
iobm/BERRrf 1 0 0 4 FB1_12 18 I/O I
cnt/IPL2r 1 0 0 4 FB1_13 (b) (b)
iobm/IOS_FSM_FFd1 2 0 0 3 FB1_14 19 I/O I
iobm/BG 2 0 0 3 FB1_15 20 I/O I
iobs/IOU0 3 0 0 2 FB1_16 (b) (b)
iobs/IOL0 3 0 0 2 FB1_17 22 GCK/I/O GCK
iobm/IOS_FSM_FFd3 3 0 0 2 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: C8M 10: iobm/nASr 18: nAoutOE
2: E 11: iobs/IOL1 19: nBERR_IOB
3: nRES.PIN 12: iobs/IOREQ 20: nBG_IOB
4: iobm/BG 13: iobs/IOU1 21: nDTACK_IOB
5: iobm/Er 14: iobs/PS_FSM_FFd1 22: nIPL2
6: iobm/IOREQr 15: iobs/PS_FSM_FFd2 23: nLDS_FSB
7: iobm/IOS_FSM_FFd1 16: nADoutLE1 24: nUDS_FSB
8: iobm/IOS_FSM_FFd2 17: nAS_IOB 25: nVPA_IOB
9: iobm/IOS_FSM_FFd3
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
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iobm/nASr ................XX...................... 2
iobm/VPArr ........................X............... 1
iobm/VPArf ........................X............... 1
iobm/RESrr ..X..................................... 1
iobm/RESrf ..X..................................... 1
iobm/IOREQr ...........X............................ 1
iobm/Er2 ....X................................... 1
iobm/Er .X...................................... 1
iobm/DTACKrr ....................X................... 1
iobm/DTACKrf ....................X................... 1
iobm/BERRrr ..................X..................... 1
iobm/BERRrf ..................X..................... 1
cnt/IPL2r .....................X.................. 1
iobm/IOS_FSM_FFd1 ......XXX............................... 3
iobm/BG .........X.........X.................... 2
iobs/IOU0 ............XXXX.......X................ 5
iobs/IOL0 ..........X..XXX......X................. 5
iobm/IOS_FSM_FFd3 X..X.XXXX............................... 6
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
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Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
(unused) 0 0 0 5 FB2_6 2 GTS/I/O I
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ram/RegUrgentSync 1 0 0 4 FB2_7 (b) (b)
ram/RefUrgent 1 0 0 4 FB2_8 3 GTS/I/O I
ram/RefReqSync 1 0 0 4 FB2_9 4 GTS/I/O I
ram/RefReq 1 0 0 4 FB2_10 (b) (b)
ram/RefRAS 1 0 0 4 FB2_11 6 I/O I
ram/BACTr 1 0 0 4 FB2_12 7 I/O I
iobs/IOACTr 1 0 0 4 FB2_13 (b) (b)
iobs/ALE0 1 0 0 4 FB2_14 8 I/O I
fsb/ASrf 1 0 0 4 FB2_15 9 I/O I
iobs/PS_FSM_FFd1 2 0 0 3 FB2_16 (b) (b)
iobs/IOU1 2 0 0 3 FB2_17 10 I/O I
iobs/IOL1 2 0 0 3 FB2_18 (b) (b)
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Signals Used by Logic in Function Block
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1: cnt/RefReq 7: iobs/PS_FSM_FFd1 12: ram/RS_FSM_FFd1
2: cnt/RefUrgent 8: iobs/PS_FSM_FFd2 13: ram/RS_FSM_FFd2
3: fsb/ASrf 9: nAS_FSB 14: ram/RefDone
4: iobm/IOACT 10: nLDS_FSB 15: ram/RefReqSync
5: iobs/IOACTr 11: nUDS_FSB 16: ram/RegUrgentSync
6: iobs/Load1
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
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ram/RegUrgentSync .X...................................... 1
ram/RefUrgent .............X.X........................ 2
ram/RefReqSync X....................................... 1
ram/RefReq .............XX......................... 2
ram/RefRAS ...........XX........................... 2
ram/BACTr ..X.....X............................... 2
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iobs/IOACTr ...X.................................... 1
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iobs/ALE0 ......XX................................ 2
fsb/ASrf ........X............................... 1
iobs/PS_FSM_FFd1 ....X.XX................................ 3
iobs/IOU1 .....X....X............................. 2
iobs/IOL1 .....X...X.............................. 2
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
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Number of function block inputs used/remaining: 34/20
Number of signals used by logic mapping into function block: 34
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-21 21:11:58 -04:00
(unused) 0 0 \/5 0 FB3_1 (b) (b)
fsb/VPA 20 15<- 0 0 FB3_2 23 GCK/I/O GCK/I
Better CPLD stuff
2022-03-29 04:23:54 -04:00
(unused) 0 0 /\5 0 FB3_3 (b) (b)
idk
2023-03-21 21:11:58 -04:00
(unused) 0 0 0 5 FB3_4 (b)
iobs/Clear1 1 0 \/1 3 FB3_5 24 I/O I
fsb/Ready0r 3 1<- \/3 0 FB3_6 25 I/O I
iobs/IOReady 4 3<- \/4 0 FB3_7 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
(unused) 0 0 \/5 0 FB3_8 27 GCK/I/O GCK
idk
2023-03-21 21:11:58 -04:00
nDTACK_FSB 11 9<- \/3 0 FB3_9 28 I/O O
fsb/Ready1r 7 3<- \/1 0 FB3_10 (b) (b)
(unused) 0 0 \/5 0 FB3_11 29 I/O I
iobs/IORW1 16 11<- 0 0 FB3_12 30 I/O I
(unused) 0 0 /\5 0 FB3_13 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
(unused) 0 0 \/5 0 FB3_14 32 I/O I
idk
2023-03-21 21:11:58 -04:00
iobs/IORW0 18 13<- 0 0 FB3_15 33 I/O I
(unused) 0 0 /\5 0 FB3_16 (b) (b)
nROMWE 1 0 /\3 1 FB3_17 34 I/O O
Better CPLD stuff
2022-03-29 04:23:54 -04:00
(unused) 0 0 \/5 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
idk
2023-03-21 21:11:58 -04:00
1: A_FSB<10> 13: A_FSB<22> 24: iobs/IORW0
2: A_FSB<11> 14: A_FSB<23> 25: iobs/IORW1
3: A_FSB<12> 15: A_FSB<8> 26: iobs/IOReady
4: A_FSB<13> 16: A_FSB<9> 27: iobs/Once
5: A_FSB<14> 17: cs/nOverlay1 28: iobs/PS_FSM_FFd1
6: A_FSB<15> 18: fsb/ASrf 29: iobs/PS_FSM_FFd2
7: A_FSB<16> 19: fsb/Ready0r 30: nADoutLE1
8: A_FSB<17> 20: fsb/Ready1r 31: nAS_FSB
9: A_FSB<18> 21: fsb/VPA 32: nDTACK_FSB
10: A_FSB<19> 22: iobm/IOBERR 33: nWE_FSB
11: A_FSB<20> 23: iobs/IOACTr 34: ram/RAMReady
12: A_FSB<21>
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
idk
2023-03-21 21:11:58 -04:00
fsb/VPA XXXXXXXXXXXXXXXXXXXXX....X...XX.XX...... 26
iobs/Clear1 ...........................XXX.......... 3
fsb/Ready0r ...........XXX..XXX...........X..X...... 8
iobs/IOReady .................X...XX..XX.XXX......... 8
nDTACK_FSB XXXXXXXXXXXXXXXXXXXX.....X...XXXXX...... 26
fsb/Ready1r ...XX.XXXXXXXX..XX.X.....X...XX.X....... 17
iobs/IORW1 ...XX.XXXXXXXX..XX......X.XXXXX.X....... 19
iobs/IORW0 ...XX.XXXXXXXX..XX.....XX.XXXXX.X....... 20
nROMWE ..............................X.X....... 2
Better CPLD stuff
2022-03-29 04:23:54 -04:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
idk
2023-03-21 21:11:58 -04:00
Number of function block inputs used/remaining: 24/30
Number of signals used by logic mapping into function block: 24
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-21 21:11:58 -04:00
cnt/nRESout 2 0 0 3 FB4_1 (b) (b)
nAoutOE 1 0 0 4 FB4_2 87 I/O O
cnt/TimerTC 2 0 0 3 FB4_3 (b) (b)
cnt/Timer<0> 2 0 0 3 FB4_4 (b) (b)
nDoutOE 1 0 0 4 FB4_5 89 I/O O
nDinOE 2 0 0 3 FB4_6 90 I/O O
cnt/PORS_FSM_FFd2 2 0 0 3 FB4_7 (b) (b)
nRES 1 0 0 4 FB4_8 91 I/O I/O
cnt/LTimer<0> 2 0 0 3 FB4_9 92 I/O I
cnt/Timer<3> 3 0 0 2 FB4_10 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
nVPA_FSB 1 0 0 4 FB4_11 93 I/O O
idk
2023-03-21 21:11:58 -04:00
cnt/Timer<2> 3 0 0 2 FB4_12 94 I/O I
cnt/Timer<1> 3 0 0 2 FB4_13 (b) (b)
cnt/RefUrgent 3 0 0 2 FB4_14 95 I/O I
cnt/RefReq 4 0 0 1 FB4_15 96 I/O I
cnt/LTimer<3> 4 0 0 1 FB4_16 (b) (b)
cnt/LTimer<2> 4 0 0 1 FB4_17 97 I/O I
cnt/LTimer<1> 4 0 0 1 FB4_18 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signals Used by Logic in Function Block
idk
2023-03-21 21:11:58 -04:00
1: A_FSB<20> 9: cnt/LTimer<2> 17: cnt/TimerTC
2: A_FSB<21> 10: cnt/LTimer<3> 18: cnt/nRESout
3: A_FSB<22> 11: cnt/PORS_FSM_FFd1 19: fsb/VPA
4: A_FSB<23> 12: cnt/PORS_FSM_FFd2 20: iobm/DoutOE
5: E 13: cnt/Timer<0> 21: nAS_FSB
6: cnt/LTimer<0> 14: cnt/Timer<1> 22: nAoutOE
7: cnt/LTimer<13> 15: cnt/Timer<2> 23: nBR_IOB
8: cnt/LTimer<1> 16: cnt/Timer<3> 24: nWE_FSB
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt/nRESout ......X...XX.....X...................... 4
nAoutOE ..........XX..........X................. 3
cnt/TimerTC ....X.......XXXX........................ 5
cnt/Timer<0> ....X.......X...X....................... 3
nDoutOE ...................X.X.................. 2
nDinOE XXXX................X..X................ 6
cnt/PORS_FSM_FFd2 ......X...XX............................ 3
nRES .................X...................... 1
cnt/LTimer<0> .....XX.........X....................... 3
cnt/Timer<3> ....X.......XXXXX....................... 6
nVPA_FSB ..................X.X................... 2
cnt/Timer<2> ....X.......XXX.X....................... 5
cnt/Timer<1> ....X.......XX..X....................... 4
cnt/RefUrgent ....X.......XXXX........................ 5
cnt/RefReq ....X.......XXXX........................ 5
cnt/LTimer<3> .....XXXXX......X....................... 6
cnt/LTimer<2> .....XXXX.......X....................... 5
cnt/LTimer<1> .....XXX........X....................... 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Better CPLD stuff
2022-03-29 04:23:54 -04:00
*********************************** FB5 ***********************************
idk
2023-03-21 21:11:58 -04:00
Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-21 21:11:58 -04:00
ram/RASEL 17 12<- 0 0 FB5_1 (b) (b)
nROMCS 2 2<- /\5 0 FB5_2 35 I/O O
ram/RefDone 2 0 /\2 1 FB5_3 (b) (b)
cs/nOverlay1 2 0 0 3 FB5_4 (b) (b)
nCAS 1 0 0 4 FB5_5 36 I/O O
nOE 1 0 \/3 1 FB5_6 37 I/O O
ram/RS_FSM_FFd1 8 3<- 0 0 FB5_7 (b) (b)
cs/nOverlay0 3 0 \/1 1 FB5_8 39 I/O (b)
RA<4> 2 1<- \/4 0 FB5_9 40 I/O O
ram/RAMEN 9 4<- 0 0 FB5_10 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
RA<3> 2 0 \/2 1 FB5_11 41 I/O O
RA<5> 2 2<- \/5 0 FB5_12 42 I/O O
idk
2023-03-21 21:11:58 -04:00
ram/RS_FSM_FFd2 10 5<- 0 0 FB5_13 (b) (b)
RA<2> 2 0 \/1 2 FB5_14 43 I/O O
RA<6> 2 1<- \/4 0 FB5_15 46 I/O O
(unused) 0 0 \/5 0 FB5_16 (b) (b)
ram/RAMReady 12 9<- \/2 0 FB5_17 49 I/O (b)
(unused) 0 0 \/5 0 FB5_18 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signals Used by Logic in Function Block
idk
2023-03-21 21:11:58 -04:00
1: A_FSB<12> 11: A_FSB<4> 21: ram/BACTr
2: A_FSB<13> 12: A_FSB<5> 22: ram/RAMEN
3: A_FSB<14> 13: A_FSB<6> 23: ram/RASEL
4: A_FSB<15> 14: A_FSB<7> 24: ram/RS_FSM_FFd1
5: A_FSB<16> 15: nRES.PIN 25: ram/RS_FSM_FFd2
6: A_FSB<20> 16: cs/nOverlay0 26: ram/RS_FSM_FFd3
7: A_FSB<21> 17: cs/nOverlay1 27: ram/RefDone
8: A_FSB<22> 18: fsb/ASrf 28: ram/RefReq
9: A_FSB<23> 19: nAS_FSB 29: ram/RefReqSync
10: A_FSB<3> 20: nWE_FSB 30: ram/RefUrgent
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
idk
2023-03-21 21:11:58 -04:00
ram/RASEL ......XXX.......XXX.XX.XXX.X.X.......... 13
nROMCS .....XXXX.......X....................... 5
ram/RefDone .......................XX.X.X........... 4
cs/nOverlay1 ...............X.XX..................... 3
nCAS ......................X................. 1
nOE ..................XX.................... 2
ram/RS_FSM_FFd1 ......XXX.......XXX..X.XXX...X.......... 11
cs/nOverlay0 .....XXXX.....XX.XX..................... 8
RA<4> ..X........X..........X................. 3
ram/RAMEN ......XXX.......XXX.XX.XXX.X.X.......... 13
RA<3> .X........X...........X................. 3
RA<5> ...X........X.........X................. 3
ram/RS_FSM_FFd2 ......XXX.......XXX.X..XXX.X.X.......... 12
RA<2> X........X............X................. 3
RA<6> ....X........X........X................. 3
ram/RAMReady ......XXX.......XXX.XX.XXX.X.X.......... 13
Better CPLD stuff
2022-03-29 04:23:54 -04:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 34/20
Number of signals used by logic mapping into function block: 34
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-21 21:11:58 -04:00
iobm/ETACK 1 0 0 4 FB6_1 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
idk
2023-03-21 21:11:58 -04:00
iobm/DoutOE 2 0 0 3 FB6_3 (b) (b)
iobm/ALE0 2 0 0 3 FB6_4 (b) (b)
iobm/ES<3> 3 0 0 2 FB6_5 76 I/O I
iobm/ES<1> 3 0 0 2 FB6_6 77 I/O I
iobm/ES<0> 3 0 0 2 FB6_7 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
iobm/ES<4> 4 0 0 1 FB6_8 78 I/O I
nLDS_IOB 4 0 0 1 FB6_9 79 I/O O
iobm/IOS_FSM_FFd2 5 0 0 0 FB6_10 (b) (b)
nUDS_IOB 4 0 0 1 FB6_11 80 I/O O
nAS_IOB 3 0 0 2 FB6_12 81 I/O O
iobm/ES<2> 5 0 0 0 FB6_13 (b) (b)
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
nADoutLE0 1 0 \/1 3 FB6_15 85 I/O O
idk
2023-03-21 21:11:58 -04:00
iobm/IOACT 6 1<- 0 0 FB6_16 (b) (b)
nDinLE 1 0 \/4 0 FB6_17 86 I/O O
Better CPLD stuff
2022-03-29 04:23:54 -04:00
iobm/IOBERR 9 4<- 0 0 FB6_18 (b) (b)
Signals Used by Logic in Function Block
idk
2023-03-21 21:11:58 -04:00
1: C8M 13: iobm/Er 24: iobm/VPArr
Better CPLD stuff
2022-03-29 04:23:54 -04:00
2: iobm/ALE0 14: iobm/Er2 25: iobs/ALE0
3: iobm/BERRrf 15: iobm/IOACT 26: iobs/Clear1
4: iobm/BERRrr 16: iobm/IOBERR 27: iobs/IOL0
5: iobm/DTACKrf 17: iobm/IOREQr 28: iobs/IORW0
6: iobm/DTACKrr 18: iobm/IOS_FSM_FFd1 29: iobs/IOU0
7: iobm/ES<0> 19: iobm/IOS_FSM_FFd2 30: iobs/Load1
8: iobm/ES<1> 20: iobm/IOS_FSM_FFd3 31: nADoutLE1
9: iobm/ES<2> 21: iobm/RESrf 32: nAoutOE
10: iobm/ES<3> 22: iobm/RESrr 33: nBERR_IOB
11: iobm/ES<4> 23: iobm/VPArf 34: nVMA_IOB
12: iobm/ETACK
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
iobm/ETACK ......XXXXX......................X...... 6
nVMA_IOB ......XXXXX...X.......XX.......X.X...... 10
idk
2023-03-21 21:11:58 -04:00
iobm/DoutOE ..................XX.......X............ 3
iobm/ALE0 ................XXXX.................... 4
Better CPLD stuff
2022-03-29 04:23:54 -04:00
iobm/ES<3> ......XXXX..XX.......................... 6
iobm/ES<1> ......XX....XX.......................... 4
iobm/ES<0> ......XXXXX.XX.......................... 7
iobm/ES<4> ......XXXXX.XX.......................... 7
nLDS_IOB .................XXX......XX...X........ 6
iobm/IOS_FSM_FFd2 X.XXXX.....X.....XXXXX.................. 11
nUDS_IOB .................XXX.......XX..X........ 6
nAS_IOB .................XXX...........X........ 4
iobm/ES<2> ......XXXXX.XX.......................... 7
nADoutLE1 .........................X...XX......... 3
nADoutLE0 .X......................X............... 2
idk
2023-03-21 21:11:58 -04:00
iobm/IOACT X.XXXX.....X....XXXXXX.................. 12
Better CPLD stuff
2022-03-29 04:23:54 -04:00
nDinLE .................XX..................... 2
iobm/IOBERR X.XXXX.....X...X.XXXXX..........X....... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
idk
2023-03-21 21:11:58 -04:00
Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-21 21:11:58 -04:00
cnt/LTimer<13> 3 0 0 2 FB7_1 (b) (b)
RA<1> 2 0 0 3 FB7_2 50 I/O O
cnt/LTimer<9> 4 0 0 1 FB7_3 (b) (b)
cnt/LTimer<8> 4 0 0 1 FB7_4 (b) (b)
RA<7> 2 0 0 3 FB7_5 52 I/O O
Better CPLD stuff
2022-03-29 04:23:54 -04:00
RA<0> 2 0 0 3 FB7_6 53 I/O O
idk
2023-03-21 21:11:58 -04:00
cnt/LTimer<7> 4 0 \/1 0 FB7_7 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
RA<8> 7 2<- 0 0 FB7_8 54 I/O O
idk
2023-03-21 21:11:58 -04:00
RA<10> 1 0 /\1 3 FB7_9 55 I/O O
cnt/LTimer<6> 4 0 0 1 FB7_10 (b) (b)
RA<9> 2 0 0 3 FB7_11 56 I/O O
C25MEN 0 0 0 5 FB7_12 58 I/O O
cnt/LTimer<5> 4 0 0 1 FB7_13 (b) (b)
C20MEN 0 0 0 5 FB7_14 59 I/O O
cnt/LTimer<4> 4 0 0 1 FB7_15 60 I/O (b)
cnt/LTimer<12> 4 0 0 1 FB7_16 (b) (b)
cnt/LTimer<11> 4 0 0 1 FB7_17 61 I/O (b)
cnt/LTimer<10> 4 0 0 1 FB7_18 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signals Used by Logic in Function Block
idk
2023-03-21 21:11:58 -04:00
1: A_FSB<10> 11: A_FSB<2> 21: cnt/LTimer<3>
2: A_FSB<11> 12: A_FSB<8> 22: cnt/LTimer<4>
3: A_FSB<17> 13: A_FSB<9> 23: cnt/LTimer<5>
4: A_FSB<18> 14: cnt/LTimer<0> 24: cnt/LTimer<6>
5: A_FSB<19> 15: cnt/LTimer<10> 25: cnt/LTimer<7>
6: A_FSB<1> 16: cnt/LTimer<11> 26: cnt/LTimer<8>
7: A_FSB<20> 17: cnt/LTimer<12> 27: cnt/LTimer<9>
8: A_FSB<21> 18: cnt/LTimer<13> 28: cnt/TimerTC
9: A_FSB<22> 19: cnt/LTimer<1> 29: cs/nOverlay1
10: A_FSB<23> 20: cnt/LTimer<2> 30: ram/RASEL
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
idk
2023-03-21 21:11:58 -04:00
cnt/LTimer<13> .............XXXXXXXXXXXXXXX............ 15
RA<1> .X........X..................X.......... 3
cnt/LTimer<9> .............X...XXXXXXXXXXX............ 12
cnt/LTimer<8> .............X...XXXXXXXXX.X............ 11
RA<7> ..X........X.................X.......... 3
RA<0> X....X.......................X.......... 3
cnt/LTimer<7> .............X...XXXXXXXX..X............ 10
RA<8> ...X...XXX..X...............XX.......... 7
Better CPLD stuff
2022-03-29 04:23:54 -04:00
RA<10> .......X................................ 1
idk
2023-03-21 21:11:58 -04:00
cnt/LTimer<6> .............X...XXXXXXX...X............ 9
RA<9> ....X.X......................X.......... 3
C25MEN ........................................ 0
cnt/LTimer<5> .............X...XXXXXX....X............ 8
C20MEN ........................................ 0
cnt/LTimer<4> .............X...XXXXX.....X............ 7
cnt/LTimer<12> .............XXXXXXXXXXXXXXX............ 15
cnt/LTimer<11> .............XXX.XXXXXXXXXXX............ 14
cnt/LTimer<10> .............XX..XXXXXXXXXXX............ 13
Better CPLD stuff
2022-03-29 04:23:54 -04:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
idk
2023-03-21 21:11:58 -04:00
Number of function block inputs used/remaining: 34/20
Number of signals used by logic mapping into function block: 34
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-21 21:11:58 -04:00
cnt/PORS_FSM_FFd1 1 0 /\2 2 FB8_1 (b) (b)
RA<11> 1 0 \/4 0 FB8_2 63 I/O O
ram/RS_FSM_FFd3 9 4<- 0 0 FB8_3 (b) (b)
(unused) 0 0 0 5 FB8_4 (b)
nRAS 3 0 \/1 1 FB8_5 64 I/O O
nRAMLWE 1 1<- \/5 0 FB8_6 65 I/O O
iobs/PS_FSM_FFd2 14 9<- 0 0 FB8_7 (b) (b)
nRAMUWE 1 0 /\4 0 FB8_8 66 I/O O
(unused) 0 0 \/4 1 FB8_9 67 I/O (b)
iobs/Load1 14 9<- 0 0 FB8_10 (b) (b)
(unused) 0 0 /\5 0 FB8_11 68 I/O (b)
nBERR_FSB 4 0 \/1 0 FB8_12 70 I/O O
Better CPLD stuff
2022-03-29 04:23:54 -04:00
(unused) 0 0 \/5 0 FB8_13 (b) (b)
idk
2023-03-21 21:11:58 -04:00
iobs/IOREQ 14 9<- 0 0 FB8_14 71 I/O (b)
nBR_IOB 2 0 /\3 0 FB8_15 72 I/O O
(unused) 0 0 \/5 0 FB8_16 (b) (b)
iobs/Once 17 12<- 0 0 FB8_17 73 I/O I
(unused) 0 0 /\5 0 FB8_18 (b) (b)
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signals Used by Logic in Function Block
idk
2023-03-21 21:11:58 -04:00
1: A_FSB<13> 13: cnt/PORS_FSM_FFd1 24: nBERR_FSB
2: A_FSB<14> 14: cnt/PORS_FSM_FFd2 25: nBR_IOB
3: A_FSB<16> 15: cs/nOverlay1 26: nLDS_FSB
4: A_FSB<17> 16: fsb/ASrf 27: nUDS_FSB
5: A_FSB<18> 17: iobm/IOBERR 28: nWE_FSB
6: A_FSB<19> 18: iobs/IOACTr 29: ram/RAMEN
7: A_FSB<20> 19: iobs/Once 30: ram/RS_FSM_FFd1
8: A_FSB<21> 20: iobs/PS_FSM_FFd1 31: ram/RS_FSM_FFd2
9: A_FSB<22> 21: iobs/PS_FSM_FFd2 32: ram/RS_FSM_FFd3
10: A_FSB<23> 22: nADoutLE1 33: ram/RefRAS
11: cnt/IPL2r 23: nAS_FSB 34: ram/RefUrgent
12: cnt/LTimer<13>
Better CPLD stuff
2022-03-29 04:23:54 -04:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
idk
2023-03-21 21:11:58 -04:00
cnt/PORS_FSM_FFd1 ..........XXXX.......................... 4
Better CPLD stuff
2022-03-29 04:23:54 -04:00
RA<11> .....X.................................. 1
idk
2023-03-21 21:11:58 -04:00
ram/RS_FSM_FFd3 .......XXX....XX......X.....XXXX.X...... 11
nRAS .......XXX....X.......X.....X...X....... 7
nRAMLWE ......................X..X.XX........... 4
iobs/PS_FSM_FFd2 XXXXXXXXXX....XX.XXXXXX....X............ 19
nRAMUWE ......................X...XXX........... 4
iobs/Load1 XXXXXXXXXX....XX..XXXXX....X............ 18
nBERR_FSB ...............XXXX.XXXX................ 8
iobs/IOREQ XXXXXXXXXX....XX.XXXXXX....X............ 19
nBR_IOB ..........X.XX..........X............... 4
iobs/Once XXXXXXXXXX....XX..XXXXX....X............ 18
Better CPLD stuff
2022-03-29 04:23:54 -04:00
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
idk
2023-03-21 21:11:58 -04:00
assign C20MEN = 1'b1;
Better CPLD stuff
2022-03-29 04:23:54 -04:00
idk
2023-03-21 21:11:58 -04:00
assign C25MEN = 1'b1;
Better CPLD stuff
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assign RA[0] = ((A_FSB[10] && !ram/RASEL)
|| (ram/RASEL && A_FSB[1]));
assign RA[1] = ((A_FSB[11] && !ram/RASEL)
|| (ram/RASEL && A_FSB[2]));
assign RA[2] = ((A_FSB[12] && !ram/RASEL)
|| (ram/RASEL && A_FSB[3]));
assign RA[3] = ((A_FSB[13] && !ram/RASEL)
|| (ram/RASEL && A_FSB[4]));
idk
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assign RA[4] = ((ram/RASEL && A_FSB[5])
|| (A_FSB[14] && !ram/RASEL));
Better CPLD stuff
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assign RA[5] = ((A_FSB[15] && !ram/RASEL)
|| (ram/RASEL && A_FSB[6]));
idk
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assign RA[6] = ((ram/RASEL && A_FSB[7])
|| (A_FSB[16] && !ram/RASEL));
Better CPLD stuff
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assign RA[7] = ((A_FSB[8] && ram/RASEL)
|| (A_FSB[17] && !ram/RASEL));
assign RA[8] = ((A_FSB[9] && !A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
ram/RASEL)
|| (A_FSB[9] && !A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && ram/RASEL)
|| (A_FSB[23] && A_FSB[18])
|| (A_FSB[18] && !ram/RASEL)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[18])
|| (A_FSB[22] && A_FSB[18] && cs/nOverlay1)
|| (!A_FSB[22] && A_FSB[18] && !cs/nOverlay1));
assign RA[9] = ((A_FSB[20] && ram/RASEL)
|| (A_FSB[19] && !ram/RASEL));
assign RA[10] = A_FSB[21];
assign RA[11] = A_FSB[19];
idk
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FDCPE FDCPE_cnt/IPL2r (cnt/IPL2r,!nIPL2,!C8M,1'b0,1'b0);
FTCPE FTCPE_cnt/LTimer0 (cnt/LTimer[0],cnt/LTimer_T[0],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[0] = (!cnt/LTimer[0] && cnt/LTimer[13] && cnt/TimerTC);
FDCPE FDCPE_cnt/LTimer1 (cnt/LTimer[1],cnt/LTimer_D[1],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_D[1] = ((cnt/LTimer[0] && cnt/LTimer[1])
|| (!cnt/LTimer[0] && !cnt/LTimer[1])
|| (cnt/LTimer[13] && cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer2 (cnt/LTimer[2],cnt/LTimer_T[2],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[2] = ((cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1])
|| (cnt/LTimer[0] && cnt/LTimer[1] && !cnt/TimerTC)
|| (cnt/LTimer[13] && cnt/LTimer[2] && cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer3 (cnt/LTimer[3],cnt/LTimer_T[3],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[3] = ((cnt/LTimer[13] && cnt/LTimer[3] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
!cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer4 (cnt/LTimer[4],cnt/LTimer_T[4],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[4] = ((cnt/LTimer[13] && cnt/LTimer[4] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && !cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer5 (cnt/LTimer[5],cnt/LTimer_T[5],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[5] = ((cnt/LTimer[13] && cnt/LTimer[5] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[4])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[4] && !cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer6 (cnt/LTimer[6],cnt/LTimer_T[6],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[6] = ((cnt/LTimer[13] && cnt/LTimer[6] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && !cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer7 (cnt/LTimer[7],cnt/LTimer_T[7],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[7] = ((cnt/LTimer[13] && cnt/LTimer[7] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] &&
cnt/LTimer[6])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && cnt/LTimer[6] &&
!cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer8 (cnt/LTimer[8],cnt/LTimer_T[8],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[8] = ((cnt/LTimer[13] && cnt/LTimer[8] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] &&
cnt/LTimer[6] && cnt/LTimer[7])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && cnt/LTimer[6] &&
cnt/LTimer[7] && !cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer9 (cnt/LTimer[9],cnt/LTimer_T[9],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[9] = ((cnt/LTimer[13] && cnt/LTimer[9] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] &&
cnt/LTimer[6] && cnt/LTimer[7] && cnt/LTimer[8])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && cnt/LTimer[6] &&
cnt/LTimer[7] && cnt/LTimer[8] && !cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer10 (cnt/LTimer[10],cnt/LTimer_T[10],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[10] = ((cnt/LTimer[13] && cnt/LTimer[10] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] &&
cnt/LTimer[6] && cnt/LTimer[7] && cnt/LTimer[9] && cnt/LTimer[8])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && cnt/LTimer[6] &&
cnt/LTimer[7] && cnt/LTimer[9] && cnt/LTimer[8] && !cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer11 (cnt/LTimer[11],cnt/LTimer_T[11],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[11] = ((cnt/LTimer[13] && cnt/LTimer[11] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] &&
cnt/LTimer[6] && cnt/LTimer[7] && cnt/LTimer[9] && cnt/LTimer[10] &&
cnt/LTimer[8])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && cnt/LTimer[6] &&
cnt/LTimer[7] && cnt/LTimer[9] && cnt/LTimer[10] && cnt/LTimer[8] &&
!cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer12 (cnt/LTimer[12],cnt/LTimer_T[12],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[12] = ((cnt/LTimer[13] && cnt/LTimer[12] && cnt/TimerTC)
|| (cnt/LTimer[0] && !cnt/LTimer[13] && cnt/LTimer[1] &&
cnt/LTimer[2] && cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] &&
cnt/LTimer[6] && cnt/LTimer[7] && cnt/LTimer[9] && cnt/LTimer[10] &&
cnt/LTimer[11] && cnt/LTimer[8])
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && cnt/LTimer[6] &&
cnt/LTimer[7] && cnt/LTimer[9] && cnt/LTimer[10] && cnt/LTimer[11] &&
cnt/LTimer[8] && !cnt/TimerTC));
FTCPE FTCPE_cnt/LTimer13 (cnt/LTimer[13],cnt/LTimer_T[13],!C8M,1'b0,1'b0,cnt/TimerTC);
assign cnt/LTimer_T[13] = ((cnt/LTimer[13] && cnt/TimerTC)
|| (cnt/LTimer[0] && cnt/LTimer[1] && cnt/LTimer[2] &&
cnt/LTimer[3] && cnt/LTimer[5] && cnt/LTimer[4] && cnt/LTimer[6] &&
cnt/LTimer[7] && cnt/LTimer[9] && cnt/LTimer[10] && cnt/LTimer[11] &&
cnt/LTimer[8] && cnt/LTimer[12]));
FTCPE FTCPE_cnt/PORS_FSM_FFd1 (cnt/PORS_FSM_FFd1,cnt/PORS_FSM_FFd1_T,!C8M,1'b0,1'b0);
assign cnt/PORS_FSM_FFd1_T = (cnt/LTimer[13] && !cnt/PORS_FSM_FFd1 &&
cnt/PORS_FSM_FFd2 && !cnt/IPL2r);
FDCPE FDCPE_cnt/PORS_FSM_FFd2 (cnt/PORS_FSM_FFd2,cnt/PORS_FSM_FFd2_D,!C8M,1'b0,1'b0);
assign cnt/PORS_FSM_FFd2_D = ((cnt/LTimer[13] && !cnt/PORS_FSM_FFd1)
|| (!cnt/LTimer[13] && cnt/PORS_FSM_FFd2));
FDCPE FDCPE_cnt/RefReq (cnt/RefReq,cnt/RefReq_D,E,1'b0,1'b0);
assign cnt/RefReq_D = ((cnt/Timer[1] && !cnt/Timer[3])
|| (cnt/Timer[2] && !cnt/Timer[3])
|| (!cnt/Timer[1] && !cnt/Timer[2] && !cnt/Timer[0] &&
cnt/Timer[3]));
FDCPE FDCPE_cnt/RefUrgent (cnt/RefUrgent,cnt/RefUrgent_D,E,1'b0,1'b0);
assign cnt/RefUrgent_D = ((cnt/Timer[1] && cnt/Timer[2] && !cnt/Timer[3])
|| (!cnt/Timer[1] && !cnt/Timer[2] && !cnt/Timer[0] &&
cnt/Timer[3]));
FDCPE FDCPE_cnt/Timer0 (cnt/Timer[0],cnt/Timer_D[0],E,1'b0,1'b0);
assign cnt/Timer_D[0] = (!cnt/TimerTC && !cnt/Timer[0]);
FDCPE FDCPE_cnt/Timer1 (cnt/Timer[1],cnt/Timer_D[1],E,1'b0,1'b0);
assign cnt/Timer_D[1] = ((!cnt/TimerTC && cnt/Timer[1] && !cnt/Timer[0])
|| (!cnt/TimerTC && !cnt/Timer[1] && cnt/Timer[0]));
FTCPE FTCPE_cnt/Timer2 (cnt/Timer[2],cnt/Timer_T[2],E,1'b0,1'b0);
assign cnt/Timer_T[2] = ((cnt/TimerTC && cnt/Timer[2])
|| (!cnt/TimerTC && cnt/Timer[1] && cnt/Timer[0]));
FTCPE FTCPE_cnt/Timer3 (cnt/Timer[3],cnt/Timer_T[3],E,1'b0,1'b0);
assign cnt/Timer_T[3] = ((cnt/TimerTC && cnt/Timer[3])
|| (!cnt/TimerTC && cnt/Timer[1] && cnt/Timer[2] &&
cnt/Timer[0]));
FDCPE FDCPE_cnt/TimerTC (cnt/TimerTC,cnt/TimerTC_D,E,1'b0,1'b0);
assign cnt/TimerTC_D = (!cnt/Timer[1] && !cnt/Timer[2] && !cnt/Timer[0] &&
cnt/Timer[3]);
FDCPE FDCPE_cnt/nRESout (cnt/nRESout,cnt/nRESout_D,!C8M,1'b0,1'b0);
assign cnt/nRESout_D = ((cnt/LTimer[13] && cnt/PORS_FSM_FFd1 &&
!cnt/PORS_FSM_FFd2)
|| (cnt/PORS_FSM_FFd1 && !cnt/PORS_FSM_FFd2 &&
cnt/nRESout));
FTCPE FTCPE_cs/nOverlay0 (cs/nOverlay0,cs/nOverlay0_T,FCLK,!nRES.PIN,1'b0);
Better CPLD stuff
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assign cs/nOverlay0_T = ((!A_FSB[23] && A_FSB[22] && !A_FSB[21] && !A_FSB[20] &&
!cs/nOverlay0 && !nAS_FSB)
|| (!A_FSB[23] && A_FSB[22] && !A_FSB[21] && !A_FSB[20] &&
!cs/nOverlay0 && fsb/ASrf));
idk
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FDCPE FDCPE_cs/nOverlay1 (cs/nOverlay1,cs/nOverlay0,FCLK,1'b0,1'b0,cs/nOverlay1_CE);
Better CPLD stuff
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assign cs/nOverlay1_CE = (nAS_FSB && !fsb/ASrf);
idk
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FDCPE FDCPE_fsb/ASrf (fsb/ASrf,!nAS_FSB,!FCLK,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_fsb/Ready0r (fsb/Ready0r,fsb/Ready0r_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign fsb/Ready0r_D = ((nAS_FSB && !fsb/ASrf)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
!fsb/Ready0r && !ram/RAMReady)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && !fsb/Ready0r && !ram/RAMReady));
idk
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FDCPE FDCPE_fsb/Ready1r (fsb/Ready1r,fsb/Ready1r_D,FCLK,1'b0,1'b0);
assign fsb/Ready1r_D = ((A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!fsb/Ready1r && !iobs/IOReady)
|| (A_FSB[14] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !fsb/Ready1r && !iobs/IOReady && !nADoutLE1)
|| (A_FSB[13] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !fsb/Ready1r && !iobs/IOReady && !nADoutLE1)
|| (nAS_FSB && !fsb/ASrf)
Better CPLD stuff
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|| (A_FSB[23] && !fsb/Ready1r && !iobs/IOReady)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !fsb/Ready1r &&
!iobs/IOReady)
|| (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
idk
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!fsb/Ready1r && !iobs/IOReady));
FDCPE FDCPE_fsb/VPA (fsb/VPA,fsb/VPA_D,FCLK,1'b0,1'b0);
assign fsb/VPA_D = ((EXP21_.EXP)
Better CPLD stuff
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|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
idk
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!fsb/Ready0r && fsb/VPA && fsb/ASrf && !ram/RAMReady)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && !fsb/Ready0r && fsb/VPA && !nAS_FSB && !ram/RAMReady)
Better CPLD stuff
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|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
idk
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!cs/nOverlay1 && !fsb/Ready0r && fsb/VPA && fsb/ASrf && !ram/RAMReady)
Better CPLD stuff
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|| (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
idk
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!fsb/Ready1r && fsb/VPA && !iobs/IOReady && !nAS_FSB)
Better CPLD stuff
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|| (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
idk
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!fsb/Ready1r && fsb/VPA && !iobs/IOReady && !nAS_FSB)
|| (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!fsb/Ready1r && fsb/VPA && !iobs/IOReady && fsb/ASrf)
|| (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!fsb/Ready1r && fsb/VPA && !iobs/IOReady && fsb/ASrf)
|| (A_FSB[14] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !fsb/Ready1r && fsb/VPA && !iobs/IOReady && !nAS_FSB &&
!nADoutLE1)
|| (A_FSB[13] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !fsb/Ready1r && fsb/VPA && !iobs/IOReady && !nAS_FSB &&
!nADoutLE1)
|| (A_FSB[13] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !fsb/Ready1r && fsb/VPA && !iobs/IOReady && fsb/ASrf &&
!nADoutLE1)
|| (A_FSB[23] && !fsb/Ready1r && fsb/VPA &&
!iobs/IOReady && !nAS_FSB)
Better CPLD stuff
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|| (A_FSB[23] && !fsb/Ready1r && fsb/VPA &&
idk
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!iobs/IOReady && fsb/ASrf)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
!fsb/Ready0r && fsb/VPA && !nAS_FSB && !ram/RAMReady)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !fsb/Ready1r &&
fsb/VPA && !iobs/IOReady && !nAS_FSB)
Better CPLD stuff
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|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !fsb/Ready1r &&
idk
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fsb/VPA && !iobs/IOReady && fsb/ASrf));
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/ALE0 (iobm/ALE0,iobm/ALE0_D,C16M,1'b0,1'b0);
assign iobm/ALE0_D = ((iobm/IOS_FSM_FFd1 && !iobm/IOS_FSM_FFd2)
|| (!iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd2 &&
!iobm/IOREQr));
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/BERRrf (iobm/BERRrf,!nBERR_IOB,!C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/BERRrr (iobm/BERRrr,!nBERR_IOB,C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/BG (iobm/BG,!nBG_IOB,C16M,1'b0,1'b0,iobm/nASr);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/DTACKrf (iobm/DTACKrf,!nDTACK_IOB,!C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/DTACKrr (iobm/DTACKrr,!nDTACK_IOB,C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/DoutOE (iobm/DoutOE,iobm/DoutOE_D,C16M,1'b0,1'b0);
assign iobm/DoutOE_D = ((iobs/IORW0 && iobm/IOS_FSM_FFd3)
|| (iobs/IORW0 && iobm/IOS_FSM_FFd2));
Better CPLD stuff
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idk
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FTCPE FTCPE_iobm/ES0 (iobm/ES[0],iobm/ES_T[0],C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/ES_T[0] = ((iobm/ES[0] && !iobm/Er && iobm/Er2)
|| (!iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
!iobm/ES[3] && !iobm/ES[4] && iobm/Er)
|| (!iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
!iobm/ES[3] && !iobm/ES[4] && !iobm/Er2));
idk
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FDCPE FDCPE_iobm/ES1 (iobm/ES[1],iobm/ES_D[1],C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/ES_D[1] = ((iobm/ES[0] && iobm/ES[1])
|| (!iobm/ES[0] && !iobm/ES[1])
|| (!iobm/Er && iobm/Er2));
idk
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FDCPE FDCPE_iobm/ES2 (iobm/ES[2],iobm/ES_D[2],C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/ES_D[2] = ((!iobm/ES[0] && !iobm/ES[2])
|| (!iobm/ES[1] && !iobm/ES[2])
|| (!iobm/Er && iobm/Er2)
|| (iobm/ES[0] && iobm/ES[1] && iobm/ES[2])
|| (!iobm/ES[2] && !iobm/ES[3] && iobm/ES[4]));
idk
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FTCPE FTCPE_iobm/ES3 (iobm/ES[3],iobm/ES_T[3],C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/ES_T[3] = ((iobm/ES[3] && !iobm/Er && iobm/Er2)
|| (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] && iobm/Er)
|| (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] && !iobm/Er2));
idk
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FTCPE FTCPE_iobm/ES4 (iobm/ES[4],iobm/ES_T[4],C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/ES_T[4] = ((iobm/ES[4] && !iobm/Er && iobm/Er2)
|| (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] &&
iobm/ES[3] && iobm/Er)
|| (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] &&
iobm/ES[3] && !iobm/Er2)
|| (iobm/ES[0] && iobm/ES[1] && !iobm/ES[2] &&
!iobm/ES[3] && iobm/ES[4]));
idk
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FDCPE FDCPE_iobm/ETACK (iobm/ETACK,iobm/ETACK_D,C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/ETACK_D = (!nVMA_IOB && !iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
!iobm/ES[3] && iobm/ES[4]);
idk
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FDCPE FDCPE_iobm/Er (iobm/Er,E,!C8M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/Er2 (iobm/Er2,iobm/Er,C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/IOACT (iobm/IOACT,iobm/IOACT_D,C16M,1'b0,1'b0);
assign iobm/IOACT_D = ((C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
Better CPLD stuff
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iobm/RESrf && iobm/RESrr)
|| (iobm/IOS_FSM_FFd1 && !iobm/IOS_FSM_FFd2)
|| (!iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd2 &&
!iobm/IOREQr)
idk
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|| (C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
Better CPLD stuff
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iobm/ETACK)
idk
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|| (C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
iobm/BERRrf && iobm/BERRrr)
|| (C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
iobm/DTACKrf && iobm/DTACKrr));
Better CPLD stuff
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idk
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FTCPE FTCPE_iobm/IOBERR (iobm/IOBERR,iobm/IOBERR_T,C16M,1'b0,1'b0);
assign iobm/IOBERR_T = ((C8M && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/RESrf &&
iobm/RESrr)
idk
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|| (C8M && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/BERRrf &&
iobm/BERRrr)
idk
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|| (C8M && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/DTACKrf &&
iobm/DTACKrr)
idk
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|| (C8M && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/RESrf &&
iobm/RESrr)
|| (iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd1 &&
!iobm/IOS_FSM_FFd2 && iobm/IOBERR)
idk
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|| (C8M && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/ETACK)
idk
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|| (C8M && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/ETACK)
idk
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|| (C8M && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/BERRrf &&
iobm/BERRrr)
idk
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|| (C8M && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/DTACKrf &&
iobm/DTACKrr));
idk
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FDCPE FDCPE_iobm/IOREQr (iobm/IOREQr,iobs/IOREQ,!C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/IOS_FSM_FFd1 (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd1_D,C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/IOS_FSM_FFd1_D = ((iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1)
|| (!iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd2));
idk
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FTCPE FTCPE_iobm/IOS_FSM_FFd2 (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_T,C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/IOS_FSM_FFd2_T = ((iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd1 &&
!iobm/IOS_FSM_FFd2)
idk
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|| (C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd2 && iobm/ETACK)
idk
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|| (C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd2 && iobm/BERRrf && iobm/BERRrr)
idk
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|| (C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd2 && iobm/DTACKrf && iobm/DTACKrr)
idk
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|| (C8M && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
Better CPLD stuff
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iobm/IOS_FSM_FFd2 && iobm/RESrf && iobm/RESrr));
idk
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FDCPE FDCPE_iobm/IOS_FSM_FFd3 (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,1'b0,1'b0);
Better CPLD stuff
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assign iobm/IOS_FSM_FFd3_D = ((iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2)
|| (iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd1 &&
!iobm/IOS_FSM_FFd2)
idk
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|| (!C8M && iobm/BG && !iobm/IOS_FSM_FFd1 &&
!iobm/IOS_FSM_FFd2 && iobm/IOREQr));
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/RESrf (iobm/RESrf,!nRES.PIN,!C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/RESrr (iobm/RESrr,!nRES.PIN,C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/VPArf (iobm/VPArf,!nVPA_IOB,!C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/VPArr (iobm/VPArr,!nVPA_IOB,C16M,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobm/nASr (iobm/nASr,iobm/nASr_D,C16M,1'b0,1'b0);
assign iobm/nASr_D = (!nAS_IOB && nAoutOE);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/ALE0 (iobs/ALE0,iobs/ALE0_D,FCLK,1'b0,1'b0);
assign iobs/ALE0_D = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/Clear1 (iobs/Clear1,iobs/Clear1_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign iobs/Clear1_D = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && !nADoutLE1);
idk
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FDCPE FDCPE_iobs/IOACTr (iobs/IOACTr,iobm/IOACT,FCLK,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/IOL0 (iobs/IOL0,iobs/IOL0_D,FCLK,1'b0,1'b0,iobs/IOL0_CE);
Better CPLD stuff
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assign iobs/IOL0_D = ((!nLDS_FSB && nADoutLE1)
|| (iobs/IOL1 && !nADoutLE1));
assign iobs/IOL0_CE = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1);
idk
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FDCPE FDCPE_iobs/IOL1 (iobs/IOL1,!nLDS_FSB,FCLK,1'b0,1'b0,iobs/Load1);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/IOREQ (iobs/IOREQ,iobs/IOREQ_D,FCLK,1'b0,1'b0);
assign iobs/IOREQ_D = ((iobs/nBERR_FSB.EXP)
|| (!A_FSB[23] && !A_FSB[22] && !A_FSB[21] &&
Better CPLD stuff
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!iobs/PS_FSM_FFd2 && nADoutLE1)
idk
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|| (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1 &&
Better CPLD stuff
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!iobs/PS_FSM_FFd2 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[19] &&
!iobs/PS_FSM_FFd2 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[16] &&
!iobs/PS_FSM_FFd2 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[21] && nWE_FSB &&
!iobs/PS_FSM_FFd2 && nADoutLE1)
idk
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|| (!A_FSB[23] && A_FSB[21] && !A_FSB[18] &&
!iobs/PS_FSM_FFd2 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[17] &&
Better CPLD stuff
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!iobs/PS_FSM_FFd2 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
cs/nOverlay1 && !iobs/PS_FSM_FFd2 && nADoutLE1)
|| (!iobs/PS_FSM_FFd2 && iobs/PS_FSM_FFd1)
|| (iobs/PS_FSM_FFd1 && iobs/IOACTr)
|| (iobs/Once && !iobs/PS_FSM_FFd2 && nADoutLE1)
idk
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|| (!A_FSB[23] && !A_FSB[20] && !iobs/PS_FSM_FFd2 &&
Better CPLD stuff
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nADoutLE1)
idk
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|| (nAS_FSB && !iobs/PS_FSM_FFd2 && !fsb/ASrf &&
nADoutLE1));
Better CPLD stuff
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idk
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FTCPE FTCPE_iobs/IORW0 (iobs/IORW0,iobs/IORW0_T,FCLK,1'b0,1'b0);
assign iobs/IORW0_T = ((A_FSB[23] && nWE_FSB && !iobs/Once && !iobs/IORW0 &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && fsb/ASrf && nADoutLE1)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && nWE_FSB &&
!iobs/Once && !iobs/IORW0 && !nAS_FSB && !iobs/PS_FSM_FFd2 &&
!iobs/PS_FSM_FFd1 && nADoutLE1)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && nWE_FSB &&
!iobs/Once && !iobs/IORW0 && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
fsb/ASrf && nADoutLE1)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !nWE_FSB &&
!iobs/Once && iobs/IORW0 && !nAS_FSB && !iobs/PS_FSM_FFd2 &&
!iobs/PS_FSM_FFd1 && nADoutLE1)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !nWE_FSB &&
!iobs/Once && iobs/IORW0 && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
fsb/ASrf && nADoutLE1)
|| (nROMWE_OBUF.EXP)
|| (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!iobs/Once && iobs/IORW0 && !nAS_FSB && !iobs/PS_FSM_FFd2 &&
!iobs/PS_FSM_FFd1 && nADoutLE1)
|| (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!iobs/Once && iobs/IORW0 && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
fsb/ASrf && nADoutLE1)
|| (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!iobs/Once && iobs/IORW0 && !nAS_FSB && !iobs/PS_FSM_FFd2 &&
!iobs/PS_FSM_FFd1 && nADoutLE1)
|| (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!iobs/Once && iobs/IORW0 && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
fsb/ASrf && nADoutLE1)
|| (A_FSB[14] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !iobs/Once && iobs/IORW0 && !nAS_FSB &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (iobs/IORW0 && !iobs/IORW1 && !iobs/PS_FSM_FFd2 &&
!iobs/PS_FSM_FFd1 && !nADoutLE1)
|| (!iobs/IORW0 && iobs/IORW1 && !iobs/PS_FSM_FFd2 &&
!iobs/PS_FSM_FFd1 && !nADoutLE1)
|| (A_FSB[23] && nWE_FSB && !iobs/Once && !iobs/IORW0 &&
!nAS_FSB && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (A_FSB[23] && !nWE_FSB && !iobs/Once && iobs/IORW0 &&
!nAS_FSB && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (A_FSB[23] && !nWE_FSB && !iobs/Once && iobs/IORW0 &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && fsb/ASrf && nADoutLE1));
FTCPE FTCPE_iobs/IORW1 (iobs/IORW1,iobs/IORW1_T,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign iobs/IORW1_T = ((iobs/Once)
|| (!nADoutLE1)
idk
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|| (fsb/Ready1r.EXP)
|| (!nWE_FSB && !iobs/IORW1)
Better CPLD stuff
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|| (nAS_FSB && !fsb/ASrf)
|| (!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1)
|| (!A_FSB[23] && !A_FSB[22] && !A_FSB[21])
|| (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[19])
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[18])
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[17])
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[16])
idk
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|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
cs/nOverlay1)
|| (!A_FSB[23] && !A_FSB[20])
Better CPLD stuff
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|| (nWE_FSB && iobs/IORW1)
|| (!A_FSB[23] && A_FSB[21] && !iobs/IORW1));
idk
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FTCPE FTCPE_iobs/IOReady (iobs/IOReady,iobs/IOReady_T,FCLK,1'b0,1'b0);
assign iobs/IOReady_T = ((iobs/Once && iobs/IOReady && !iobs/PS_FSM_FFd2 &&
Better CPLD stuff
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!iobs/IOACTr && iobm/IOBERR && nADoutLE1)
|| (iobs/Once && !iobs/IOReady && !nAS_FSB &&
!iobs/PS_FSM_FFd2 && !iobs/IOACTr && !iobm/IOBERR && nADoutLE1)
|| (iobs/Once && !iobs/IOReady && !iobs/PS_FSM_FFd2 &&
idk
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!iobs/IOACTr && !iobm/IOBERR && fsb/ASrf && nADoutLE1)
|| (iobs/IOReady && nAS_FSB && !fsb/ASrf));
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/IOU0 (iobs/IOU0,iobs/IOU0_D,FCLK,1'b0,1'b0,iobs/IOU0_CE);
Better CPLD stuff
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assign iobs/IOU0_D = ((!nUDS_FSB && nADoutLE1)
|| (iobs/IOU1 && !nADoutLE1));
assign iobs/IOU0_CE = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1);
idk
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FDCPE FDCPE_iobs/IOU1 (iobs/IOU1,!nUDS_FSB,FCLK,1'b0,1'b0,iobs/Load1);
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/Load1 (iobs/Load1,iobs/Load1_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign iobs/Load1_D = ((iobs/Once)
|| (!nADoutLE1)
|| (!A_FSB[23] && !A_FSB[22] && !A_FSB[21])
idk
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|| (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1)
Better CPLD stuff
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|| (!A_FSB[23] && A_FSB[21] && !A_FSB[19])
idk
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|| (!A_FSB[23] && A_FSB[21] && nWE_FSB)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[18])
Better CPLD stuff
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|| (!A_FSB[23] && A_FSB[21] && !A_FSB[17])
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[16])
|| (!A_FSB[14] && !A_FSB[13] && !A_FSB[23] && A_FSB[21])
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
cs/nOverlay1)
idk
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|| (!A_FSB[23] && !A_FSB[20])
Better CPLD stuff
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|| (nAS_FSB && !fsb/ASrf)
idk
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|| (!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1));
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/Once (iobs/Once,iobs/Once_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign iobs/Once_D = ((A_FSB[23] && !iobs/Once && iobs/PS_FSM_FFd1)
idk
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|| (!iobs/Once && iobs/PS_FSM_FFd2 && !nADoutLE1)
Better CPLD stuff
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|| (!iobs/Once && iobs/PS_FSM_FFd1 && !nADoutLE1)
|| (!A_FSB[23] && !A_FSB[22] && !A_FSB[21] && !iobs/Once)
idk
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|| (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1 &&
!iobs/Once)
|| (cnt/PORS_FSM_FFd1.EXP)
Better CPLD stuff
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|| (!A_FSB[23] && A_FSB[21] && !A_FSB[19] && !iobs/Once)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[18] && !iobs/Once)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[17] && !iobs/Once)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[16] && !iobs/Once)
|| (!A_FSB[23] && A_FSB[21] && nWE_FSB && !iobs/Once)
|| (nAS_FSB && !fsb/ASrf)
|| (A_FSB[23] && !iobs/Once && iobs/PS_FSM_FFd2)
idk
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|| (!A_FSB[23] && !A_FSB[20] && !iobs/Once)
Better CPLD stuff
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|| (A_FSB[22] && !iobs/Once && iobs/PS_FSM_FFd2)
idk
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|| (A_FSB[22] && !iobs/Once && iobs/PS_FSM_FFd1));
Better CPLD stuff
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idk
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FDCPE FDCPE_iobs/PS_FSM_FFd1 (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign iobs/PS_FSM_FFd1_D = ((iobs/PS_FSM_FFd2)
|| (iobs/PS_FSM_FFd1 && iobs/IOACTr));
idk
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FDCPE FDCPE_iobs/PS_FSM_FFd2 (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign iobs/PS_FSM_FFd2_D = ((!A_FSB[23] && !A_FSB[22] && !A_FSB[21] &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
idk
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|| (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1 &&
Better CPLD stuff
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!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[19] &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[21] && !A_FSB[16] &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
idk
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|| (!A_FSB[23] && A_FSB[21] && nWE_FSB &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
Better CPLD stuff
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|| (!A_FSB[23] && A_FSB[21] && !A_FSB[18] &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
idk
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|| (!A_FSB[23] && A_FSB[21] && !A_FSB[17] &&
Better CPLD stuff
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!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (!A_FSB[14] && !A_FSB[13] && !A_FSB[23] && A_FSB[21] &&
!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
cs/nOverlay1 && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|| (iobs/PS_FSM_FFd2 && iobs/PS_FSM_FFd1 &&
iobs/IOACTr)
|| (!iobs/PS_FSM_FFd2 && iobs/PS_FSM_FFd1 &&
!iobs/IOACTr)
|| (iobs/Once && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
nADoutLE1)
idk
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|| (!A_FSB[23] && !A_FSB[20] && !iobs/PS_FSM_FFd2 &&
!iobs/PS_FSM_FFd1 && nADoutLE1)
Better CPLD stuff
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|| (nAS_FSB && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
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!fsb/ASrf && nADoutLE1));
Better CPLD stuff
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assign nADoutLE0 = (!iobm/ALE0 && !iobs/ALE0);
idk
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FDCPE FDCPE_nADoutLE1 (nADoutLE1,nADoutLE1_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign nADoutLE1_D = ((iobs/Load1)
|| (!iobs/Clear1 && !nADoutLE1));
idk
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FDCPE FDCPE_nAS_IOB (nAS_IOB_I,nAS_IOB,!C16M,1'b0,1'b0);
Better CPLD stuff
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assign nAS_IOB = ((!iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd2)
|| (iobm/IOS_FSM_FFd1 && !iobm/IOS_FSM_FFd2));
assign nAS_IOB = nAS_IOB_OE ? nAS_IOB_I : 1'bZ;
idk
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assign nAS_IOB_OE = nAoutOE;
Better CPLD stuff
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idk
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FDCPE FDCPE_nAoutOE (nAoutOE,nAoutOE_D,!C8M,1'b0,1'b0);
assign nAoutOE_D = (!nBR_IOB && cnt/PORS_FSM_FFd1 && !cnt/PORS_FSM_FFd2);
Better CPLD stuff
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idk
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FTCPE FTCPE_nBERR_FSB (nBERR_FSB,nBERR_FSB_T,FCLK,1'b0,1'b0);
assign nBERR_FSB_T = ((nAS_FSB && !nBERR_FSB && !fsb/ASrf)
|| (iobs/Once && !nBERR_FSB && !iobs/PS_FSM_FFd2 &&
!iobs/IOACTr && !iobm/IOBERR && nADoutLE1)
|| (iobs/Once && !nAS_FSB && nBERR_FSB &&
!iobs/PS_FSM_FFd2 && !iobs/IOACTr && iobm/IOBERR && nADoutLE1)
|| (iobs/Once && nBERR_FSB && !iobs/PS_FSM_FFd2 &&
!iobs/IOACTr && iobm/IOBERR && fsb/ASrf && nADoutLE1));
Better CPLD stuff
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idk
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FTCPE FTCPE_nBR_IOB (nBR_IOB,nBR_IOB_T,!C8M,1'b0,1'b0);
assign nBR_IOB_T = ((nBR_IOB && !cnt/PORS_FSM_FFd1 && !cnt/PORS_FSM_FFd2)
|| (!nBR_IOB && !cnt/PORS_FSM_FFd1 && cnt/PORS_FSM_FFd2 &&
cnt/IPL2r));
Better CPLD stuff
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idk
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FDCPE FDCPE_nCAS (nCAS,!ram/RASEL,!FCLK,1'b0,1'b0);
Better CPLD stuff
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idk
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FDCPE FDCPE_nDTACK_FSB (nDTACK_FSB,nDTACK_FSB_D,FCLK,1'b0,1'b0);
assign nDTACK_FSB_D = ((iobs/IOReady.EXP)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
!fsb/Ready0r && nDTACK_FSB && !ram/RAMReady)
Better CPLD stuff
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|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !fsb/Ready1r &&
!iobs/IOReady && nDTACK_FSB)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && !fsb/Ready0r && nDTACK_FSB && !ram/RAMReady)
idk
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|| (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!fsb/Ready1r && !iobs/IOReady && nDTACK_FSB)
Better CPLD stuff
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|| (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
!fsb/Ready1r && !iobs/IOReady && nDTACK_FSB)
idk
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|| (A_FSB[14] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
Better CPLD stuff
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A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !fsb/Ready1r && !iobs/IOReady && nDTACK_FSB &&
!nADoutLE1)
idk
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|| (A_FSB[13] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
cs/nOverlay1 && !fsb/Ready1r && !iobs/IOReady && nDTACK_FSB &&
!nADoutLE1));
FDCPE FDCPE_nDinLE (nDinLE,nDinLE_D,!C16M,1'b0,1'b0);
Better CPLD stuff
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assign nDinLE_D = (iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2);
assign nDinOE = ((A_FSB[23] && nWE_FSB && !nAS_FSB)
|| (A_FSB[22] && !A_FSB[21] && A_FSB[20] && nWE_FSB &&
idk
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!nAS_FSB));
Better CPLD stuff
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idk
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assign nDoutOE = !((!nAoutOE && iobm/DoutOE));
Better CPLD stuff
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idk
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FDCPE FDCPE_nLDS_IOB (nLDS_IOB_I,nLDS_IOB,!C16M,1'b0,1'b0);
Better CPLD stuff
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assign nLDS_IOB = ((iobs/IOL0 && !iobm/IOS_FSM_FFd3 &&
iobm/IOS_FSM_FFd2)
|| (iobs/IOL0 && iobm/IOS_FSM_FFd1 &&
iobm/IOS_FSM_FFd2)
|| (!iobs/IORW0 && iobs/IOL0 && iobm/IOS_FSM_FFd3 &&
!iobm/IOS_FSM_FFd1));
assign nLDS_IOB = nLDS_IOB_OE ? nLDS_IOB_I : 1'bZ;
idk
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assign nLDS_IOB_OE = nAoutOE;
Better CPLD stuff
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assign nOE = !((nWE_FSB && !nAS_FSB));
idk
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assign nRAMLWE = !((!nWE_FSB && !nLDS_FSB && !nAS_FSB && ram/RAMEN));
Better CPLD stuff
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idk
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assign nRAMUWE = !((!nWE_FSB && !nUDS_FSB && !nAS_FSB && ram/RAMEN));
Better CPLD stuff
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assign nRAS = !(((ram/RefRAS)
idk
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|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 && !nAS_FSB &&
ram/RAMEN)
Better CPLD stuff
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|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
idk
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!cs/nOverlay1 && !nAS_FSB && ram/RAMEN)));
Better CPLD stuff
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idk
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assign nRES_I = 1'b0;
assign nRES = nRES_OE ? nRES_I : 1'bZ;
assign nRES_OE = !cnt/nRESout;
assign nROMCS = !(((!A_FSB[23] && A_FSB[22] && !A_FSB[21] && !A_FSB[20])
|| (!A_FSB[23] && !A_FSB[21] && !A_FSB[20] &&
Better CPLD stuff
2022-03-29 04:23:54 -04:00
!cs/nOverlay1)));
assign nROMWE = !((!nWE_FSB && !nAS_FSB));
idk
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FDCPE FDCPE_nUDS_IOB (nUDS_IOB_I,nUDS_IOB,!C16M,1'b0,1'b0);
Better CPLD stuff
2022-03-29 04:23:54 -04:00
assign nUDS_IOB = ((iobs/IOU0 && !iobm/IOS_FSM_FFd3 &&
iobm/IOS_FSM_FFd2)
|| (iobs/IOU0 && iobm/IOS_FSM_FFd1 &&
iobm/IOS_FSM_FFd2)
|| (!iobs/IORW0 && iobs/IOU0 && iobm/IOS_FSM_FFd3 &&
!iobm/IOS_FSM_FFd1));
assign nUDS_IOB = nUDS_IOB_OE ? nUDS_IOB_I : 1'bZ;
idk
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assign nUDS_IOB_OE = nAoutOE;
Better CPLD stuff
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idk
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FTCPE FTCPE_nVMA_IOB (nVMA_IOB_I,nVMA_IOB_T,C16M,1'b0,1'b0);
Better CPLD stuff
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assign nVMA_IOB_T = ((!nVMA_IOB && !iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
!iobm/ES[3] && !iobm/ES[4])
|| (nVMA_IOB && iobm/ES[0] && iobm/ES[1] && iobm/ES[2] &&
!iobm/ES[3] && !iobm/ES[4] && iobm/IOACT && iobm/VPArf &&
iobm/VPArr));
assign nVMA_IOB = nVMA_IOB_OE ? nVMA_IOB_I : 1'bZ;
idk
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assign nVMA_IOB_OE = nAoutOE;
Better CPLD stuff
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assign nVPA_FSB = !((fsb/VPA && !nAS_FSB));
idk
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FDCPE FDCPE_ram/BACTr (ram/BACTr,ram/BACTr_D,FCLK,1'b0,1'b0);
Better CPLD stuff
2022-03-29 04:23:54 -04:00
assign ram/BACTr_D = (nAS_FSB && !fsb/ASrf);
idk
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FDCPE FDCPE_ram/RAMEN (ram/RAMEN,ram/RAMEN_D,FCLK,1'b0,1'b0);
assign ram/RAMEN_D = ((!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 && !nAS_FSB &&
!ram/RS_FSM_FFd1 && ram/RAMEN)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
!ram/RS_FSM_FFd1 && ram/RAMEN && fsb/ASrf)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 && ram/RAMEN)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && !ram/RS_FSM_FFd1 && ram/RAMEN && fsb/ASrf)
|| (ram/RS_FSM_FFd2 && ram/RAMEN)
|| (ram/RS_FSM_FFd3 && ram/RAMEN)
|| (!ram/RS_FSM_FFd1 && !ram/RefUrgent && ram/RAMEN &&
ram/BACTr)
|| (!ram/RS_FSM_FFd1 && !ram/RefUrgent && ram/RAMEN &&
!ram/RefReq)
|| (nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !fsb/ASrf));
FDCPE FDCPE_ram/RAMReady (ram/RAMReady,ram/RAMReady_D,FCLK,1'b0,1'b0);
assign ram/RAMReady_D = ((RA_6_OBUF.EXP)
|| (A_FSB[23] && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !ram/RefReq)
|| (A_FSB[22] && !A_FSB[21] && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && ram/BACTr)
|| (A_FSB[22] && !A_FSB[21] && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && !ram/RefReq)
|| (A_FSB[22] && cs/nOverlay1 && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && ram/BACTr)
|| (!A_FSB[22] && !cs/nOverlay1 && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && ram/BACTr)
|| (ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3)
|| (A_FSB[23] && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && ram/BACTr)
|| (nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !fsb/ASrf));
FDCPE FDCPE_ram/RASEL (ram/RASEL,ram/RASEL_D,FCLK,1'b0,1'b0);
assign ram/RASEL_D = ((A_FSB[22] && !A_FSB[21] && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && !ram/RefReq)
|| (A_FSB[22] && cs/nOverlay1 && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && !ram/RefReq)
|| (!A_FSB[22] && !cs/nOverlay1 && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && !ram/RefReq)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 && !nAS_FSB &&
!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && !ram/RAMEN)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && !ram/RAMEN && fsb/ASrf)
|| (ram/RAMReady.EXP)
|| (A_FSB[23] && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && ram/BACTr)
|| (A_FSB[23] && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !ram/RefReq)
|| (A_FSB[22] && !A_FSB[21] && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && ram/BACTr)
|| (A_FSB[22] && cs/nOverlay1 && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && ram/BACTr)
|| (!A_FSB[22] && !cs/nOverlay1 && !ram/RS_FSM_FFd2 &&
!ram/RefUrgent && !ram/RS_FSM_FFd3 && ram/BACTr)
|| (ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2)
|| (ram/RS_FSM_FFd2 && ram/RS_FSM_FFd3)
|| (!nAS_FSB && ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3)
|| (ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|| (nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !fsb/ASrf));
FDCPE FDCPE_ram/RS_FSM_FFd1 (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_D,FCLK,1'b0,1'b0);
assign ram/RS_FSM_FFd1_D = ((!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
!ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && ram/RefUrgent && !ram/RAMEN &&
fsb/ASrf)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
Better CPLD stuff
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!cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
idk
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ram/RefUrgent && !ram/RAMEN)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
Better CPLD stuff
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!cs/nOverlay1 && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
idk
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ram/RefUrgent && !ram/RAMEN && fsb/ASrf)
Better CPLD stuff
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|| (ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2)
|| (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd3)
idk
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|| (!nAS_FSB && ram/RS_FSM_FFd1 && ram/RefUrgent &&
!ram/RS_FSM_FFd3)
|| (ram/RS_FSM_FFd1 && ram/RefUrgent &&
!ram/RS_FSM_FFd3 && fsb/ASrf)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 && !nAS_FSB &&
!ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && ram/RefUrgent && !ram/RAMEN));
FDCPE FDCPE_ram/RS_FSM_FFd2 (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_D,FCLK,1'b0,1'b0);
assign ram/RS_FSM_FFd2_D = ((nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !fsb/ASrf)
Better CPLD stuff
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|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 && !nAS_FSB &&
!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3)
|| (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3)
|| (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
!cs/nOverlay1 && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|| (ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2)
|| (!nAS_FSB && ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3)
|| (ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && fsb/ASrf)
idk
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|| (!ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && ram/BACTr)
|| (!ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !ram/RefReq));
FTCPE FTCPE_ram/RS_FSM_FFd3 (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,FCLK,1'b0,1'b0);
assign ram/RS_FSM_FFd3_T = ((ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2 &&
!ram/RS_FSM_FFd3)
|| (ram/RS_FSM_FFd1 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3)
|| (A_FSB[23] && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
!ram/RS_FSM_FFd3)
|| (nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
!fsb/ASrf)
|| (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2 &&
ram/RS_FSM_FFd3)
|| (!ram/RS_FSM_FFd2 && !ram/RefUrgent &&
!ram/RS_FSM_FFd3 && !ram/RAMEN)
|| (A_FSB[22] && !A_FSB[21] && !ram/RS_FSM_FFd1 &&
!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3)
|| (A_FSB[22] && cs/nOverlay1 && !ram/RS_FSM_FFd1 &&
!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3)
|| (!A_FSB[22] && !cs/nOverlay1 && !ram/RS_FSM_FFd1 &&
!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3));
FDCPE FDCPE_ram/RefDone (ram/RefDone,ram/RefDone_D,FCLK,1'b0,1'b0);
assign ram/RefDone_D = ((ram/RefDone && ram/RefReqSync)
|| (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2 &&
ram/RefReqSync));
FDCPE FDCPE_ram/RefRAS (ram/RefRAS,ram/RefRAS_D,FCLK,1'b0,1'b0);
Better CPLD stuff
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assign ram/RefRAS_D = (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2);
idk
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FDCPE FDCPE_ram/RefReq (ram/RefReq,ram/RefReq_D,FCLK,1'b0,1'b0);
assign ram/RefReq_D = (!ram/RefDone && ram/RefReqSync);
FDCPE FDCPE_ram/RefReqSync (ram/RefReqSync,cnt/RefReq,FCLK,1'b0,1'b0);
FDCPE FDCPE_ram/RefUrgent (ram/RefUrgent,ram/RefUrgent_D,FCLK,1'b0,1'b0);
assign ram/RefUrgent_D = (!ram/RefDone && ram/RegUrgentSync);
FDCPE FDCPE_ram/RegUrgentSync (ram/RegUrgentSync,cnt/RefUrgent,FCLK,1'b0,1'b0);
Better CPLD stuff
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Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 A_FSB<5> 52 RA<7>
3 A_FSB<6> 53 RA<0>
4 A_FSB<7> 54 RA<8>
5 VCC 55 RA<10>
6 A_FSB<8> 56 RA<9>
7 A_FSB<9> 57 VCC
idk
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8 A_FSB<10> 58 C25MEN
9 A_FSB<11> 59 C20MEN
10 A_FSB<12> 60 KPR
11 A_FSB<13> 61 KPR
Better CPLD stuff
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12 A_FSB<14> 62 GND
13 A_FSB<15> 63 RA<11>
14 A_FSB<16> 64 nRAS
15 A_FSB<17> 65 nRAMLWE
16 A_FSB<18> 66 nRAMUWE
17 A_FSB<19> 67 KPR
18 A_FSB<20> 68 KPR
19 A_FSB<21> 69 GND
20 A_FSB<22> 70 nBERR_FSB
21 GND 71 KPR
idk
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22 C16M 72 nBR_IOB
23 C8M 73 nBG_IOB
Better CPLD stuff
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24 A_FSB<23> 74 nVMA_IOB
idk
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25 E 75 GND
Better CPLD stuff
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26 VCC 76 nBERR_IOB
idk
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27 FCLK 77 nVPA_IOB
Better CPLD stuff
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28 nDTACK_FSB 78 nDTACK_IOB
29 nWE_FSB 79 nLDS_IOB
30 nLDS_FSB 80 nUDS_IOB
31 GND 81 nAS_IOB
32 nAS_FSB 82 nADoutLE1
33 nUDS_FSB 83 TDO
34 nROMWE 84 GND
35 nROMCS 85 nADoutLE0
36 nCAS 86 nDinLE
37 nOE 87 nAoutOE
38 VCC 88 VCC
39 KPR 89 nDoutOE
40 RA<4> 90 nDinOE
41 RA<3> 91 nRES
42 RA<5> 92 nIPL2
43 RA<2> 93 nVPA_FSB
44 GND 94 A_FSB<1>
45 TDI 95 A_FSB<2>
46 RA<6> 96 A_FSB<3>
47 TMS 97 A_FSB<4>
48 TCK 98 VCC
49 KPR 99 KPR
50 RA<1> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 50
</pre>
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