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< html > < head > < link type = 'text/css' href = 'style.css' rel = 'stylesheet' > < / head > < body class = 'pgBgnd' >
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< table width = '90%' align = 'center' border = '1' cellpadding = '0' cellspacing = '0' >
< tr > < td >
< / td > < / tr > < tr > < td >
********** Mapped Logic **********
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign C20MEN = 1'b1;
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign C25MEN = 1'b1;
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign RA[0] = ((A_FSB[10] & & !ram/RASEL)
< br / > || (ram/RASEL & & A_FSB[1]));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[1] = ((A_FSB[11] & & !ram/RASEL)
< br / > || (ram/RASEL & & A_FSB[2]));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[2] = ((A_FSB[12] & & !ram/RASEL)
< br / > || (ram/RASEL & & A_FSB[3]));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[3] = ((A_FSB[13] & & !ram/RASEL)
< br / > || (ram/RASEL & & A_FSB[4]));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign RA[4] = ((ram/RASEL & & A_FSB[5])
< br / > || (A_FSB[14] & & !ram/RASEL));
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[5] = ((A_FSB[15] & & !ram/RASEL)
< br / > || (ram/RASEL & & A_FSB[6]));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign RA[6] = ((ram/RASEL & & A_FSB[7])
< br / > || (A_FSB[16] & & !ram/RASEL));
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[7] = ((A_FSB[8] & & ram/RASEL)
< br / > || (A_FSB[17] & & !ram/RASEL));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[8] = ((A_FSB[9] & & !A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
< br / > ram/RASEL)
< br / > || (A_FSB[9] & & !A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & ram/RASEL)
< br / > || (A_FSB[23] & & A_FSB[18])
< br / > || (A_FSB[18] & & !ram/RASEL)
< br / > || (A_FSB[22] & & !A_FSB[21] & & A_FSB[18])
< br / > || (A_FSB[22] & & A_FSB[18] & & cs/nOverlay1)
< br / > || (!A_FSB[22] & & A_FSB[18] & & !cs/nOverlay1));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[9] = ((A_FSB[20] & & ram/RASEL)
< br / > || (A_FSB[19] & & !ram/RASEL));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[10] = A_FSB[21];
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign RA[11] = A_FSB[19];
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_cnt/IPL2r (cnt/IPL2r,!nIPL2,!C8M,1'b0,1'b0);
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer0 (cnt/LTimer[0],cnt/LTimer_T[0],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[0] = (!cnt/LTimer[0] & & cnt/LTimer[13] & & cnt/TimerTC);
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/LTimer1 (cnt/LTimer[1],cnt/LTimer_D[1],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_D[1] = ((cnt/LTimer[0] & & cnt/LTimer[1])
< br / > || (!cnt/LTimer[0] & & !cnt/LTimer[1])
< br / > || (cnt/LTimer[13] & & cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer2 (cnt/LTimer[2],cnt/LTimer_T[2],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[2] = ((cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & !cnt/TimerTC)
< br / > || (cnt/LTimer[13] & & cnt/LTimer[2] & & cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer3 (cnt/LTimer[3],cnt/LTimer_T[3],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[3] = ((cnt/LTimer[13] & & cnt/LTimer[3] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer4 (cnt/LTimer[4],cnt/LTimer_T[4],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[4] = ((cnt/LTimer[13] & & cnt/LTimer[4] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer5 (cnt/LTimer[5],cnt/LTimer_T[5],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[5] = ((cnt/LTimer[13] & & cnt/LTimer[5] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[4])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[4] & & !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer6 (cnt/LTimer[6],cnt/LTimer_T[6],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[6] = ((cnt/LTimer[13] & & cnt/LTimer[6] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer7 (cnt/LTimer[7],cnt/LTimer_T[7],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[7] = ((cnt/LTimer[13] & & cnt/LTimer[7] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & &
< br / > cnt/LTimer[6])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & cnt/LTimer[6] & &
< br / > !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer8 (cnt/LTimer[8],cnt/LTimer_T[8],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[8] = ((cnt/LTimer[13] & & cnt/LTimer[8] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & &
< br / > cnt/LTimer[6] & & cnt/LTimer[7])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & cnt/LTimer[6] & &
< br / > cnt/LTimer[7] & & !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer9 (cnt/LTimer[9],cnt/LTimer_T[9],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[9] = ((cnt/LTimer[13] & & cnt/LTimer[9] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & &
< br / > cnt/LTimer[6] & & cnt/LTimer[7] & & cnt/LTimer[8])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & cnt/LTimer[6] & &
< br / > cnt/LTimer[7] & & cnt/LTimer[8] & & !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer10 (cnt/LTimer[10],cnt/LTimer_T[10],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[10] = ((cnt/LTimer[13] & & cnt/LTimer[10] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & &
< br / > cnt/LTimer[6] & & cnt/LTimer[7] & & cnt/LTimer[9] & & cnt/LTimer[8])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & cnt/LTimer[6] & &
< br / > cnt/LTimer[7] & & cnt/LTimer[9] & & cnt/LTimer[8] & & !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer11 (cnt/LTimer[11],cnt/LTimer_T[11],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[11] = ((cnt/LTimer[13] & & cnt/LTimer[11] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & &
< br / > cnt/LTimer[6] & & cnt/LTimer[7] & & cnt/LTimer[9] & & cnt/LTimer[10] & &
< br / > cnt/LTimer[8])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & cnt/LTimer[6] & &
< br / > cnt/LTimer[7] & & cnt/LTimer[9] & & cnt/LTimer[10] & & cnt/LTimer[8] & &
< br / > !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer12 (cnt/LTimer[12],cnt/LTimer_T[12],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[12] = ((cnt/LTimer[13] & & cnt/LTimer[12] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & !cnt/LTimer[13] & & cnt/LTimer[1] & &
< br / > cnt/LTimer[2] & & cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & &
< br / > cnt/LTimer[6] & & cnt/LTimer[7] & & cnt/LTimer[9] & & cnt/LTimer[10] & &
< br / > cnt/LTimer[11] & & cnt/LTimer[8])
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & cnt/LTimer[6] & &
< br / > cnt/LTimer[7] & & cnt/LTimer[9] & & cnt/LTimer[10] & & cnt/LTimer[11] & &
< br / > cnt/LTimer[8] & & !cnt/TimerTC));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/LTimer13 (cnt/LTimer[13],cnt/LTimer_T[13],!C8M,1'b0,1'b0,cnt/TimerTC);
< br / > assign cnt/LTimer_T[13] = ((cnt/LTimer[13] & & cnt/TimerTC)
< br / > || (cnt/LTimer[0] & & cnt/LTimer[1] & & cnt/LTimer[2] & &
< br / > cnt/LTimer[3] & & cnt/LTimer[5] & & cnt/LTimer[4] & & cnt/LTimer[6] & &
< br / > cnt/LTimer[7] & & cnt/LTimer[9] & & cnt/LTimer[10] & & cnt/LTimer[11] & &
< br / > cnt/LTimer[8] & & cnt/LTimer[12]));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/PORS_FSM_FFd1 (cnt/PORS_FSM_FFd1,cnt/PORS_FSM_FFd1_T,!C8M,1'b0,1'b0);
< br / > assign cnt/PORS_FSM_FFd1_T = (cnt/LTimer[13] & & !cnt/PORS_FSM_FFd1 & &
< br / > cnt/PORS_FSM_FFd2 & & !cnt/IPL2r);
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/PORS_FSM_FFd2 (cnt/PORS_FSM_FFd2,cnt/PORS_FSM_FFd2_D,!C8M,1'b0,1'b0);
< br / > assign cnt/PORS_FSM_FFd2_D = ((cnt/LTimer[13] & & !cnt/PORS_FSM_FFd1)
< br / > || (!cnt/LTimer[13] & & cnt/PORS_FSM_FFd2));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/RefReq (cnt/RefReq,cnt/RefReq_D,E,1'b0,1'b0);
< br / > assign cnt/RefReq_D = ((cnt/Timer[1] & & !cnt/Timer[3])
< br / > || (cnt/Timer[2] & & !cnt/Timer[3])
< br / > || (!cnt/Timer[1] & & !cnt/Timer[2] & & !cnt/Timer[0] & &
< br / > cnt/Timer[3]));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/RefUrgent (cnt/RefUrgent,cnt/RefUrgent_D,E,1'b0,1'b0);
< br / > assign cnt/RefUrgent_D = ((cnt/Timer[1] & & cnt/Timer[2] & & !cnt/Timer[3])
< br / > || (!cnt/Timer[1] & & !cnt/Timer[2] & & !cnt/Timer[0] & &
< br / > cnt/Timer[3]));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/Timer0 (cnt/Timer[0],cnt/Timer_D[0],E,1'b0,1'b0);
< br / > assign cnt/Timer_D[0] = (!cnt/TimerTC & & !cnt/Timer[0]);
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/Timer1 (cnt/Timer[1],cnt/Timer_D[1],E,1'b0,1'b0);
< br / > assign cnt/Timer_D[1] = ((!cnt/TimerTC & & cnt/Timer[1] & & !cnt/Timer[0])
< br / > || (!cnt/TimerTC & & !cnt/Timer[1] & & cnt/Timer[0]));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/Timer2 (cnt/Timer[2],cnt/Timer_T[2],E,1'b0,1'b0);
< br / > assign cnt/Timer_T[2] = ((cnt/TimerTC & & cnt/Timer[2])
< br / > || (!cnt/TimerTC & & cnt/Timer[1] & & cnt/Timer[0]));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cnt/Timer3 (cnt/Timer[3],cnt/Timer_T[3],E,1'b0,1'b0);
< br / > assign cnt/Timer_T[3] = ((cnt/TimerTC & & cnt/Timer[3])
< br / > || (!cnt/TimerTC & & cnt/Timer[1] & & cnt/Timer[2] & &
< br / > cnt/Timer[0]));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/TimerTC (cnt/TimerTC,cnt/TimerTC_D,E,1'b0,1'b0);
< br / > assign cnt/TimerTC_D = (!cnt/Timer[1] & & !cnt/Timer[2] & & !cnt/Timer[0] & &
< br / > cnt/Timer[3]);
< / td > < / tr > < tr > < td >
FDCPE FDCPE_cnt/nRESout (cnt/nRESout,cnt/nRESout_D,!C8M,1'b0,1'b0);
< br / > assign cnt/nRESout_D = ((cnt/LTimer[13] & & cnt/PORS_FSM_FFd1 & &
< br / > !cnt/PORS_FSM_FFd2)
< br / > || (cnt/PORS_FSM_FFd1 & & !cnt/PORS_FSM_FFd2 & &
< br / > cnt/nRESout));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_cs/nOverlay0 (cs/nOverlay0,cs/nOverlay0_T,FCLK,!nRES.PIN,1'b0);
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< br / > assign cs/nOverlay0_T = ((!A_FSB[23] & & A_FSB[22] & & !A_FSB[21] & & !A_FSB[20] & &
< br / > !cs/nOverlay0 & & !nAS_FSB)
< br / > || (!A_FSB[23] & & A_FSB[22] & & !A_FSB[21] & & !A_FSB[20] & &
< br / > !cs/nOverlay0 & & fsb/ASrf));
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_cs/nOverlay1 (cs/nOverlay1,cs/nOverlay0,FCLK,1'b0,1'b0,cs/nOverlay1_CE);
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< br / > assign cs/nOverlay1_CE = (nAS_FSB & & !fsb/ASrf);
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_fsb/ASrf (fsb/ASrf,!nAS_FSB,!FCLK,1'b0,1'b0);
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< / td > < / tr > < tr > < td >
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FDCPE FDCPE_fsb/Ready0r (fsb/Ready0r,fsb/Ready0r_D,FCLK,1'b0,1'b0);
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< br / > assign fsb/Ready0r_D = ((nAS_FSB & & !fsb/ASrf)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
< br / > !fsb/Ready0r & & !ram/RAMReady)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & !fsb/Ready0r & & !ram/RAMReady));
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_fsb/Ready1r (fsb/Ready1r,fsb/Ready1r_D,FCLK,1'b0,1'b0);
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< br / > assign fsb/Ready1r_D = ((A_FSB[14] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & !iobs/IOReady & & !nADoutLE1)
< br / > || (A_FSB[13] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & !iobs/IOReady & & !nADoutLE1)
2023-03-22 01:11:58 +00:00
< br / > || (nAS_FSB & & !fsb/ASrf)
2022-03-29 08:23:54 +00:00
< br / > || (A_FSB[23] & & !fsb/Ready1r & & !iobs/IOReady)
2023-03-25 07:49:44 +00:00
< br / > || (A_FSB[22] & & A_FSB[21] & & !fsb/Ready1r & &
2022-03-29 08:23:54 +00:00
< br / > !iobs/IOReady)
2023-03-25 07:49:44 +00:00
< br / > || (A_FSB[22] & & A_FSB[20] & & !fsb/Ready1r & &
< br / > !iobs/IOReady));
2023-03-22 01:11:58 +00:00
< / td > < / tr > < tr > < td >
FDCPE FDCPE_fsb/VPA (fsb/VPA,fsb/VPA_D,FCLK,1'b0,1'b0);
2023-03-25 07:49:44 +00:00
< br / > assign fsb/VPA_D = ((EXP15_.EXP)
< br / > || (A_FSB[14] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & fsb/VPA & & !iobs/IOReady & & !nAS_FSB & & !nADoutLE1)
< br / > || (A_FSB[14] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & fsb/VPA & & !iobs/IOReady & & fsb/ASrf & & !nADoutLE1)
< br / > || (A_FSB[13] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & fsb/VPA & & !iobs/IOReady & & !nAS_FSB & & !nADoutLE1)
< br / > || (A_FSB[13] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & fsb/VPA & & !iobs/IOReady & & fsb/ASrf & & !nADoutLE1)
< br / > || (A_FSB[9] & & A_FSB[8] & & A_FSB[15] & & A_FSB[14] & &
< br / > A_FSB[13] & & A_FSB[12] & & A_FSB[11] & & A_FSB[10] & & A_FSB[23] & &
< br / > A_FSB[22] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & & A_FSB[18] & &
< br / > A_FSB[17] & & A_FSB[16] & & iobs/IOReady & & !nAS_FSB)
< br / > || (A_FSB[22] & & A_FSB[20] & & !fsb/Ready1r & & fsb/VPA & &
< br / > !iobs/IOReady & & fsb/ASrf)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
< br / > !fsb/Ready0r & & fsb/VPA & & !nAS_FSB & & !ram/RAMReady)
2022-03-29 08:23:54 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
2023-03-22 01:11:58 +00:00
< br / > !fsb/Ready0r & & fsb/VPA & & fsb/ASrf & & !ram/RAMReady)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & !fsb/Ready0r & & fsb/VPA & & !nAS_FSB & & !ram/RAMReady)
2022-03-29 08:23:54 +00:00
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
2023-03-22 01:11:58 +00:00
< br / > !cs/nOverlay1 & & !fsb/Ready0r & & fsb/VPA & & fsb/ASrf & & !ram/RAMReady)
< br / > || (A_FSB[23] & & !fsb/Ready1r & & fsb/VPA & &
< br / > !iobs/IOReady & & !nAS_FSB)
2022-03-29 08:23:54 +00:00
< br / > || (A_FSB[23] & & !fsb/Ready1r & & fsb/VPA & &
2023-03-22 01:11:58 +00:00
< br / > !iobs/IOReady & & fsb/ASrf)
2023-03-25 07:49:44 +00:00
< br / > || (A_FSB[22] & & A_FSB[21] & & !fsb/Ready1r & & fsb/VPA & &
< br / > !iobs/IOReady & & !nAS_FSB)
< br / > || (A_FSB[22] & & A_FSB[21] & & !fsb/Ready1r & & fsb/VPA & &
< br / > !iobs/IOReady & & fsb/ASrf)
< br / > || (A_FSB[22] & & A_FSB[20] & & !fsb/Ready1r & & fsb/VPA & &
< br / > !iobs/IOReady & & !nAS_FSB));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/ALE0 (iobm/ALE0,iobm/ALE0_D,C16M,1'b0,1'b0);
< br / > assign iobm/ALE0_D = ((iobm/IOS_FSM_FFd1 & & !iobm/IOS_FSM_FFd2)
< br / > || (!iobm/IOS_FSM_FFd3 & & !iobm/IOS_FSM_FFd2 & &
< br / > !iobm/IOREQr));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/BERRrf (iobm/BERRrf,!nBERR_IOB,!C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/BERRrr (iobm/BERRrr,!nBERR_IOB,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/DTACKrf (iobm/DTACKrf,!nDTACK_IOB,!C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/DTACKrr (iobm/DTACKrr,!nDTACK_IOB,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/DoutOE (iobm/DoutOE,iobm/DoutOE_D,C16M,1'b0,1'b0);
< br / > assign iobm/DoutOE_D = ((iobs/IORW0 & & iobm/IOS_FSM_FFd3)
< br / > || (iobs/IORW0 & & iobm/IOS_FSM_FFd2));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_iobm/ES0 (iobm/ES[0],iobm/ES_T[0],C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/ES_T[0] = ((iobm/ES[0] & & !iobm/Er & & iobm/Er2)
< br / > || (!iobm/ES[0] & & !iobm/ES[1] & & !iobm/ES[2] & &
< br / > !iobm/ES[3] & & !iobm/ES[4] & & iobm/Er)
< br / > || (!iobm/ES[0] & & !iobm/ES[1] & & !iobm/ES[2] & &
< br / > !iobm/ES[3] & & !iobm/ES[4] & & !iobm/Er2));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/ES1 (iobm/ES[1],iobm/ES_D[1],C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/ES_D[1] = ((iobm/ES[0] & & iobm/ES[1])
< br / > || (!iobm/ES[0] & & !iobm/ES[1])
< br / > || (!iobm/Er & & iobm/Er2));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/ES2 (iobm/ES[2],iobm/ES_D[2],C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/ES_D[2] = ((!iobm/ES[0] & & !iobm/ES[2])
< br / > || (!iobm/ES[1] & & !iobm/ES[2])
< br / > || (!iobm/Er & & iobm/Er2)
< br / > || (iobm/ES[0] & & iobm/ES[1] & & iobm/ES[2])
< br / > || (!iobm/ES[2] & & !iobm/ES[3] & & iobm/ES[4]));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_iobm/ES3 (iobm/ES[3],iobm/ES_T[3],C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/ES_T[3] = ((iobm/ES[3] & & !iobm/Er & & iobm/Er2)
< br / > || (iobm/ES[0] & & iobm/ES[1] & & iobm/ES[2] & & iobm/Er)
< br / > || (iobm/ES[0] & & iobm/ES[1] & & iobm/ES[2] & & !iobm/Er2));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_iobm/ES4 (iobm/ES[4],iobm/ES_T[4],C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/ES_T[4] = ((iobm/ES[4] & & !iobm/Er & & iobm/Er2)
< br / > || (iobm/ES[0] & & iobm/ES[1] & & iobm/ES[2] & &
< br / > iobm/ES[3] & & iobm/Er)
< br / > || (iobm/ES[0] & & iobm/ES[1] & & iobm/ES[2] & &
< br / > iobm/ES[3] & & !iobm/Er2)
< br / > || (iobm/ES[0] & & iobm/ES[1] & & !iobm/ES[2] & &
< br / > !iobm/ES[3] & & iobm/ES[4]));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/ETACK (iobm/ETACK,iobm/ETACK_D,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/ETACK_D = (!nVMA_IOB & & !iobm/ES[0] & & !iobm/ES[1] & & !iobm/ES[2] & &
< br / > !iobm/ES[3] & & iobm/ES[4]);
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/Er (iobm/Er,E,!C8M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/Er2 (iobm/Er2,iobm/Er,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/IOACT (iobm/IOACT,iobm/IOACT_D,C16M,1'b0,1'b0);
< br / > assign iobm/IOACT_D = ((C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/RESrf & & iobm/RESrr)
< br / > || (iobm/IOS_FSM_FFd1 & & !iobm/IOS_FSM_FFd2)
< br / > || (!iobm/IOS_FSM_FFd3 & & !iobm/IOS_FSM_FFd2 & &
< br / > !iobm/IOREQr)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/ETACK)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
< br / > iobm/BERRrf & & iobm/BERRrr)
< br / > || (C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
< br / > iobm/DTACKrf & & iobm/DTACKrr));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_iobm/IOBERR (iobm/IOBERR,iobm/IOBERR_T,C16M,1'b0,1'b0);
2023-03-25 07:49:44 +00:00
< br / > assign iobm/IOBERR_T = ((C8M & & !nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & !iobm/IOBERR & & iobm/BERRrf & &
< br / > iobm/BERRrr)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & !nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & !iobm/IOBERR & & iobm/DTACKrf & &
< br / > iobm/DTACKrr)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & !nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & !iobm/IOBERR & & iobm/RESrf & &
< br / > iobm/RESrr)
2023-03-25 07:49:44 +00:00
< br / > || (C8M & & nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & iobm/IOBERR & & iobm/RESrf & &
< br / > iobm/RESrr)
2022-03-29 08:23:54 +00:00
< br / > || (iobm/IOS_FSM_FFd3 & & !iobm/IOS_FSM_FFd1 & &
< br / > !iobm/IOS_FSM_FFd2 & & iobm/IOBERR)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & iobm/IOBERR & & iobm/ETACK)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & !nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & !iobm/IOBERR & & iobm/ETACK)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & iobm/IOBERR & & iobm/BERRrf & &
< br / > iobm/BERRrr)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & nBERR_IOB & & iobm/IOS_FSM_FFd3 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2 & & iobm/IOBERR & & iobm/DTACKrf & &
< br / > iobm/DTACKrr));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/IOREQr (iobm/IOREQr,iobs/IOREQ,!C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/IOS_FSM_FFd1 (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd1_D,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/IOS_FSM_FFd1_D = ((iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1)
< br / > || (!iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd2));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_iobm/IOS_FSM_FFd2 (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_T,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/IOS_FSM_FFd2_T = ((iobm/IOS_FSM_FFd3 & & !iobm/IOS_FSM_FFd1 & &
< br / > !iobm/IOS_FSM_FFd2)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd2 & & iobm/ETACK)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd2 & & iobm/BERRrf & & iobm/BERRrr)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd2 & & iobm/DTACKrf & & iobm/DTACKrr)
2023-03-22 01:11:58 +00:00
< br / > || (C8M & & iobm/IOS_FSM_FFd3 & & iobm/IOS_FSM_FFd1 & &
2022-03-29 08:23:54 +00:00
< br / > iobm/IOS_FSM_FFd2 & & iobm/RESrf & & iobm/RESrr));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/IOS_FSM_FFd3 (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobm/IOS_FSM_FFd3_D = ((iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2)
< br / > || (iobm/IOS_FSM_FFd3 & & !iobm/IOS_FSM_FFd1 & &
< br / > !iobm/IOS_FSM_FFd2)
2023-03-25 07:49:44 +00:00
< br / > || (!C8M & & !iobm/IOS_FSM_FFd1 & & !iobm/IOS_FSM_FFd2 & &
< br / > iobm/IOREQr & & !nAoutOE));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/RESrf (iobm/RESrf,!nRES.PIN,!C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/RESrr (iobm/RESrr,!nRES.PIN,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/VPArf (iobm/VPArf,!nVPA_IOB,!C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobm/VPArr (iobm/VPArr,!nVPA_IOB,C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/ALE0 (iobs/ALE0,iobs/ALE0_D,FCLK,1'b0,1'b0);
< br / > assign iobs/ALE0_D = (iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/Clear1 (iobs/Clear1,iobs/Clear1_D,FCLK,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobs/Clear1_D = (iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & !nADoutLE1);
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/IOACTr (iobs/IOACTr,iobm/IOACT,FCLK,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/IOL0 (iobs/IOL0,iobs/IOL0_D,FCLK,1'b0,1'b0,iobs/IOL0_CE);
2022-03-29 08:23:54 +00:00
< br / > assign iobs/IOL0_D = ((!nLDS_FSB & & nADoutLE1)
< br / > || (iobs/IOL1 & & !nADoutLE1));
< br / > assign iobs/IOL0_CE = (iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1);
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/IOL1 (iobs/IOL1,!nLDS_FSB,FCLK,1'b0,1'b0,iobs/Load1);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/IOREQ (iobs/IOREQ,iobs/IOREQ_D,FCLK,1'b0,1'b0);
2023-03-25 07:49:44 +00:00
< br / > assign iobs/IOREQ_D = ((EXP16_.EXP)
< br / > || (A_FSB[23] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd1)
< br / > || (A_FSB[23] & & !iobs/Once & & !iobs/PS_FSM_FFd1 & &
< br / > fsb/ASrf)
< br / > || (A_FSB[22] & & A_FSB[21] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd1)
< br / > || (A_FSB[22] & & A_FSB[21] & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[22] & & A_FSB[20] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd1)
< br / > || (iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (iobs/PS_FSM_FFd2 & & !iobs/IOACTr)
< br / > || (!iobs/PS_FSM_FFd1 & & !nADoutLE1));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_iobs/IORW0 (iobs/IORW0,iobs/IORW0_D,FCLK,1'b0,1'b0);
< br / > assign iobs/IORW0_D = ((!iobs/IORW1 & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & &
< br / > !nADoutLE1)
< br / > || (!A_FSB[23] & & !A_FSB[21] & & !A_FSB[20] & & !iobs/IORW0 & &
2022-03-29 08:23:54 +00:00
< br / > nADoutLE1)
2023-03-25 07:49:44 +00:00
< br / > || (A_FSB[23] & & !nWE_FSB & & !iobs/Once & & !nAS_FSB & &
2023-03-22 01:11:58 +00:00
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & nADoutLE1)
2023-03-25 07:49:44 +00:00
< br / > || (A_FSB[23] & & !nWE_FSB & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf & & nADoutLE1)
< br / > || (A_FSB[22] & & A_FSB[21] & & !nWE_FSB & & !iobs/Once & &
2023-03-22 01:11:58 +00:00
< br / > !nAS_FSB & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & nADoutLE1)
2023-03-25 07:49:44 +00:00
< br / > || (nROMWE_OBUF.EXP)
< br / > || (A_FSB[22] & & A_FSB[21] & & !nWE_FSB & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf & & nADoutLE1)
< br / > || (A_FSB[22] & & A_FSB[20] & & !nWE_FSB & & !iobs/Once & &
2023-03-22 01:11:58 +00:00
< br / > !nAS_FSB & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & nADoutLE1)
2023-03-25 07:49:44 +00:00
< br / > || (A_FSB[22] & & A_FSB[20] & & !nWE_FSB & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf & & nADoutLE1)
< br / > || (A_FSB[14] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & !iobs/Once & &
< br / > cs/nOverlay1 & & !nAS_FSB & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & &
< br / > nADoutLE1)
< br / > || (A_FSB[13] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & !iobs/Once & &
< br / > cs/nOverlay1 & & !nAS_FSB & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & &
< br / > nADoutLE1)
< br / > || (!iobs/IORW0 & & iobs/PS_FSM_FFd2)
< br / > || (!iobs/IORW0 & & iobs/PS_FSM_FFd1)
< br / > || (iobs/Once & & !iobs/IORW0 & & nADoutLE1)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !iobs/IORW0 & & nADoutLE1)
< br / > || (!iobs/IORW0 & & nAS_FSB & & !fsb/ASrf & & nADoutLE1));
2023-03-22 01:11:58 +00:00
< / td > < / tr > < tr > < td >
FTCPE FTCPE_iobs/IORW1 (iobs/IORW1,iobs/IORW1_T,FCLK,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobs/IORW1_T = ((iobs/Once)
< br / > || (!nADoutLE1)
2023-03-22 01:11:58 +00:00
< br / > || (fsb/Ready1r.EXP)
2022-03-29 08:23:54 +00:00
< br / > || (nAS_FSB & & !fsb/ASrf)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[21])
2023-03-25 07:49:44 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[19])
< br / > || (!A_FSB[23] & & !A_FSB[22] & & nWE_FSB)
2022-03-29 08:23:54 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !cs/nOverlay1)
2023-03-25 07:49:44 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[20])
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[18])
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[17])
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[16])
< br / > || (!A_FSB[23] & & !A_FSB[21] & & !A_FSB[20])
2022-03-29 08:23:54 +00:00
< br / > || (nWE_FSB & & iobs/IORW1)
2023-03-25 07:49:44 +00:00
< br / > || (!nWE_FSB & & !iobs/IORW1)
< br / > || (!iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_iobs/IOReady (iobs/IOReady,iobs/IOReady_T,FCLK,1'b0,1'b0);
2023-03-25 07:49:44 +00:00
< br / > assign iobs/IOReady_T = ((iobs/IOReady & & nAS_FSB & & !fsb/ASrf)
< br / > || (iobs/Once & & iobs/IOReady & & !iobs/PS_FSM_FFd2 & &
2022-03-29 08:23:54 +00:00
< br / > !iobs/IOACTr & & iobm/IOBERR & & nADoutLE1)
< br / > || (iobs/Once & & !iobs/IOReady & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/IOACTr & & !iobm/IOBERR & & nADoutLE1)
< br / > || (iobs/Once & & !iobs/IOReady & & !iobs/PS_FSM_FFd2 & &
2023-03-25 07:49:44 +00:00
< br / > !iobs/IOACTr & & !iobm/IOBERR & & fsb/ASrf & & nADoutLE1));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/IOU0 (iobs/IOU0,iobs/IOU0_D,FCLK,1'b0,1'b0,iobs/IOU0_CE);
2022-03-29 08:23:54 +00:00
< br / > assign iobs/IOU0_D = ((!nUDS_FSB & & nADoutLE1)
< br / > || (iobs/IOU1 & & !nADoutLE1));
< br / > assign iobs/IOU0_CE = (iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1);
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/IOU1 (iobs/IOU1,!nUDS_FSB,FCLK,1'b0,1'b0,iobs/Load1);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/Load1 (iobs/Load1,iobs/Load1_D,FCLK,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobs/Load1_D = ((iobs/Once)
< br / > || (!nADoutLE1)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[21])
2023-03-25 07:49:44 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[19])
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[17])
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[16])
2023-03-22 01:11:58 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !cs/nOverlay1)
2023-03-25 07:49:44 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[20])
< br / > || (!A_FSB[23] & & !A_FSB[22] & & !A_FSB[18])
< br / > || (!A_FSB[23] & & !A_FSB[21] & & !A_FSB[20])
< br / > || (!A_FSB[14] & & !A_FSB[13] & & !A_FSB[23] & & !A_FSB[22])
2022-03-29 08:23:54 +00:00
< br / > || (nAS_FSB & & !fsb/ASrf)
2023-03-25 07:49:44 +00:00
< br / > || (!iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & nWE_FSB));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_iobs/Once (iobs/Once,iobs/Once_T,FCLK,1'b0,1'b0);
< br / > assign iobs/Once_T = ((A_FSB[13] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & !iobs/Once & &
< br / > cs/nOverlay1 & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[14] & & !A_FSB[23] & & !A_FSB[22] & & A_FSB[21] & &
< br / > A_FSB[20] & & A_FSB[19] & & A_FSB[18] & & A_FSB[17] & & A_FSB[16] & &
< br / > !nWE_FSB & & !iobs/Once & & cs/nOverlay1 & & !nAS_FSB & & nADoutLE1)
< br / > || (A_FSB[14] & & !A_FSB[23] & & !A_FSB[22] & & A_FSB[21] & &
< br / > A_FSB[20] & & A_FSB[19] & & A_FSB[18] & & A_FSB[17] & & A_FSB[16] & &
< br / > !nWE_FSB & & !iobs/Once & & cs/nOverlay1 & & fsb/ASrf & & nADoutLE1)
< br / > || (A_FSB[13] & & !A_FSB[23] & & !A_FSB[22] & & A_FSB[21] & &
< br / > A_FSB[20] & & A_FSB[19] & & A_FSB[18] & & A_FSB[17] & & A_FSB[16] & &
< br / > !nWE_FSB & & !iobs/Once & & cs/nOverlay1 & & !nAS_FSB & & nADoutLE1)
< br / > || (A_FSB[13] & & !A_FSB[23] & & !A_FSB[22] & & A_FSB[21] & &
< br / > A_FSB[20] & & A_FSB[19] & & A_FSB[18] & & A_FSB[17] & & A_FSB[16] & &
< br / > !nWE_FSB & & !iobs/Once & & cs/nOverlay1 & & fsb/ASrf & & nADoutLE1)
< br / > || (A_FSB[22] & & A_FSB[21] & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[22] & & A_FSB[20] & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[14] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & !iobs/Once & &
< br / > cs/nOverlay1 & & !nAS_FSB & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (A_FSB[14] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & !iobs/Once & &
< br / > cs/nOverlay1 & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[13] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & !iobs/Once & &
< br / > cs/nOverlay1 & & !nAS_FSB & & !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (iobs/Once & & nAS_FSB & & !fsb/ASrf)
< br / > || (A_FSB[23] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (A_FSB[23] & & !iobs/Once & & !iobs/PS_FSM_FFd2 & &
< br / > !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[22] & & A_FSB[21] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (A_FSB[22] & & A_FSB[20] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_iobs/PS_FSM_FFd1 (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,FCLK,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign iobs/PS_FSM_FFd1_D = ((iobs/PS_FSM_FFd2)
< br / > || (iobs/PS_FSM_FFd1 & & iobs/IOACTr));
< / td > < / tr > < tr > < td >
2023-03-25 07:49:44 +00:00
FTCPE FTCPE_iobs/PS_FSM_FFd2 (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_T,FCLK,1'b0,1'b0);
< br / > assign iobs/PS_FSM_FFd2_T = ((iobs/nBERR_FSB.EXP)
< br / > || (A_FSB[23] & & !iobs/Once & & !iobs/PS_FSM_FFd2 & &
< br / > !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[22] & & A_FSB[21] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (A_FSB[22] & & A_FSB[21] & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (A_FSB[22] & & A_FSB[20] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1)
< br / > || (A_FSB[22] & & A_FSB[20] & & !iobs/Once & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & fsb/ASrf)
< br / > || (iobs/PS_FSM_FFd1 & & iobs/IOACTr)
< br / > || (!iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1 & & !nADoutLE1)
< br / > || (A_FSB[23] & & !iobs/Once & & !nAS_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/PS_FSM_FFd1));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign nADoutLE0 = (!iobm/ALE0 & & !iobs/ALE0);
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_nADoutLE1 (nADoutLE1,nADoutLE1_D,FCLK,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign nADoutLE1_D = ((iobs/Load1)
< br / > || (!iobs/Clear1 & & !nADoutLE1));
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_nAS_IOB (nAS_IOB_I,nAS_IOB,!C16M,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< br / > assign nAS_IOB = ((!iobm/IOS_FSM_FFd3 & & !iobm/IOS_FSM_FFd2)
< br / > || (iobm/IOS_FSM_FFd1 & & !iobm/IOS_FSM_FFd2));
< br / > assign nAS_IOB = nAS_IOB_OE ? nAS_IOB_I : 1'bZ;
2023-03-25 07:49:44 +00:00
< br / > assign nAS_IOB_OE = !nAoutOE;
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_nAoutOE (nAoutOE,nAoutOE_D,!C8M,1'b0,1'b0);
< br / > assign nAoutOE_D = (!nBR_IOB & & cnt/PORS_FSM_FFd1 & & !cnt/PORS_FSM_FFd2);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_nBERR_FSB (nBERR_FSB,nBERR_FSB_T,FCLK,1'b0,1'b0);
2023-03-25 07:49:44 +00:00
< br / > assign nBERR_FSB_T = ((iobs/Once & & !nBERR_FSB & & !iobs/PS_FSM_FFd2 & &
2023-03-22 01:11:58 +00:00
< br / > !iobs/IOACTr & & !iobm/IOBERR & & nADoutLE1)
< br / > || (iobs/Once & & !nAS_FSB & & nBERR_FSB & &
< br / > !iobs/PS_FSM_FFd2 & & !iobs/IOACTr & & iobm/IOBERR & & nADoutLE1)
< br / > || (iobs/Once & & nBERR_FSB & & !iobs/PS_FSM_FFd2 & &
2023-03-25 07:49:44 +00:00
< br / > !iobs/IOACTr & & iobm/IOBERR & & fsb/ASrf & & nADoutLE1)
< br / > || (nAS_FSB & & !nBERR_FSB & & !fsb/ASrf));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FTCPE FTCPE_nBR_IOB (nBR_IOB,nBR_IOB_T,!C8M,1'b0,1'b0);
< br / > assign nBR_IOB_T = ((nBR_IOB & & !cnt/PORS_FSM_FFd1 & & !cnt/PORS_FSM_FFd2)
< br / > || (!nBR_IOB & & !cnt/PORS_FSM_FFd1 & & cnt/PORS_FSM_FFd2 & &
< br / > cnt/IPL2r));
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_nCAS (nCAS,!ram/RASEL,!FCLK,1'b0,1'b0);
2022-03-29 08:23:54 +00:00
< / td > < / tr > < tr > < td >
2023-03-22 01:11:58 +00:00
FDCPE FDCPE_nDTACK_FSB (nDTACK_FSB,nDTACK_FSB_D,FCLK,1'b0,1'b0);
2023-03-25 07:49:44 +00:00
< br / > assign nDTACK_FSB_D = ((iobs/IOREQ.EXP)
< br / > || (nAS_FSB & & !fsb/ASrf)
< br / > || (A_FSB[23] & & !fsb/Ready1r & & !iobs/IOReady & &
< br / > nDTACK_FSB)
< br / > || (A_FSB[22] & & A_FSB[21] & & !fsb/Ready1r & &
< br / > !iobs/IOReady & & nDTACK_FSB)
< br / > || (A_FSB[22] & & A_FSB[20] & & !fsb/Ready1r & &
< br / > !iobs/IOReady & & nDTACK_FSB)
2023-03-22 01:11:58 +00:00
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
< br / > !fsb/Ready0r & & nDTACK_FSB & & !ram/RAMReady)
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< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & !fsb/Ready0r & & nDTACK_FSB & & !ram/RAMReady)
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< br / > || (A_FSB[14] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & !iobs/IOReady & & nDTACK_FSB & & !nADoutLE1)
< br / > || (A_FSB[13] & & A_FSB[21] & & A_FSB[20] & & A_FSB[19] & &
< br / > A_FSB[18] & & A_FSB[17] & & A_FSB[16] & & !nWE_FSB & & cs/nOverlay1 & &
< br / > !fsb/Ready1r & & !iobs/IOReady & & nDTACK_FSB & & !nADoutLE1));
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< / td > < / tr > < tr > < td >
FDCPE FDCPE_nDinLE (nDinLE,nDinLE_D,!C16M,1'b0,1'b0);
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< br / > assign nDinLE_D = (iobm/IOS_FSM_FFd1 & & iobm/IOS_FSM_FFd2);
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign nDinOE = ((A_FSB[23] & & nWE_FSB & & !nAS_FSB)
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< br / > || (A_FSB[22] & & A_FSB[21] & & nWE_FSB & & !nAS_FSB)
< br / > || (A_FSB[22] & & A_FSB[20] & & nWE_FSB & & !nAS_FSB));
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign nDoutOE = !((iobm/DoutOE & & !nAoutOE));
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< / td > < / tr > < tr > < td >
FDCPE FDCPE_nLDS_IOB (nLDS_IOB_I,nLDS_IOB,!C16M,1'b0,1'b0);
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< br / > assign nLDS_IOB = ((iobs/IOL0 & & !iobm/IOS_FSM_FFd3 & &
< br / > iobm/IOS_FSM_FFd2)
< br / > || (iobs/IOL0 & & iobm/IOS_FSM_FFd1 & &
< br / > iobm/IOS_FSM_FFd2)
< br / > || (!iobs/IORW0 & & iobs/IOL0 & & iobm/IOS_FSM_FFd3 & &
< br / > !iobm/IOS_FSM_FFd1));
< br / > assign nLDS_IOB = nLDS_IOB_OE ? nLDS_IOB_I : 1'bZ;
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< br / > assign nLDS_IOB_OE = !nAoutOE;
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign nOE = !((nWE_FSB & & !nAS_FSB));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign nRAMLWE = !((!nWE_FSB & & !nLDS_FSB & & !nAS_FSB & & ram/RAMEN));
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign nRAMUWE = !((!nWE_FSB & & !nUDS_FSB & & !nAS_FSB & & ram/RAMEN));
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign nRAS = !(((ram/RefRAS)
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< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & & !nAS_FSB & &
< br / > ram/RAMEN)
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< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
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< br / > !cs/nOverlay1 & & !nAS_FSB & & ram/RAMEN)));
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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assign nRES_I = 1'b0;
< br / > assign nRES = nRES_OE ? nRES_I : 1'bZ;
< br / > assign nRES_OE = !cnt/nRESout;
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign nROMCS = !(((!A_FSB[23] & & A_FSB[22] & & !A_FSB[21] & & !A_FSB[20])
< br / > || (!A_FSB[23] & & !A_FSB[21] & & !A_FSB[20] & &
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< br / > !cs/nOverlay1)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign nROMWE = !((!nWE_FSB & & !nAS_FSB));
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_nUDS_IOB (nUDS_IOB_I,nUDS_IOB,!C16M,1'b0,1'b0);
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< br / > assign nUDS_IOB = ((iobs/IOU0 & & !iobm/IOS_FSM_FFd3 & &
< br / > iobm/IOS_FSM_FFd2)
< br / > || (iobs/IOU0 & & iobm/IOS_FSM_FFd1 & &
< br / > iobm/IOS_FSM_FFd2)
< br / > || (!iobs/IORW0 & & iobs/IOU0 & & iobm/IOS_FSM_FFd3 & &
< br / > !iobm/IOS_FSM_FFd1));
< br / > assign nUDS_IOB = nUDS_IOB_OE ? nUDS_IOB_I : 1'bZ;
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< br / > assign nUDS_IOB_OE = !nAoutOE;
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< / td > < / tr > < tr > < td >
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FTCPE FTCPE_nVMA_IOB (nVMA_IOB_I,nVMA_IOB_T,C16M,1'b0,1'b0);
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< br / > assign nVMA_IOB_T = ((!nVMA_IOB & & !iobm/ES[0] & & !iobm/ES[1] & & !iobm/ES[2] & &
< br / > !iobm/ES[3] & & !iobm/ES[4])
< br / > || (nVMA_IOB & & iobm/ES[0] & & iobm/ES[1] & & iobm/ES[2] & &
< br / > !iobm/ES[3] & & !iobm/ES[4] & & iobm/IOACT & & iobm/VPArf & &
< br / > iobm/VPArr));
< br / > assign nVMA_IOB = nVMA_IOB_OE ? nVMA_IOB_I : 1'bZ;
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< br / > assign nVMA_IOB_OE = !nAoutOE;
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
assign nVPA_FSB = !((fsb/VPA & & !nAS_FSB));
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_ram/BACTr (ram/BACTr,ram/BACTr_D,FCLK,1'b0,1'b0);
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< br / > assign ram/BACTr_D = (nAS_FSB & & !fsb/ASrf);
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_ram/RAMEN (ram/RAMEN,ram/RAMEN_D,FCLK,1'b0,1'b0);
< br / > assign ram/RAMEN_D = ((!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & & !nAS_FSB & &
< br / > !ram/RS_FSM_FFd1 & & ram/RAMEN)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
< br / > !ram/RS_FSM_FFd1 & & ram/RAMEN & & fsb/ASrf)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & !nAS_FSB & & !ram/RS_FSM_FFd1 & & ram/RAMEN)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & !ram/RS_FSM_FFd1 & & ram/RAMEN & & fsb/ASrf)
< br / > || (ram/RS_FSM_FFd2 & & ram/RAMEN)
< br / > || (ram/RS_FSM_FFd3 & & ram/RAMEN)
< br / > || (!ram/RS_FSM_FFd1 & & !ram/RefUrgent & & ram/RAMEN & &
< br / > ram/BACTr)
< br / > || (!ram/RS_FSM_FFd1 & & !ram/RefUrgent & & ram/RAMEN & &
< br / > !ram/RefReq)
< br / > || (nAS_FSB & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !fsb/ASrf));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RAMReady (ram/RAMReady,ram/RAMReady_D,FCLK,1'b0,1'b0);
< br / > assign ram/RAMReady_D = ((RA_6_OBUF.EXP)
< br / > || (A_FSB[23] & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !ram/RefReq)
< br / > || (A_FSB[22] & & !A_FSB[21] & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (A_FSB[22] & & !A_FSB[21] & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & !ram/RefReq)
< br / > || (A_FSB[22] & & cs/nOverlay1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (!A_FSB[22] & & !cs/nOverlay1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3)
< br / > || (A_FSB[23] & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (nAS_FSB & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !fsb/ASrf));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RASEL (ram/RASEL,ram/RASEL_D,FCLK,1'b0,1'b0);
< br / > assign ram/RASEL_D = ((A_FSB[22] & & !A_FSB[21] & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & !ram/RefReq)
< br / > || (A_FSB[22] & & cs/nOverlay1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & !ram/RefReq)
< br / > || (!A_FSB[22] & & !cs/nOverlay1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & !ram/RefReq)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & & !nAS_FSB & &
< br / > !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3 & & !ram/RAMEN)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
< br / > !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3 & & !ram/RAMEN & & fsb/ASrf)
< br / > || (ram/RAMReady.EXP)
< br / > || (A_FSB[23] & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (A_FSB[23] & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !ram/RefReq)
< br / > || (A_FSB[22] & & !A_FSB[21] & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (A_FSB[22] & & cs/nOverlay1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (!A_FSB[22] & & !cs/nOverlay1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RefUrgent & & !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (ram/RS_FSM_FFd1 & & ram/RS_FSM_FFd2)
< br / > || (ram/RS_FSM_FFd2 & & ram/RS_FSM_FFd3)
< br / > || (!nAS_FSB & & ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd3)
< br / > || (ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd3 & & fsb/ASrf)
< br / > || (nAS_FSB & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !fsb/ASrf));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RS_FSM_FFd1 (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_D,FCLK,1'b0,1'b0);
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< br / > assign ram/RS_FSM_FFd1_D = ((ram/RS_FSM_FFd1 & & ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & fsb/ASrf)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & & !nAS_FSB & &
< br / > !ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd2 & & ram/RefUrgent & & !ram/RAMEN)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
2023-03-22 01:11:58 +00:00
< br / > !ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd2 & & ram/RefUrgent & & !ram/RAMEN & &
< br / > fsb/ASrf)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
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< br / > !cs/nOverlay1 & & !nAS_FSB & & !ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd2 & &
2023-03-22 01:11:58 +00:00
< br / > ram/RefUrgent & & !ram/RAMEN)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
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< br / > !cs/nOverlay1 & & !ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd2 & &
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< br / > ram/RefUrgent & & !ram/RAMEN & & fsb/ASrf)
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< br / > || (ram/RS_FSM_FFd1 & & ram/RS_FSM_FFd2)
< br / > || (!ram/RS_FSM_FFd1 & & ram/RS_FSM_FFd3)
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< br / > || (!nAS_FSB & & ram/RS_FSM_FFd1 & & ram/RefUrgent & &
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< br / > !ram/RS_FSM_FFd3));
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< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RS_FSM_FFd2 (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_D,FCLK,1'b0,1'b0);
< br / > assign ram/RS_FSM_FFd2_D = ((nAS_FSB & & !ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !fsb/ASrf)
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< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & & !nAS_FSB & &
< br / > !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3)
< br / > || (!A_FSB[23] & & !A_FSB[22] & & cs/nOverlay1 & &
< br / > !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3 & & fsb/ASrf)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & !nAS_FSB & & !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3)
< br / > || (!A_FSB[23] & & A_FSB[22] & & A_FSB[21] & &
< br / > !cs/nOverlay1 & & !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3 & & fsb/ASrf)
< br / > || (ram/RS_FSM_FFd1 & & ram/RS_FSM_FFd2)
< br / > || (!nAS_FSB & & ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd3)
< br / > || (ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd3 & & fsb/ASrf)
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< br / > || (!ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & ram/BACTr)
< br / > || (!ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !ram/RefReq));
< / td > < / tr > < tr > < td >
FTCPE FTCPE_ram/RS_FSM_FFd3 (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,FCLK,1'b0,1'b0);
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< br / > assign ram/RS_FSM_FFd3_T = ((ram/RS_FSM_FFd1.EXP)
< br / > || (!ram/RS_FSM_FFd1 & & ram/RS_FSM_FFd2 & &
< br / > ram/RS_FSM_FFd3)
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< br / > || (A_FSB[23] & & !ram/RS_FSM_FFd1 & & !ram/RS_FSM_FFd2 & &
< br / > !ram/RS_FSM_FFd3)
< br / > || (nAS_FSB & & !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3 & &
< br / > !fsb/ASrf)
< br / > || (!ram/RS_FSM_FFd2 & & !ram/RefUrgent & &
< br / > !ram/RS_FSM_FFd3 & & !ram/RAMEN)
< br / > || (A_FSB[22] & & !A_FSB[21] & & !ram/RS_FSM_FFd1 & &
< br / > !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3)
< br / > || (A_FSB[22] & & cs/nOverlay1 & & !ram/RS_FSM_FFd1 & &
< br / > !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3)
< br / > || (!A_FSB[22] & & !cs/nOverlay1 & & !ram/RS_FSM_FFd1 & &
< br / > !ram/RS_FSM_FFd2 & & !ram/RS_FSM_FFd3));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RefDone (ram/RefDone,ram/RefDone_D,FCLK,1'b0,1'b0);
< br / > assign ram/RefDone_D = ((ram/RefDone & & ram/RefReqSync)
< br / > || (!ram/RS_FSM_FFd1 & & ram/RS_FSM_FFd2 & &
< br / > ram/RefReqSync));
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RefRAS (ram/RefRAS,ram/RefRAS_D,FCLK,1'b0,1'b0);
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< br / > assign ram/RefRAS_D = (!ram/RS_FSM_FFd1 & & ram/RS_FSM_FFd2);
< / td > < / tr > < tr > < td >
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FDCPE FDCPE_ram/RefReq (ram/RefReq,ram/RefReq_D,FCLK,1'b0,1'b0);
< br / > assign ram/RefReq_D = (!ram/RefDone & & ram/RefReqSync);
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RefReqSync (ram/RefReqSync,cnt/RefReq,FCLK,1'b0,1'b0);
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RefUrgent (ram/RefUrgent,ram/RefUrgent_D,FCLK,1'b0,1'b0);
< br / > assign ram/RefUrgent_D = (!ram/RefDone & & ram/RegUrgentSync);
< / td > < / tr > < tr > < td >
FDCPE FDCPE_ram/RegUrgentSync (ram/RegUrgentSync,cnt/RefUrgent,FCLK,1'b0,1'b0);
< / td > < / tr > < tr > < td >
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Register Legend:
< br / > FDCPE (Q,D,C,CLR,PRE,CE);
< br / > FTCPE (Q,D,C,CLR,PRE,CE);
< br / > LDCP (Q,D,G,CLR,PRE);
< / td > < / tr > < tr > < td >
< / td > < / tr >
< / table >
< form > < span class = "pgRef" > < table width = "90%" align = "center" > < tr >
< td align = "left" > < input type = "button" onclick = "javascript:parent.leftnav.showTop()" onmouseover = "window.status='goto top of page'; return true;" onmouseout = "window.status=''" value = "back to top" > < / td >
< td align = "right" > < input type = "button" onclick = "window.print()" onmouseover = "window.status='print page'; return true;" onmouseout = "window.status=''" value = "print page" > < / td >
< / tr > < / table > < / span > < / form >
< / body > < / html >
