2022-02-14 21:38:58 +00:00
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< h3 align = "center" > Failure Table< / h3 >
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< th align = "left" > Signal Name< / th >
< th align = "left" > FB1< / th >
< th align = "left" > FB2< / th >
< th align = "left" > FB3< / th >
< th align = "left" > FB4< / th >
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< th align = "left" > Signal Name< / th >
< th align = "left" > FB5< / th >
< th align = "left" > FB6< / th >
< th align = "left" > FB7< / th >
< th align = "left" > FB8< / th >
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< tr > < td > Legend:< / td > < / tr >
< tr > < td > ce - signal clock enable cannot be placed< / td > < / tr >
< tr > < td > clk - signal clock cannot be placed< / td > < / tr >
< tr > < td > fbi - insufficient function block inputs available to place signal< / td > < / tr >
< tr > < td > io - insufficient I/O pins available to place output< / td > < / tr >
< tr > < td > loc - signal cannot be placed in this FB because it is assigned to a different FB< / td > < / tr >
< tr > < td > mc - insufficient macrocells available to place signal< / td > < / tr >
< tr > < td > oe - signal output enable cannot be placed< / td > < / tr >
< tr > < td > pt - insufficient product terms available to place signal< / td > < / tr >
< tr > < td > sr - signal set/reset cannot be placed< / td > < / tr >
< tr > < td > unk - unknown reason for failure - Please contact Xilinx Support< / td > < / tr >
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