mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-12-02 16:49:21 +00:00
1016 lines
70 KiB
HTML
1016 lines
70 KiB
HTML
|
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
|
||
|
|
<h3 align='center'>Equations</h3>
|
||
|
|
<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
|
||
|
|
<tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
********** Mapped Logic **********
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign $OpTx$FX_DC$591 = (nAS_FSB && !fsb/ASrf);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign CLK20EN = SW[0];
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign CLK25EN = !SW[0];
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_IPL2r0 (IPL2r0,!nIPL2,CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_IPL2r1 (IPL2r1,IPL2r0,CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[0] = ((A_FSB[10] && !ram/RASEL)
|
||
|
|
<br/> || (ram/RASEL && A_FSB[1]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[1] = ((A_FSB[11] && !ram/RASEL)
|
||
|
|
<br/> || (ram/RASEL && A_FSB[2]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[2] = ((A_FSB[12] && !ram/RASEL)
|
||
|
|
<br/> || (ram/RASEL && A_FSB[3]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[3] = ((A_FSB[13] && !ram/RASEL)
|
||
|
|
<br/> || (ram/RASEL && A_FSB[4]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[4] = ((A_FSB[14] && !ram/RASEL)
|
||
|
|
<br/> || (ram/RASEL && A_FSB[5]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[5] = ((A_FSB[15] && !ram/RASEL)
|
||
|
|
<br/> || (ram/RASEL && A_FSB[6]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[6] = ((A_FSB[16] && !ram/RASEL)
|
||
|
|
<br/> || (ram/RASEL && A_FSB[7]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[7] = ((A_FSB[8] && ram/RASEL)
|
||
|
|
<br/> || (A_FSB[17] && !ram/RASEL));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[8] = ((A_FSB[9] && !A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
|
||
|
|
<br/> ram/RASEL)
|
||
|
|
<br/> || (A_FSB[9] && !A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> !cs/nOverlay1 && ram/RASEL)
|
||
|
|
<br/> || (A_FSB[23] && A_FSB[18])
|
||
|
|
<br/> || (A_FSB[18] && !ram/RASEL)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && A_FSB[18])
|
||
|
|
<br/> || (A_FSB[22] && A_FSB[18] && cs/nOverlay1)
|
||
|
|
<br/> || (!A_FSB[22] && A_FSB[18] && !cs/nOverlay1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[9] = ((A_FSB[20] && ram/RASEL)
|
||
|
|
<br/> || (A_FSB[19] && !ram/RASEL));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[10] = A_FSB[21];
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign RA[11] = A_FSB[19];
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_RESDone (RESDone,1'b1,CLK_FSB,1'b0,1'b0,RESDone_CE);
|
||
|
|
<br/> assign RESDone_CE = (!RESr0 && !RESr1 && RESr2);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_RESr0 (RESr0,!nRES,CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_RESr1 (RESr1,RESr0,CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_RESr2 (RESr2,RESr1,CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt0 (cnt/RefCnt[0],1'b1,CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt1 (cnt/RefCnt[1],cnt/RefCnt[0],CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt2 (cnt/RefCnt[2],cnt/RefCnt_T[2],CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/RefCnt_T[2] = (cnt/RefCnt[0] && cnt/RefCnt[1]);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt3 (cnt/RefCnt[3],cnt/RefCnt_T[3],CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/RefCnt_T[3] = (cnt/RefCnt[0] && cnt/RefCnt[1] && cnt/RefCnt[2]);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt4 (cnt/RefCnt[4],cnt/RefCnt_T[4],CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/RefCnt_T[4] = (cnt/RefCnt[0] && cnt/RefCnt[1] && cnt/RefCnt[3] &&
|
||
|
|
<br/> cnt/RefCnt[2]);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt5 (cnt/RefCnt[5],cnt/RefCnt_T[5],CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/RefCnt_T[5] = (cnt/RefCnt[0] && cnt/RefCnt[1] && cnt/RefCnt[3] &&
|
||
|
|
<br/> cnt/RefCnt[2] && cnt/RefCnt[4]);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt6 (cnt/RefCnt[6],cnt/RefCnt_T[6],CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/RefCnt_T[6] = (cnt/RefCnt[5] && cnt/RefCnt[0] && cnt/RefCnt[1] &&
|
||
|
|
<br/> cnt/RefCnt[3] && cnt/RefCnt[2] && cnt/RefCnt[4]);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/RefCnt7 (cnt/RefCnt[7],cnt/RefCnt_T[7],CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/RefCnt_T[7] = (cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[0] &&
|
||
|
|
<br/> cnt/RefCnt[1] && cnt/RefCnt[3] && cnt/RefCnt[2] && cnt/RefCnt[4]);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_cnt/RefDone (cnt/RefDone,cnt/RefDone_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/RefDone_D = ((!cnt/RefDone && !ram/RefRAS)
|
||
|
|
<br/> || (!cnt/RefCnt[5] && !cnt/RefCnt[6] && !cnt/RefCnt[0] &&
|
||
|
|
<br/> !cnt/RefCnt[7] && !cnt/RefCnt[1] && !cnt/RefCnt[3] && !cnt/RefCnt[2] &&
|
||
|
|
<br/> !cnt/RefCnt[4]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/TimeoutA (cnt/TimeoutA,cnt/TimeoutA_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/TimeoutA_T = ((cnt/TimeoutA && nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!cnt/TimeoutA && !nAS_FSB && !cnt/RefCnt[5] &&
|
||
|
|
<br/> !cnt/RefCnt[6] && !cnt/RefCnt[0] && !cnt/RefCnt[1] && !cnt/RefCnt[3] &&
|
||
|
|
<br/> !cnt/RefCnt[2] && !cnt/RefCnt[4])
|
||
|
|
<br/> || (!cnt/TimeoutA && !cnt/RefCnt[5] && !cnt/RefCnt[6] &&
|
||
|
|
<br/> !cnt/RefCnt[0] && !cnt/RefCnt[1] && !cnt/RefCnt[3] && !cnt/RefCnt[2] &&
|
||
|
|
<br/> !cnt/RefCnt[4] && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/TimeoutB (cnt/TimeoutB,cnt/TimeoutB_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/TimeoutB_T = ((cnt/TimeoutB && nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!cnt/TimeoutB && cnt/TimeoutBPre && !nAS_FSB &&
|
||
|
|
<br/> !cnt/RefCnt[5] && !cnt/RefCnt[6] && !cnt/RefCnt[0] && !cnt/RefCnt[7] &&
|
||
|
|
<br/> !cnt/RefCnt[1] && !cnt/RefCnt[3] && !cnt/RefCnt[2] && !cnt/RefCnt[4])
|
||
|
|
<br/> || (!cnt/TimeoutB && cnt/TimeoutBPre && !cnt/RefCnt[5] &&
|
||
|
|
<br/> !cnt/RefCnt[6] && !cnt/RefCnt[0] && !cnt/RefCnt[7] && !cnt/RefCnt[1] &&
|
||
|
|
<br/> !cnt/RefCnt[3] && !cnt/RefCnt[2] && !cnt/RefCnt[4] && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cnt/TimeoutBPre (cnt/TimeoutBPre,cnt/TimeoutBPre_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign cnt/TimeoutBPre_T = ((cnt/TimeoutBPre && nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!cnt/TimeoutBPre && !nAS_FSB && !cnt/RefCnt[5] &&
|
||
|
|
<br/> !cnt/RefCnt[6] && !cnt/RefCnt[0] && !cnt/RefCnt[7] && !cnt/RefCnt[1] &&
|
||
|
|
<br/> !cnt/RefCnt[3] && !cnt/RefCnt[2] && !cnt/RefCnt[4])
|
||
|
|
<br/> || (!cnt/TimeoutBPre && !cnt/RefCnt[5] && !cnt/RefCnt[6] &&
|
||
|
|
<br/> !cnt/RefCnt[0] && !cnt/RefCnt[7] && !cnt/RefCnt[1] && !cnt/RefCnt[3] &&
|
||
|
|
<br/> !cnt/RefCnt[2] && !cnt/RefCnt[4] && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_cs/nOverlay0 (cs/nOverlay0,cs/nOverlay0_T,CLK_FSB,!nRES,1'b0);
|
||
|
|
<br/> assign cs/nOverlay0_T = ((!A_FSB[23] && A_FSB[22] && !A_FSB[21] && !A_FSB[20] &&
|
||
|
|
<br/> !cs/nOverlay0 && !nAS_FSB)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && !A_FSB[21] && !A_FSB[20] &&
|
||
|
|
<br/> !cs/nOverlay0 && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_cs/nOverlay1 (cs/nOverlay1,cs/nOverlay0,CLK_FSB,1'b0,1'b0,cs/nOverlay1_CE);
|
||
|
|
<br/> assign cs/nOverlay1_CE = (nAS_FSB && !fsb/ASrf);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_fsb/ASrf (fsb/ASrf,!nAS_FSB,!CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_fsb/BERR0r (fsb/BERR0r,fsb/BERR0r_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign fsb/BERR0r_D = ((!cnt/TimeoutB && !fsb/BERR0r)
|
||
|
|
<br/> || (nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && !A_FSB[21] && A_FSB[20] &&
|
||
|
|
<br/> !fsb/BERR0r));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_fsb/BERR1r (fsb/BERR1r,fsb/BERR1r_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign fsb/BERR1r_D = ((!iobs/BERR && !fsb/BERR1r)
|
||
|
|
<br/> || (nAS_FSB && !fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_fsb/Ready0r (fsb/Ready0r,fsb/Ready0r_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign fsb/Ready0r_D = ((nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready0r && !ram/RAMReady)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> !cs/nOverlay1 && !fsb/Ready0r && !ram/RAMReady));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_fsb/Ready1r (fsb/Ready1r,fsb/Ready1r_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign fsb/Ready1r_D = ((cs/nOverlay0.EXP)
|
||
|
|
<br/> || (A_FSB[23] && !fsb/Ready1r && !iobs/IOReady)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !fsb/Ready1r &&
|
||
|
|
<br/> !iobs/IOReady)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !fsb/Ready1r &&
|
||
|
|
<br/> !iobs/IOReady && !SW[1])
|
||
|
|
<br/> || (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
|
||
|
|
<br/> A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready1r && !iobs/IOReady)
|
||
|
|
<br/> || (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
|
||
|
|
<br/> A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready1r && !iobs/IOReady)
|
||
|
|
<br/> || (nAS_FSB && !fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_fsb/Ready2r (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign fsb/Ready2r_D = ((nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_fsb/VPA (fsb/VPA,fsb/VPA_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign fsb/VPA_D = ((EXP15_.EXP)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready0r && fsb/VPA && !ram/RAMReady && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !fsb/Ready1r && fsb/VPA &&
|
||
|
|
<br/> !iobs/IOReady && !SW[1] && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> !cs/nOverlay1 && !fsb/Ready0r && fsb/VPA && !ram/RAMReady &&
|
||
|
|
<br/> !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
|
||
|
|
<br/> A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready1r && fsb/VPA && !iobs/IOReady && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
|
||
|
|
<br/> A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready1r && fsb/VPA && !iobs/IOReady && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (nROMWE_OBUF.EXP)
|
||
|
|
<br/> || (A_FSB[23] && cnt/TimeoutB && fsb/VPA &&
|
||
|
|
<br/> !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (!A_FSB[22] && cnt/TimeoutB && fsb/VPA &&
|
||
|
|
<br/> !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (A_FSB[21] && cnt/TimeoutB && fsb/VPA &&
|
||
|
|
<br/> !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (A_FSB[23] && !fsb/Ready1r && fsb/VPA &&
|
||
|
|
<br/> !iobs/IOReady && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !fsb/Ready1r &&
|
||
|
|
<br/> fsb/VPA && !iobs/IOReady && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (iobs/BERR && fsb/VPA && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (fsb/BERR0r && fsb/VPA && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (fsb/BERR1r && fsb/VPA && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (fsb/VPA && !nBR_IOB && !$OpTx$FX_DC$591)
|
||
|
|
<br/> || (!A_FSB[20] && cnt/TimeoutB && fsb/VPA &&
|
||
|
|
<br/> !$OpTx$FX_DC$591));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/ALE0 (iobm/ALE0,iobm/ALE0_D,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/ALE0_D = ((iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd1)
|
||
|
|
<br/> || (!iobm/IOS_FSM_FFd1 && iobm/IOREQr && !nAoutOE));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/BERRrf (iobm/BERRrf,!nBERR_IOB,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/BERRrr (iobm/BERRrr,!nBERR_IOB,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/BGr0 (iobm/BGr0,!nBG_IOB,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/BGr1 (iobm/BGr1,iobm/BGr0,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/DTACKrf (iobm/DTACKrf,!nDTACK_IOB,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/DTACKrr (iobm/DTACKrr,!nDTACK_IOB,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobm/ES0 (iobm/ES[0],iobm/ES_T[0],CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/ES_T[0] = ((iobm/ES[0] && !iobm/Er && iobm/Er2)
|
||
|
|
<br/> || (!iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
|
||
|
|
<br/> !iobm/ES[3] && !iobm/ES[4] && iobm/Er)
|
||
|
|
<br/> || (!iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
|
||
|
|
<br/> !iobm/ES[3] && !iobm/ES[4] && !iobm/Er2));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/ES1 (iobm/ES[1],iobm/ES_D[1],CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/ES_D[1] = ((iobm/ES[0] && iobm/ES[1])
|
||
|
|
<br/> || (!iobm/ES[0] && !iobm/ES[1])
|
||
|
|
<br/> || (!iobm/Er && iobm/Er2));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/ES2 (iobm/ES[2],iobm/ES_D[2],CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/ES_D[2] = ((!iobm/ES[0] && !iobm/ES[2])
|
||
|
|
<br/> || (!iobm/ES[1] && !iobm/ES[2])
|
||
|
|
<br/> || (!iobm/Er && iobm/Er2)
|
||
|
|
<br/> || (iobm/ES[0] && iobm/ES[1] && iobm/ES[2])
|
||
|
|
<br/> || (!iobm/ES[2] && !iobm/ES[3] && iobm/ES[4]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobm/ES3 (iobm/ES[3],iobm/ES_T[3],CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/ES_T[3] = ((iobm/ES[3] && !iobm/Er && iobm/Er2)
|
||
|
|
<br/> || (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] && iobm/Er)
|
||
|
|
<br/> || (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] && !iobm/Er2));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobm/ES4 (iobm/ES[4],iobm/ES_T[4],CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/ES_T[4] = ((iobm/ES[4] && !iobm/Er && iobm/Er2)
|
||
|
|
<br/> || (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] &&
|
||
|
|
<br/> iobm/ES[3] && iobm/Er)
|
||
|
|
<br/> || (iobm/ES[0] && iobm/ES[1] && iobm/ES[2] &&
|
||
|
|
<br/> iobm/ES[3] && !iobm/Er2)
|
||
|
|
<br/> || (iobm/ES[0] && iobm/ES[1] && !iobm/ES[2] &&
|
||
|
|
<br/> !iobm/ES[3] && iobm/ES[4]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/ETACK (iobm/ETACK,iobm/ETACK_D,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/ETACK_D = (!nVMA_IOB && !iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
|
||
|
|
<br/> !iobm/ES[3] && iobm/ES[4]);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/Er (iobm/Er,E_IOB,!CLK_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/Er2 (iobm/Er2,iobm/Er,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/IOACT (iobm/IOACT,iobm/IOACT_D,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/IOACT_D = ((CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/DTACKrf && iobm/DTACKrr)
|
||
|
|
<br/> || (CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/RESrf && iobm/RESrr)
|
||
|
|
<br/> || (iobm/IOS_FSM_FFd1 && !iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (!iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd2 &&
|
||
|
|
<br/> !iobm/IOREQr)
|
||
|
|
<br/> || (!iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd2 && nAoutOE)
|
||
|
|
<br/> || (CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/ETACK)
|
||
|
|
<br/> || (CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/BERRrf && iobm/BERRrr));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobm/IOBERR (iobm/IOBERR,iobm/IOBERR_T,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/IOBERR_T = ((CLK_IOB && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/RESrf &&
|
||
|
|
<br/> iobm/RESrr)
|
||
|
|
<br/> || (CLK_IOB && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/BERRrf &&
|
||
|
|
<br/> iobm/BERRrr)
|
||
|
|
<br/> || (CLK_IOB && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/DTACKrf &&
|
||
|
|
<br/> iobm/DTACKrr)
|
||
|
|
<br/> || (CLK_IOB && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/RESrf &&
|
||
|
|
<br/> iobm/RESrr)
|
||
|
|
<br/> || (iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> !iobm/IOS_FSM_FFd2 && iobm/IOBERR)
|
||
|
|
<br/> || (CLK_IOB && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/ETACK)
|
||
|
|
<br/> || (CLK_IOB && !nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && !iobm/IOBERR && iobm/ETACK)
|
||
|
|
<br/> || (CLK_IOB && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/BERRrf &&
|
||
|
|
<br/> iobm/BERRrr)
|
||
|
|
<br/> || (CLK_IOB && nBERR_IOB && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2 && iobm/IOBERR && iobm/DTACKrf &&
|
||
|
|
<br/> iobm/DTACKrr));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/IOREQr (iobm/IOREQr,iobs/IOREQ,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/IOS_FSM_FFd1 (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd1_D,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/IOS_FSM_FFd1_D = ((iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1)
|
||
|
|
<br/> || (!iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd2));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobm/IOS_FSM_FFd2 (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_T,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/IOS_FSM_FFd2_T = ((iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> !iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2 && iobm/ETACK)
|
||
|
|
<br/> || (CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2 && iobm/BERRrf && iobm/BERRrr)
|
||
|
|
<br/> || (CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2 && iobm/DTACKrf && iobm/DTACKrr)
|
||
|
|
<br/> || (CLK_IOB && iobm/IOS_FSM_FFd3 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2 && iobm/RESrf && iobm/RESrr));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/IOS_FSM_FFd3 (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign iobm/IOS_FSM_FFd3_D = ((iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> !iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (!CLK_IOB && !iobm/IOS_FSM_FFd1 && !iobm/IOS_FSM_FFd2 &&
|
||
|
|
<br/> iobm/IOREQr && !nAoutOE));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/RESrf (iobm/RESrf,!nRES,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/RESrr (iobm/RESrr,!nRES,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/VPArf (iobm/VPArf,!nVPA_IOB,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobm/VPArr (iobm/VPArr,!nVPA_IOB,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/ALE0 (iobs/ALE0,iobs/ALE0_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/ALE0_D = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobs/BERR (iobs/BERR,iobs/BERR_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/BERR_T = ((iobs/BERR && nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (iobs/Once && iobs/BERR && !iobs/PS_FSM_FFd2 &&
|
||
|
|
<br/> !iobs/IOACTr && !iobm/IOBERR && nADoutLE1)
|
||
|
|
<br/> || (iobs/Once && !iobs/BERR && !nAS_FSB &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/IOACTr && iobm/IOBERR && nADoutLE1)
|
||
|
|
<br/> || (iobs/Once && !iobs/BERR && !iobs/PS_FSM_FFd2 &&
|
||
|
|
<br/> !iobs/IOACTr && iobm/IOBERR && fsb/ASrf && nADoutLE1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/Clear1 (iobs/Clear1,iobs/Clear1_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/Clear1_D = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && !nADoutLE1);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/IOACTr (iobs/IOACTr,iobm/IOACT,CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/IOL0 (iobs/IOL0,iobs/IOL0_D,CLK_FSB,1'b0,1'b0,iobs/IOL0_CE);
|
||
|
|
<br/> assign iobs/IOL0_D = ((!nLDS_FSB && nADoutLE1)
|
||
|
|
<br/> || (iobs/IOL1 && !nADoutLE1));
|
||
|
|
<br/> assign iobs/IOL0_CE = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/IOL1 (iobs/IOL1,!nLDS_FSB,CLK_FSB,1'b0,1'b0,iobs/Load1);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/IOREQ (iobs/IOREQ,iobs/IOREQ_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/IOREQ_D = ((!A_FSB[23] && !A_FSB[22] && !A_FSB[21] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[20] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[19] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[17] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[16] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[18] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && nWE_FSB &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[20] && !iobs/PS_FSM_FFd2 &&
|
||
|
|
<br/> SW[1] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[14] && !A_FSB[13] && !A_FSB[23] && A_FSB[21] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> cs/nOverlay1 && !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (!iobs/PS_FSM_FFd2 && iobs/PS_FSM_FFd1)
|
||
|
|
<br/> || (iobs/PS_FSM_FFd1 && iobs/IOACTr)
|
||
|
|
<br/> || (iobs/Once && !iobs/PS_FSM_FFd2 && nADoutLE1)
|
||
|
|
<br/> || (nAS_FSB && !iobs/PS_FSM_FFd2 && !fsb/ASrf &&
|
||
|
|
<br/> nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1 &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && nADoutLE1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobs/IORW0 (iobs/IORW0,iobs/IORW0_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/IORW0_T = ((A_FSB_19_IBUF$BUF0.EXP)
|
||
|
|
<br/> || (iobs/IORW0 && iobs/IORW1 && !nADoutLE1)
|
||
|
|
<br/> || (!iobs/IORW0 && !iobs/IORW1 && !nADoutLE1)
|
||
|
|
<br/> || (nAS_FSB && !fsb/ASrf && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !A_FSB[21] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !iobs/IORW0 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[19] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[18] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[17] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[16] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[20] && SW[1] && nADoutLE1)
|
||
|
|
<br/> || (!nWE_FSB && !iobs/IORW0 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1 &&
|
||
|
|
<br/> nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[20] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[14] && !A_FSB[13] && !A_FSB[23] && A_FSB[21] &&
|
||
|
|
<br/> nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> cs/nOverlay1 && nADoutLE1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobs/IORW1 (iobs/IORW1,iobs/IORW1_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/IORW1_T = ((iobs/Once)
|
||
|
|
<br/> || (!nADoutLE1)
|
||
|
|
<br/> || (nBERR_FSB_OBUF.EXP)
|
||
|
|
<br/> || (nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !A_FSB[21])
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[20])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[19])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[18])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[17])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[16])
|
||
|
|
<br/> || (nWE_FSB && iobs/IORW1)
|
||
|
|
<br/> || (!nWE_FSB && !iobs/IORW1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !iobs/IORW1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_iobs/IOReady (iobs/IOReady,iobs/IOReady_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/IOReady_T = ((iobs/IOReady && nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (iobs/Once && iobs/IOReady && !iobs/PS_FSM_FFd2 &&
|
||
|
|
<br/> !iobs/IOACTr && iobm/IOBERR && nADoutLE1)
|
||
|
|
<br/> || (iobs/Once && !iobs/IOReady && !nAS_FSB &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/IOACTr && !iobm/IOBERR && nADoutLE1)
|
||
|
|
<br/> || (iobs/Once && !iobs/IOReady && !iobs/PS_FSM_FFd2 &&
|
||
|
|
<br/> !iobs/IOACTr && !iobm/IOBERR && fsb/ASrf && nADoutLE1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/IOU0 (iobs/IOU0,iobs/IOU0_D,CLK_FSB,1'b0,1'b0,iobs/IOU0_CE);
|
||
|
|
<br/> assign iobs/IOU0_D = ((!nUDS_FSB && nADoutLE1)
|
||
|
|
<br/> || (iobs/IOU1 && !nADoutLE1));
|
||
|
|
<br/> assign iobs/IOU0_CE = (iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/IOU1 (iobs/IOU1,!nUDS_FSB,CLK_FSB,1'b0,1'b0,iobs/Load1);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/Load1 (iobs/Load1,iobs/Load1_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/Load1_D = ((iobs/Once)
|
||
|
|
<br/> || (!nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !A_FSB[21])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[20])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[19])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[17])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[16])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[18])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && nWE_FSB)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[20] && SW[1])
|
||
|
|
<br/> || (!A_FSB[14] && !A_FSB[13] && !A_FSB[23] && A_FSB[21])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> cs/nOverlay1)
|
||
|
|
<br/> || (nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/Once (iobs/Once,iobs/Once_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/Once_D = ((A_FSB[23] && !iobs/Once && iobs/PS_FSM_FFd1)
|
||
|
|
<br/> || (!iobs/Once && iobs/PS_FSM_FFd1 && !nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !A_FSB[21] && !iobs/Once)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !iobs/Once &&
|
||
|
|
<br/> !cs/nOverlay1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[20] && !iobs/Once)
|
||
|
|
<br/> || (RA_4_OBUF.EXP)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[19] && !iobs/Once)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[18] && !iobs/Once)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[17] && !iobs/Once)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[16] && !iobs/Once)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && nWE_FSB && !iobs/Once)
|
||
|
|
<br/> || (nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[23] && !iobs/Once && iobs/PS_FSM_FFd2)
|
||
|
|
<br/> || (A_FSB[22] && !iobs/Once && iobs/PS_FSM_FFd2)
|
||
|
|
<br/> || (A_FSB[22] && !iobs/Once && iobs/PS_FSM_FFd1)
|
||
|
|
<br/> || (!iobs/Once && iobs/PS_FSM_FFd2 && !nADoutLE1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/PS_FSM_FFd1 (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/PS_FSM_FFd1_D = ((iobs/PS_FSM_FFd2)
|
||
|
|
<br/> || (iobs/PS_FSM_FFd1 && iobs/IOACTr));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_iobs/PS_FSM_FFd2 (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign iobs/PS_FSM_FFd2_D = ((!A_FSB[23] && !A_FSB[22] && !A_FSB[21] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[20] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[19] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[17] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[16] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && !A_FSB[18] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[21] && nWE_FSB &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[20] && !iobs/PS_FSM_FFd2 &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd1 && SW[1] && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[14] && !A_FSB[13] && !A_FSB[23] && A_FSB[21] &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> cs/nOverlay1 && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1)
|
||
|
|
<br/> || (iobs/PS_FSM_FFd2 && iobs/PS_FSM_FFd1 &&
|
||
|
|
<br/> iobs/IOACTr)
|
||
|
|
<br/> || (!iobs/PS_FSM_FFd2 && iobs/PS_FSM_FFd1 &&
|
||
|
|
<br/> !iobs/IOACTr)
|
||
|
|
<br/> || (iobs/Once && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
|
||
|
|
<br/> nADoutLE1)
|
||
|
|
<br/> || (nAS_FSB && !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 &&
|
||
|
|
<br/> !fsb/ASrf && nADoutLE1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cs/nOverlay1 &&
|
||
|
|
<br/> !iobs/PS_FSM_FFd2 && !iobs/PS_FSM_FFd1 && nADoutLE1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nADoutLE0 = (!iobm/ALE0 && !iobs/ALE0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nADoutLE1 (nADoutLE1,nADoutLE1_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign nADoutLE1_D = ((iobs/Load1)
|
||
|
|
<br/> || (!iobs/Clear1 && !nADoutLE1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nAS_IOB (nAS_IOB_I,nAS_IOB,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign nAS_IOB = ((!iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (iobm/IOS_FSM_FFd1 && !iobm/IOS_FSM_FFd2));
|
||
|
|
<br/> assign nAS_IOB = nAS_IOB_OE ? nAS_IOB_I : 1'bZ;
|
||
|
|
<br/> assign nAS_IOB_OE = !nAoutOE;
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nAoutOE (nAoutOE,nAoutOE_D,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign nAoutOE_D = ((!iobm/BGr0 && !iobm/BGr1)
|
||
|
|
<br/> || (!iobm/BGr1 && nAoutOE)
|
||
|
|
<br/> || (!nAS_IOB && !iobm/BGr0 && !nAoutOE));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nBERR_FSB = ((nAS_FSB)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && !A_FSB[21] && A_FSB[20] &&
|
||
|
|
<br/> !iobs/BERR && !fsb/BERR0r && !fsb/BERR1r)
|
||
|
|
<br/> || (!iobs/BERR && !cnt/TimeoutB && !fsb/BERR0r &&
|
||
|
|
<br/> !fsb/BERR1r));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nBR_IOB (nBR_IOB,1'b0,CLK_FSB,1'b0,1'b0,nBR_IOB_CE);
|
||
|
|
<br/> assign nBR_IOB_CE = (RESr0 && RESr1 && IPL2r0 && RESr2 && !RESDone &&
|
||
|
|
<br/> IPL2r1);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nCAS (nCAS,!ram/RASEL,!CLK_FSB,1'b0,1'b0);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nDTACK_FSB (nDTACK_FSB,nDTACK_FSB_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign nDTACK_FSB_D = ((EXP18_.EXP)
|
||
|
|
<br/> || (A_FSB[14] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
|
||
|
|
<br/> A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready1r && !iobs/IOReady && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[14] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
|
||
|
|
<br/> A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
|
||
|
|
<br/> cs/nOverlay1 && !fsb/Ready1r && !iobs/IOReady && nDTACK_FSB &&
|
||
|
|
<br/> !nADoutLE1)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB)
|
||
|
|
<br/> || (EXP21_.EXP)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && A_FSB[20] && !fsb/Ready1r &&
|
||
|
|
<br/> !iobs/IOReady && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !fsb/Ready1r &&
|
||
|
|
<br/> !iobs/IOReady && nDTACK_FSB && !SW[1])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> !cs/nOverlay1 && !fsb/Ready0r && nDTACK_FSB && !ram/RAMReady)
|
||
|
|
<br/> || (A_FSB[13] && A_FSB[22] && A_FSB[20] && A_FSB[19] &&
|
||
|
|
<br/> A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB && !cs/nOverlay1 &&
|
||
|
|
<br/> !fsb/Ready1r && !iobs/IOReady && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[13] && !A_FSB[22] && A_FSB[21] && A_FSB[20] &&
|
||
|
|
<br/> A_FSB[19] && A_FSB[18] && A_FSB[17] && A_FSB[16] && !nWE_FSB &&
|
||
|
|
<br/> cs/nOverlay1 && !fsb/Ready1r && !iobs/IOReady && nDTACK_FSB &&
|
||
|
|
<br/> !nADoutLE1)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> A_FSB[12] && A_FSB[11] && A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && !cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[9] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB)
|
||
|
|
<br/> || (A_FSB[8] && A_FSB[15] && !A_FSB[14] && A_FSB[13] &&
|
||
|
|
<br/> !A_FSB[12] && !A_FSB[11] && !A_FSB[10] && !A_FSB[23] && !A_FSB[22] &&
|
||
|
|
<br/> A_FSB[21] && A_FSB[20] && A_FSB[19] && A_FSB[18] && A_FSB[17] &&
|
||
|
|
<br/> A_FSB[16] && !nWE_FSB && cs/nOverlay1 && !cnt/TimeoutA &&
|
||
|
|
<br/> !fsb/Ready2r && nDTACK_FSB));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nDinLE (nDinLE,nDinLE_D,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign nDinLE_D = (iobm/IOS_FSM_FFd1 && iobm/IOS_FSM_FFd2);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nDinOE = ((A_FSB[23] && nWE_FSB && !nAS_FSB)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && A_FSB[20] && nWE_FSB &&
|
||
|
|
<br/> !nAS_FSB)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && nWE_FSB && !nAS_FSB &&
|
||
|
|
<br/> !SW[1]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nDoutOE (nDoutOE,nDoutOE_D,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign nDoutOE_D = ((!iobs/IORW0)
|
||
|
|
<br/> || (!iobm/IOS_FSM_FFd3 && !iobm/IOS_FSM_FFd2));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nLDS_IOB (nLDS_IOB_I,nLDS_IOB,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign nLDS_IOB = ((iobs/IOL0 && !iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (iobs/IOL0 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (!iobs/IORW0 && iobs/IOL0 && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> !iobm/IOS_FSM_FFd1));
|
||
|
|
<br/> assign nLDS_IOB = nLDS_IOB_OE ? nLDS_IOB_I : 1'bZ;
|
||
|
|
<br/> assign nLDS_IOB_OE = !nAoutOE;
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nOE = !((nWE_FSB && !nAS_FSB));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nRAMLWE = !((!nWE_FSB && !nLDS_FSB && !ram/RAMDIS2 && !nAS_FSB &&
|
||
|
|
<br/> !ram/RAMDIS1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nRAMUWE = !((!nWE_FSB && !nUDS_FSB && !ram/RAMDIS2 && !nAS_FSB &&
|
||
|
|
<br/> !ram/RAMDIS1));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nRAS = !(((ram/RefRAS)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RAMDIS2 && !nAS_FSB && !ram/RAMDIS1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> !cs/nOverlay1 && !ram/RAMDIS2 && !nAS_FSB && !ram/RAMDIS1)));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nROMCS = !(((A_FSB[23] && !A_FSB[22] && !A_FSB[21] && !A_FSB[20] &&
|
||
|
|
<br/> !SW[1])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && !A_FSB[21] && !A_FSB[20] &&
|
||
|
|
<br/> SW[1])
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !A_FSB[21] && !A_FSB[20] &&
|
||
|
|
<br/> !cs/nOverlay1)));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nROMWE = !((!nWE_FSB && !nAS_FSB));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_nUDS_IOB (nUDS_IOB_I,nUDS_IOB,!CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign nUDS_IOB = ((iobs/IOU0 && !iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (iobs/IOU0 && iobm/IOS_FSM_FFd1 &&
|
||
|
|
<br/> iobm/IOS_FSM_FFd2)
|
||
|
|
<br/> || (!iobs/IORW0 && iobs/IOU0 && iobm/IOS_FSM_FFd3 &&
|
||
|
|
<br/> !iobm/IOS_FSM_FFd1));
|
||
|
|
<br/> assign nUDS_IOB = nUDS_IOB_OE ? nUDS_IOB_I : 1'bZ;
|
||
|
|
<br/> assign nUDS_IOB_OE = !nAoutOE;
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_nVMA_IOB (nVMA_IOB_I,nVMA_IOB_T,CLK2X_IOB,1'b0,1'b0);
|
||
|
|
<br/> assign nVMA_IOB_T = ((!nVMA_IOB && !iobm/ES[0] && !iobm/ES[1] && !iobm/ES[2] &&
|
||
|
|
<br/> !iobm/ES[3] && !iobm/ES[4])
|
||
|
|
<br/> || (nVMA_IOB && iobm/ES[0] && iobm/ES[1] && iobm/ES[2] &&
|
||
|
|
<br/> !iobm/ES[3] && !iobm/ES[4] && iobm/IOACT && iobm/VPArf &&
|
||
|
|
<br/> iobm/VPArr));
|
||
|
|
<br/> assign nVMA_IOB = nVMA_IOB_OE ? nVMA_IOB_I : 1'bZ;
|
||
|
|
<br/> assign nVMA_IOB_OE = !nAoutOE;
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr><tr><td>
|
||
|
|
assign nVPA_FSB = !((fsb/VPA && !nAS_FSB));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/BACTr (ram/BACTr,ram/BACTr_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/BACTr_D = (nAS_FSB && !fsb/ASrf);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_ram/Once (ram/Once,ram/Once_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/Once_T = ((ram/Once && nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !ram/Once &&
|
||
|
|
<br/> !cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !ram/Once &&
|
||
|
|
<br/> !cs/nOverlay1 && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/RAMDIS1 (ram/RAMDIS1,ram/RAMDIS1_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RAMDIS1_D = ((RA_1_OBUF.EXP)
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!A_FSB[22] && !cnt/RefDone && !cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!cnt/RefDone && ram/Once && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] &&
|
||
|
|
<br/> cnt/RefCnt[7])
|
||
|
|
<br/> || (!cnt/RefDone && nAS_FSB && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] &&
|
||
|
|
<br/> !fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[22] && !cnt/RefDone && cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[22] && !cnt/RefDone && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[22] && !cnt/RefDone && !cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && !ram/BACTr)
|
||
|
|
<br/> || (ram/RS_FSM_FFd1 && ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2)
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!cnt/RefDone && ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FTCPE FTCPE_ram/RAMDIS2 (ram/RAMDIS2,ram/RAMDIS2_T,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RAMDIS2_T = ((!A_FSB[23] && A_FSB[22] && A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> ram/Once && !cs/nOverlay1 && !ram/RAMDIS2 && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] &&
|
||
|
|
<br/> cnt/RefCnt[7])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> ram/Once && !cs/nOverlay1 && !ram/RAMDIS2 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] &&
|
||
|
|
<br/> fsb/ASrf)
|
||
|
|
<br/> || (ram/RAMDIS2 && nAS_FSB && !fsb/ASrf)
|
||
|
|
<br/> || (!cnt/RefDone && ram/Once && !ram/RAMDIS2 && !nAS_FSB &&
|
||
|
|
<br/> ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!cnt/RefDone && ram/Once && !ram/RAMDIS2 &&
|
||
|
|
<br/> ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cnt/RefDone && ram/Once &&
|
||
|
|
<br/> cs/nOverlay1 && !ram/RAMDIS2 && !nAS_FSB && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cnt/RefDone && ram/Once &&
|
||
|
|
<br/> cs/nOverlay1 && !ram/RAMDIS2 && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/RAMReady (ram/RAMReady,ram/RAMReady_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RAMReady_D = ((ram/RS_FSM_FFd2)
|
||
|
|
<br/> || (ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[22] && !cnt/RefDone && cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/BACTr)
|
||
|
|
<br/> || (!A_FSB[22] && !cnt/RefDone && !cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[22] && !cnt/RefDone && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[22] && !cnt/RefDone && !cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !ram/Once &&
|
||
|
|
<br/> !cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !ram/Once &&
|
||
|
|
<br/> !cs/nOverlay1 && !ram/RS_FSM_FFd1 && fsb/ASrf)
|
||
|
|
<br/> || (!cnt/RefDone && cnt/RefCnt[5] && cnt/RefCnt[6] &&
|
||
|
|
<br/> cnt/RefCnt[7])
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/BACTr && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/RASEL (ram/RASEL,ram/RASEL_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RASEL_D = ((A_FSB[22] && !cnt/RefDone && cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[22] && !cnt/RefDone && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[22] && !cnt/RefDone && !cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/BACTr)
|
||
|
|
<br/> || (!A_FSB[22] && !cnt/RefDone && !cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && cnt/RefCnt[5] && cnt/RefCnt[6] &&
|
||
|
|
<br/> cnt/RefCnt[7])
|
||
|
|
<br/> || (EXP26_.EXP)
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd2 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && fsb/ASrf)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[22] && !A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!ram/RS_FSM_FFd2 && ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 && !ram/BACTr)
|
||
|
|
<br/> || (A_FSB[23] && !cnt/RefDone && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd2 && !ram/BACTr && fsb/ASrf)
|
||
|
|
<br/> || (!cnt/RefDone && nAS_FSB && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && !fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/RS_FSM_FFd1 (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RS_FSM_FFd1_D = ((!A_FSB[23] && A_FSB[22] && A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> ram/Once && !cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd2 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> ram/Once && !cs/nOverlay1 && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cnt/RefDone && ram/Once &&
|
||
|
|
<br/> cs/nOverlay1 && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && fsb/ASrf)
|
||
|
|
<br/> || (ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2)
|
||
|
|
<br/> || (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!cnt/RefDone && !nAS_FSB && ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!cnt/RefDone && ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cnt/RefDone && ram/Once &&
|
||
|
|
<br/> cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7]));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/RS_FSM_FFd2 (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RS_FSM_FFd2_D = ((!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> !cnt/RefCnt[5] && ram/BACTr)
|
||
|
|
<br/> || (!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> !cnt/RefCnt[6] && ram/BACTr)
|
||
|
|
<br/> || (nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> !cnt/RefCnt[5] && !fsb/ASrf)
|
||
|
|
<br/> || (nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> !cnt/RefCnt[7] && !fsb/ASrf)
|
||
|
|
<br/> || (nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> !cnt/RefCnt[6] && !fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 && !nAS_FSB &&
|
||
|
|
<br/> !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> !cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] &&
|
||
|
|
<br/> !cs/nOverlay1 && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|
||
|
|
<br/> || (ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2)
|
||
|
|
<br/> || (cnt/RefDone && !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!nAS_FSB && ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|
||
|
|
<br/> || (!ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> !cnt/RefCnt[7] && ram/BACTr));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/RS_FSM_FFd3 (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RS_FSM_FFd3_D = ((!cnt/RefDone && !nAS_FSB && ram/RS_FSM_FFd1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd2 && !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] &&
|
||
|
|
<br/> cnt/RefCnt[7])
|
||
|
|
<br/> || (!cnt/RefDone && ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd2 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd3 && cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] &&
|
||
|
|
<br/> fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cnt/RefDone &&
|
||
|
|
<br/> cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !cnt/RefDone &&
|
||
|
|
<br/> cs/nOverlay1 && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> !cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7])
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !cnt/RefDone &&
|
||
|
|
<br/> !cs/nOverlay1 && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 &&
|
||
|
|
<br/> cnt/RefCnt[5] && cnt/RefCnt[6] && cnt/RefCnt[7] && fsb/ASrf)
|
||
|
|
<br/> || (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!A_FSB[23] && !A_FSB[22] && !ram/Once && cs/nOverlay1 &&
|
||
|
|
<br/> !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && fsb/ASrf)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !ram/Once &&
|
||
|
|
<br/> !cs/nOverlay1 && !nAS_FSB && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3)
|
||
|
|
<br/> || (!A_FSB[23] && A_FSB[22] && A_FSB[21] && !ram/Once &&
|
||
|
|
<br/> !cs/nOverlay1 && !ram/RS_FSM_FFd1 && !ram/RS_FSM_FFd3 && fsb/ASrf));
|
||
|
|
</td></tr><tr><td>
|
||
|
|
FDCPE FDCPE_ram/RefRAS (ram/RefRAS,ram/RefRAS_D,CLK_FSB,1'b0,1'b0);
|
||
|
|
<br/> assign ram/RefRAS_D = (!ram/RS_FSM_FFd1 && ram/RS_FSM_FFd2);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
Register Legend:
|
||
|
|
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
|
||
|
|
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
|
||
|
|
<br/> LDCP (Q,D,G,CLR,PRE);
|
||
|
|
</td></tr><tr><td>
|
||
|
|
</td></tr>
|
||
|
|
</table>
|
||
|
|
<form><span class="pgRef"><table width="90%" align="center"><tr>
|
||
|
|
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
||
|
|
<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
|
||
|
|
</tr></table></span></form>
|
||
|
|
</body></html>
|