2021-10-29 10:04:59 +00:00
< html > < head > < link type = 'text/css' href = 'style.css' rel = 'stylesheet' > < / head > < body class = 'pgBgnd' >
< h3 align = 'center' > Equations< / h3 >
< table width = '90%' align = 'center' border = '1' cellpadding = '0' cellspacing = '0' >
< tr > < td >
< / td > < / tr > < tr > < td >
********** Mapped Logic **********
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
2022-02-14 21:38:58 +00:00
$OpTx$FX_DC$602 < = ((NOT TimeoutB)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20)));
2022-01-16 15:56:37 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
2022-02-14 21:38:58 +00:00
$OpTx$FX_DC$606 < = ((A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB)
< br / > OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
< br / > A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
< br / > cs/nOverlay1 AND NOT nWE_FSB AND NOT nADoutLE1)
< br / > OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
< br / > A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
< br / > cs/nOverlay1 AND NOT nWE_FSB AND NOT nADoutLE1)
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20))
< br / > OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,CLK2X_IOB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > ALE0M_D < = ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
< br / > NOT iobm/IOREQr)
< br / > OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
< br / > NOT iobm/IOS_FSM_FFd8));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,CLK_FSB,'0','0');
< br / > ALE0S_D < = (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
< / td > < / tr > < tr > < td >
FTCPE_BERR_IOBS: FTCPE port map (BERR_IOBS,BERR_IOBS_T,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > BERR_IOBS_T < = ((BERR_IOBS AND nAS_FSB AND NOT fsb/ASrf)
< br / > OR (iobs/Once AND BERR_IOBS AND NOT IOBERR AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
< br / > OR (iobs/Once AND NOT BERR_IOBS AND IOBERR AND NOT nAS_FSB AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
< br / > OR (iobs/Once AND NOT BERR_IOBS AND IOBERR AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,CLK2X_IOB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > IOACT_D < = ((NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
< br / > iobm/BERRrf AND iobm/BERRrr)
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
< br / > iobm/DTACKrf AND iobm/DTACKrr)
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd8 AND
< br / > iobm/RESrf AND iobm/RESrr)
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
< br / > iobm/DTACKrf AND iobm/DTACKrr)
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
< br / > iobm/RESrf AND iobm/RESrr)
< br / > OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
< br / > NOT iobm/IOREQr)
< br / > OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
< br / > NOT iobm/IOS_FSM_FFd8)
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
< br / > NOT iobm/IOREQr)
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND iobm/ETACK AND
< br / > NOT iobm/IOS_FSM_FFd8)
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
< br / > NOT iobm/IOS_FSM_FFd6 AND CLK_IOB AND NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr AND
< br / > iobm/BERRrf AND iobm/BERRrr));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,CLK2X_IOB,'0','0');
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< br / > IOBERR_T < = ((nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
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< br / > CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
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< br / > OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
< br / > CLK_IOB AND iobm/RESrf AND iobm/RESrr)
< br / > OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
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< br / > CLK_IOB AND iobm/BERRrf AND iobm/BERRrr)
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< br / > OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
< br / > CLK_IOB AND iobm/DTACKrf AND iobm/DTACKrr)
< br / > OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
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< br / > CLK_IOB AND iobm/RESrf AND iobm/RESrr)
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< br / > OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
< br / > CLK_IOB AND iobm/ETACK)
< br / > OR (NOT nBERR_IOB AND NOT IOBERR AND iobm/IOS_FSM_FFd3 AND
< br / > CLK_IOB AND iobm/ETACK)
< br / > OR (nBERR_IOB AND IOBERR AND iobm/IOS_FSM_FFd3 AND
< br / > CLK_IOB AND iobm/BERRrf AND iobm/BERRrr));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,CLK_FSB,'0','0',IOL0_CE);
< br / > IOL0_D < = ((NOT nLDS_FSB AND nADoutLE1)
< br / > OR (iobs/IOL1 AND NOT nADoutLE1));
< br / > IOL0_CE < = (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
< / td > < / tr > < tr > < td >
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,CLK_FSB,'0','0');
2022-01-16 15:56:37 +00:00
< br / > IOREQ_D < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
< br / > NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1)
< br / > OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr)
< br / > OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/PS_FSM_FFd2 AND
< br / > nADoutLE1)
< br / > OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT fsb/ASrf AND
< br / > nADoutLE1));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FTCPE_IORW0: FTCPE port map (IORW0,IORW0_T,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > IORW0_T < = ((EXP22_.EXP)
< br / > OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
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< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
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< br / > IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
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< br / > IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
< br / > fsb/ASrf AND nADoutLE1)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
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< br / > NOT IORW0 AND nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT iobs/Once AND
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< br / > NOT IORW0 AND nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
< br / > fsb/ASrf AND nADoutLE1)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
< br / > NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
< br / > NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
< br / > OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
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< br / > NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND
2021-10-29 10:04:59 +00:00
< br / > NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
< br / > OR (IORW0 AND NOT iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
< br / > OR (NOT IORW0 AND iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND
< br / > NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
< br / > OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
< br / > NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (A_FSB(23) AND NOT iobs/Once AND IORW0 AND NOT nWE_FSB AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
< br / > OR (A_FSB(23) AND NOT iobs/Once AND NOT IORW0 AND nWE_FSB AND
< br / > NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1));
< / td > < / tr > < tr > < td >
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,CLK_FSB,'0','0',IOU0_CE);
< br / > IOU0_D < = ((NOT nUDS_FSB AND nADoutLE1)
< br / > OR (iobs/IOU1 AND NOT nADoutLE1));
< br / > IOU0_CE < = (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(0) < = ((A_FSB(10) AND NOT ram/RASEL)
< br / > OR (ram/RASEL AND A_FSB(1)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(1) < = ((A_FSB(11) AND NOT ram/RASEL)
< br / > OR (ram/RASEL AND A_FSB(2)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(2) < = ((A_FSB(12) AND NOT ram/RASEL)
< br / > OR (ram/RASEL AND A_FSB(3)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(3) < = ((A_FSB(13) AND NOT ram/RASEL)
< br / > OR (ram/RASEL AND A_FSB(4)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(4) < = ((A_FSB(14) AND NOT ram/RASEL)
< br / > OR (ram/RASEL AND A_FSB(5)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(5) < = ((A_FSB(15) AND NOT ram/RASEL)
< br / > OR (ram/RASEL AND A_FSB(6)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(6) < = ((A_FSB(16) AND NOT ram/RASEL)
< br / > OR (ram/RASEL AND A_FSB(7)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
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RA(7) < = ((A_FSB(8) AND ram/RASEL)
< br / > OR (A_FSB(17) AND NOT ram/RASEL));
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< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(8) < = ((A_FSB(9) AND ram/RASEL)
< br / > OR (A_FSB(18) AND NOT ram/RASEL));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(9) < = ((A_FSB(20) AND ram/RASEL)
< br / > OR (A_FSB(19) AND NOT ram/RASEL));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(10) < = A_FSB(21);
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
RA(11) < = A_FSB(19);
< / td > < / tr > < tr > < td >
FDCPE_RefAck: FDCPE port map (RefAck,RefAck_D,CLK_FSB,'0','0');
< br / > RefAck_D < = (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
< / td > < / tr > < tr > < td >
FTCPE_TimeoutA: FTCPE port map (TimeoutA,TimeoutA_T,CLK_FSB,'0','0');
< br / > TimeoutA_T < = ((TimeoutA AND nAS_FSB AND NOT fsb/ASrf)
< br / > OR (NOT TimeoutA AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
< br / > NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
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< br / > NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4))
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< br / > OR (NOT TimeoutA AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
< br / > NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
2022-01-16 15:56:37 +00:00
< br / > NOT cnt/RefCnt(4) AND fsb/ASrf));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FTCPE_TimeoutB: FTCPE port map (TimeoutB,TimeoutB_T,CLK_FSB,'0','0');
< br / > TimeoutB_T < = ((TimeoutB AND nAS_FSB AND NOT fsb/ASrf)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT nAS_FSB AND
< br / > NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND
< br / > NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
< br / > OR (NOT TimeoutB AND cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND
2021-10-29 10:04:59 +00:00
< br / > NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
< br / > NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt0: FTCPE port map (cnt/RefCnt(0),'1',CLK_FSB,'0','0');
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt1: FTCPE port map (cnt/RefCnt(1),cnt/RefCnt(0),CLK_FSB,'0','0');
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt2: FTCPE port map (cnt/RefCnt(2),cnt/RefCnt_T(2),CLK_FSB,'0','0');
< br / > cnt/RefCnt_T(2) < = (cnt/RefCnt(0) AND cnt/RefCnt(1));
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt3: FTCPE port map (cnt/RefCnt(3),cnt/RefCnt_T(3),CLK_FSB,'0','0');
< br / > cnt/RefCnt_T(3) < = (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2));
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt4: FTCPE port map (cnt/RefCnt(4),cnt/RefCnt_T(4),CLK_FSB,'0','0');
< br / > cnt/RefCnt_T(4) < = (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
< br / > cnt/RefCnt(3));
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt5: FTCPE port map (cnt/RefCnt(5),cnt/RefCnt_T(5),CLK_FSB,'0','0');
< br / > cnt/RefCnt_T(5) < = (cnt/RefCnt(0) AND cnt/RefCnt(1) AND cnt/RefCnt(2) AND
< br / > cnt/RefCnt(3) AND cnt/RefCnt(4));
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt6: FTCPE port map (cnt/RefCnt(6),cnt/RefCnt_T(6),CLK_FSB,'0','0');
< br / > cnt/RefCnt_T(6) < = (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(1) AND
< br / > cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
< / td > < / tr > < tr > < td >
FTCPE_cnt/RefCnt7: FTCPE port map (cnt/RefCnt(7),cnt/RefCnt_T(7),CLK_FSB,'0','0');
< br / > cnt/RefCnt_T(7) < = (cnt/RefCnt(0) AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
< br / > cnt/RefCnt(1) AND cnt/RefCnt(2) AND cnt/RefCnt(3) AND cnt/RefCnt(4));
< / td > < / tr > < tr > < td >
FDCPE_cnt/RefDone: FDCPE port map (cnt/RefDone,cnt/RefDone_D,CLK_FSB,'0','0');
< br / > cnt/RefDone_D < = ((NOT cnt/RefDone AND NOT RefAck)
< br / > OR (NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND
< br / > NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND
< br / > NOT cnt/RefCnt(7)));
< / td > < / tr > < tr > < td >
2022-01-16 15:56:37 +00:00
FTCPE_cnt/TimeoutBPre: FTCPE port map (cnt/TimeoutBPre,cnt/TimeoutBPre_T,CLK_FSB,'0','0');
< br / > cnt/TimeoutBPre_T < = ((cnt/TimeoutBPre AND nAS_FSB AND NOT fsb/ASrf)
< br / > OR (NOT cnt/TimeoutBPre AND NOT nAS_FSB AND NOT cnt/RefCnt(0) AND
< br / > NOT cnt/RefCnt(5) AND NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND
< br / > NOT cnt/RefCnt(3) AND NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7))
< br / > OR (NOT cnt/TimeoutBPre AND NOT cnt/RefCnt(0) AND NOT cnt/RefCnt(5) AND
< br / > NOT cnt/RefCnt(6) AND NOT cnt/RefCnt(1) AND NOT cnt/RefCnt(2) AND NOT cnt/RefCnt(3) AND
< br / > NOT cnt/RefCnt(4) AND NOT cnt/RefCnt(7) AND fsb/ASrf));
< / td > < / tr > < tr > < td >
2021-10-29 10:04:59 +00:00
FTCPE_cs/nOverlay0: FTCPE port map (cs/nOverlay0,cs/nOverlay0_T,CLK_FSB,NOT nRES,'0');
2022-01-16 15:56:37 +00:00
< br / > cs/nOverlay0_T < = ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
2021-10-29 10:04:59 +00:00
< br / > NOT cs/nOverlay0 AND NOT nAS_FSB)
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< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
2021-10-29 10:04:59 +00:00
< br / > NOT cs/nOverlay0 AND fsb/ASrf));
< / td > < / tr > < tr > < td >
FDCPE_cs/nOverlay1: FDCPE port map (cs/nOverlay1,cs/nOverlay0,CLK_FSB,'0','0',cs/nOverlay1_CE);
< br / > cs/nOverlay1_CE < = (nAS_FSB AND NOT fsb/ASrf);
< / td > < / tr > < tr > < td >
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT CLK_FSB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_fsb/BERR0r: FDCPE port map (fsb/BERR0r,fsb/BERR0r_D,CLK_FSB,'0','0');
2022-01-16 15:56:37 +00:00
< br / > fsb/BERR0r_D < = ((NOT TimeoutB AND NOT fsb/BERR0r)
< br / > OR (nAS_FSB AND NOT fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND
2021-10-29 10:04:59 +00:00
< br / > NOT fsb/BERR0r));
< / td > < / tr > < tr > < td >
FDCPE_fsb/BERR1r: FDCPE port map (fsb/BERR1r,fsb/BERR1r_D,CLK_FSB,'0','0');
< br / > fsb/BERR1r_D < = ((NOT BERR_IOBS AND NOT fsb/BERR1r)
< br / > OR (nAS_FSB AND NOT fsb/ASrf));
< / td > < / tr > < tr > < td >
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,CLK_FSB,'0','0');
< br / > fsb/Ready0r_D < = ((nAS_FSB AND NOT fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
< br / > NOT fsb/Ready0r AND NOT ram/RAMReady)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT fsb/Ready0r AND NOT ram/RAMReady));
< / td > < / tr > < tr > < td >
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > fsb/Ready1r_D < = ((A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
< br / > A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
< br / > cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
< br / > NOT nADoutLE1)
< br / > OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
< br / > A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
< br / > cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
< br / > NOT nADoutLE1)
< br / > OR (nAS_FSB AND NOT fsb/ASrf)
2021-10-29 10:04:59 +00:00
< br / > OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
2021-10-29 10:04:59 +00:00
< br / > NOT iobs/IOReady)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
2021-10-29 10:04:59 +00:00
< br / > NOT fsb/Ready1r AND NOT iobs/IOReady)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
2022-02-14 21:38:58 +00:00
< br / > NOT fsb/Ready1r AND NOT iobs/IOReady));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_fsb/Ready2r: FDCPE port map (fsb/Ready2r,fsb/Ready2r_D,CLK_FSB,'0','0');
< br / > fsb/Ready2r_D < = ((nAS_FSB AND NOT fsb/ASrf)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r));
< / td > < / tr > < tr > < td >
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > fsb/VPA_D < = ((EXP18_.EXP)
< br / > OR (BERR_IOBS AND fsb/VPA AND fsb/ASrf)
< br / > OR (fsb/BERR0r AND fsb/VPA AND fsb/ASrf)
< br / > OR (fsb/BERR1r AND fsb/VPA AND fsb/ASrf)
< br / > OR (fsb/VPA AND fsb/ASrf AND
< br / > fsb/VPA__or00001/fsb/VPA__or00001_D2)
< br / > OR (fsb/VPA AND fsb/ASrf AND NOT $OpTx$FX_DC$602)
< br / > OR ($OpTx$FX_DC$602.EXP)
< br / > OR (NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND NOT nAS_FSB AND
< br / > $OpTx$FX_DC$606)
< br / > OR (NOT fsb/Ready1r AND fsb/VPA AND NOT iobs/IOReady AND fsb/ASrf AND
< br / > $OpTx$FX_DC$606)
2022-02-07 05:21:01 +00:00
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
2022-02-14 21:38:58 +00:00
< br / > NOT fsb/Ready0r AND fsb/VPA AND NOT nAS_FSB AND NOT ram/RAMReady)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
< br / > NOT fsb/Ready0r AND fsb/VPA AND fsb/ASrf AND NOT ram/RAMReady)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT fsb/Ready0r AND fsb/VPA AND NOT nAS_FSB AND NOT ram/RAMReady)
< br / > OR (BERR_IOBS AND fsb/VPA AND NOT nAS_FSB)
< br / > OR (fsb/BERR0r AND fsb/VPA AND NOT nAS_FSB)
< br / > OR (fsb/BERR1r AND fsb/VPA AND NOT nAS_FSB)
< br / > OR (fsb/VPA AND NOT nAS_FSB AND
< br / > fsb/VPA__or00001/fsb/VPA__or00001_D2)
< br / > OR (fsb/VPA AND NOT nAS_FSB AND NOT $OpTx$FX_DC$602));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
fsb/VPA__or00001/fsb/VPA__or00001_D2 < = ((A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(9) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r)
< br / > OR (A_FSB(8) AND A_FSB(15) AND NOT A_FSB(14) AND A_FSB(13) AND
< br / > NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),CLK2X_IOB,'0','0');
< br / > iobm/ES_T(0) < = ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
< br / > OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
< br / > NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
< br / > OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
< br / > NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
< / td > < / tr > < tr > < td >
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),CLK2X_IOB,'0','0');
< br / > iobm/ES_D(1) < = ((iobm/ES(0) AND iobm/ES(1))
< br / > OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
< br / > OR (NOT iobm/Er AND iobm/Er2));
< / td > < / tr > < tr > < td >
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),CLK2X_IOB,'0','0');
< br / > iobm/ES_D(2) < = ((NOT iobm/ES(0) AND NOT iobm/ES(2))
< br / > OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
< br / > OR (NOT iobm/Er AND iobm/Er2)
< br / > OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
< br / > OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
< / td > < / tr > < tr > < td >
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),CLK2X_IOB,'0','0');
< br / > iobm/ES_T(3) < = ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
< br / > OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
< br / > OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
< / td > < / tr > < tr > < td >
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),CLK2X_IOB,'0','0');
< br / > iobm/ES_T(4) < = ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
< br / > OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
< br / > iobm/ES(3) AND iobm/Er)
< br / > OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
< br / > iobm/ES(3) AND NOT iobm/Er2)
< br / > OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
< br / > NOT iobm/ES(3) AND iobm/ES(4)));
< / td > < / tr > < tr > < td >
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,CLK2X_IOB,'0','0');
< br / > iobm/ETACK_D < = (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
< br / > NOT iobm/ES(3) AND iobm/ES(4));
< / td > < / tr > < tr > < td >
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E_IOB,NOT CLK_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
2022-02-14 21:38:58 +00:00
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,CLK2X_IOB,'0','0');
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,CLK2X_IOB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > iobm/IOS_FSM_FFd2_D < = ((iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/ETACK)
< br / > OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/BERRrf AND
< br / > iobm/BERRrr)
< br / > OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/DTACKrf AND
< br / > iobm/DTACKrr)
< br / > OR (iobm/IOS_FSM_FFd3 AND CLK_IOB AND iobm/RESrf AND
< br / > iobm/RESrr));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,CLK2X_IOB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > iobm/IOS_FSM_FFd3_D < = ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/ETACK)
2022-02-14 21:38:58 +00:00
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/BERRrf AND
< br / > iobm/BERRrr)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/DTACKrf AND
< br / > iobm/DTACKrr)
2022-02-14 21:38:58 +00:00
< br / > OR (NOT iobm/IOS_FSM_FFd4 AND CLK_IOB AND iobm/RESrf AND
< br / > iobm/RESrr));
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd7,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,CLK2X_IOB,'0','0');
< br / > iobm/IOS_FSM_FFd7_D < = (NOT CLK_IOB AND iobm/IOREQr AND iobm/IOS_FSM_FFd8);
< / td > < / tr > < tr > < td >
FDCPE_iobm/IOS_FSM_FFd8: FDCPE port map (iobm/IOS_FSM_FFd8,iobm/IOS_FSM_FFd8_D,CLK2X_IOB,'0','0');
< br / > iobm/IOS_FSM_FFd8_D < = ((NOT iobm/IOS_FSM_FFd8 AND NOT iobm/IOS_FSM_FFd1)
< br / > OR (NOT CLK_IOB AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES,NOT CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,CLK2X_IOB,'0','0');
< / td > < / tr > < tr > < td >
2022-01-16 15:56:37 +00:00
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,CLK_FSB,'0','0');
< br / > iobs/Clear1_D < = (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1);
< / td > < / tr > < tr > < td >
2021-10-29 10:04:59 +00:00
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,CLK_FSB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,CLK_FSB,'0','0',iobs/Load1);
< / td > < / tr > < tr > < td >
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,CLK_FSB,'0','0');
< br / > iobs/IORW1_T < = ((iobs/Once)
< br / > OR (NOT nADoutLE1)
2022-02-14 21:38:58 +00:00
< br / > OR (nVMA_IOB_OBUF.EXP)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT nWE_FSB AND NOT iobs/IORW1)
< br / > OR (nAS_FSB AND NOT fsb/ASrf)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
2022-02-14 21:38:58 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
2022-01-16 15:56:37 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(20))
< br / > OR (nWE_FSB AND iobs/IORW1)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/IORW1));
< / td > < / tr > < tr > < td >
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,CLK_FSB,'0','0');
< br / > iobs/IOReady_T < = ((iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf)
2022-02-14 21:38:58 +00:00
< br / > OR (iobs/Once AND IOBERR AND iobs/IOReady AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
< br / > OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND NOT nAS_FSB AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND nADoutLE1)
< br / > OR (iobs/Once AND NOT IOBERR AND NOT iobs/IOReady AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND fsb/ASrf AND nADoutLE1));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,CLK_FSB,'0','0',iobs/Load1);
< / td > < / tr > < tr > < td >
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,CLK_FSB,'0','0');
< br / > iobs/Load1_D < = ((iobs/Once)
< br / > OR (NOT nADoutLE1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19))
2021-10-29 10:04:59 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18))
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17))
2022-02-14 21:38:58 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16))
< br / > OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21))
2022-01-16 15:56:37 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > cs/nOverlay1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(20))
2021-10-29 10:04:59 +00:00
< br / > OR (nAS_FSB AND NOT fsb/ASrf)
< br / > OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
< / td > < / tr > < tr > < td >
2022-01-16 15:56:37 +00:00
FDCPE_iobs/Once: FDCPE port map (iobs/Once,iobs/Once_D,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > iobs/Once_D < = ((RA_2_OBUF.EXP)
< br / > OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd1)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT iobs/Once AND iobs/PS_FSM_FFd2 AND NOT nADoutLE1)
< br / > OR (NOT iobs/Once AND iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND NOT iobs/Once)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
< br / > NOT iobs/Once)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND NOT iobs/Once)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND NOT iobs/Once)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND NOT iobs/Once)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND NOT iobs/Once)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT iobs/Once AND nWE_FSB)
< br / > OR (nAS_FSB AND NOT fsb/ASrf)
< br / > OR (A_FSB(23) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/Once)
< br / > OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd2)
< br / > OR (A_FSB(22) AND NOT iobs/Once AND iobs/PS_FSM_FFd1));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,CLK_FSB,'0','0');
< br / > iobs/PS_FSM_FFd1_D < = ((iobs/PS_FSM_FFd2)
< br / > OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
< / td > < / tr > < tr > < td >
2022-01-16 15:56:37 +00:00
FDCPE_iobs/PS_FSM_FFd2: FDCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_D,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > iobs/PS_FSM_FFd2_D < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21) AND
2022-01-16 15:56:37 +00:00
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay1 AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(19) AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND nWE_FSB AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
2022-02-14 21:38:58 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(18) AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(17) AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(21) AND NOT A_FSB(16) AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND A_FSB(21) AND
< br / > NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > cs/nOverlay1 AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
2022-01-16 15:56:37 +00:00
< br / > OR (iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
< br / > iobs/IOACTr)
< br / > OR (NOT iobs/PS_FSM_FFd2 AND iobs/PS_FSM_FFd1 AND
< br / > NOT iobs/IOACTr)
< br / > OR (iobs/Once AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
< br / > nADoutLE1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(20) AND NOT iobs/PS_FSM_FFd2 AND
2022-02-14 21:38:58 +00:00
< br / > NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
< br / > OR (nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
< br / > NOT fsb/ASrf AND nADoutLE1));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nADoutLE0 < = (NOT ALE0M AND NOT ALE0S);
< / td > < / tr > < tr > < td >
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,CLK_FSB,'0','0');
2022-01-16 15:56:37 +00:00
< br / > nADoutLE1_D < = ((iobs/Load1)
< br / > OR (NOT iobs/Clear1 AND NOT nADoutLE1));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB,nAS_IOB_D,NOT CLK2X_IOB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > nAS_IOB_D < = (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7);
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nAoutOE < = '0';
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nBERR_FSB < = ((nAS_FSB)
2022-02-14 21:38:58 +00:00
< br / > OR (NOT BERR_IOBS AND NOT TimeoutB AND NOT fsb/BERR0r AND NOT fsb/BERR1r)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND
2022-02-14 21:38:58 +00:00
< br / > NOT BERR_IOBS AND NOT fsb/BERR0r AND NOT fsb/BERR1r));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/RASEL,NOT CLK_FSB,'0','0');
< / td > < / tr > < tr > < td >
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > nDTACK_FSB_D < = ((EXP21_.EXP)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
< br / > nDTACK_FSB)
2022-02-07 05:21:01 +00:00
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
< br / > NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
2022-02-14 21:38:58 +00:00
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND NOT fsb/Ready1r AND
< br / > NOT iobs/IOReady AND nDTACK_FSB)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(14) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
2021-10-29 10:04:59 +00:00
< br / > NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
2022-02-14 21:38:58 +00:00
< br / > OR ($OpTx$FX_DC$606.EXP)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(13) AND A_FSB(22) AND A_FSB(20) AND A_FSB(19) AND
< br / > A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT cs/nOverlay1 AND NOT nWE_FSB AND
< br / > NOT fsb/Ready1r AND NOT iobs/IOReady AND nDTACK_FSB)
< br / > OR (A_FSB(14) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
< br / > A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
< br / > cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
< br / > nDTACK_FSB AND NOT nADoutLE1)
2022-02-14 21:38:58 +00:00
< br / > OR (A_FSB(13) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
< br / > A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
< br / > cs/nOverlay1 AND NOT nWE_FSB AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
< br / > nDTACK_FSB AND NOT nADoutLE1)
< br / > OR (A_FSB(9) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
< br / > nDTACK_FSB)
< br / > OR (A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND A_FSB(13) AND
< br / > A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT A_FSB(23) AND NOT A_FSB(22) AND
< br / > A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND
< br / > A_FSB(16) AND cs/nOverlay1 AND NOT nWE_FSB AND NOT TimeoutA AND NOT fsb/Ready2r AND
< br / > nDTACK_FSB)
2022-01-16 15:56:37 +00:00
< br / > OR (BERR_IOBS AND nDTACK_FSB)
< br / > OR (fsb/BERR0r AND nDTACK_FSB)
< br / > OR (fsb/BERR1r AND nDTACK_FSB)
< br / > OR (nAS_FSB AND NOT fsb/ASrf)
2022-02-14 21:38:58 +00:00
< br / > OR (nDTACK_FSB AND NOT $OpTx$FX_DC$602));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT CLK2X_IOB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > nDinLE_D < = (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nDinOE < = ((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
2022-01-16 15:56:37 +00:00
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND A_FSB(20) AND nWE_FSB AND
2021-10-29 10:04:59 +00:00
< br / > NOT nAS_FSB));
< / td > < / tr > < tr > < td >
FDCPE_nDoutOE: FDCPE port map (nDoutOE,nDoutOE_D,CLK2X_IOB,'0','0');
< br / > nDoutOE_D < = ((NOT IORW0)
2022-02-14 21:38:58 +00:00
< br / > OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7 AND
2021-10-29 10:04:59 +00:00
< br / > NOT iobm/IOS_FSM_FFd2));
< / td > < / tr > < tr > < td >
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB,nLDS_IOB_D,NOT CLK2X_IOB,'0','0');
< br / > nLDS_IOB_D < = ((NOT IOL0)
2022-02-14 21:38:58 +00:00
< br / > OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5)
< br / > OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nOE < = NOT ((nWE_FSB AND NOT nAS_FSB));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nRAMLWE < = NOT ((NOT nWE_FSB AND NOT nLDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
< br / > NOT ram/RAMDIS1));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nRAMUWE < = NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
< br / > NOT ram/RAMDIS1));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nRAS < = NOT (((RefAck)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
< br / > NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RAMDIS1)));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
2022-02-14 21:38:58 +00:00
nROMCS < = NOT (((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20))
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
< br / > NOT cs/nOverlay1)));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nROMWE < = NOT ((NOT nWE_FSB AND NOT nAS_FSB));
< / td > < / tr > < tr > < td >
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB,nUDS_IOB_D,NOT CLK2X_IOB,'0','0');
< br / > nUDS_IOB_D < = ((NOT IOU0)
2022-02-14 21:38:58 +00:00
< br / > OR (IORW0 AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5)
< br / > OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
< br / > NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT iobm/IOS_FSM_FFd7));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB,nVMA_IOB_T,CLK2X_IOB,'0','0');
< br / > nVMA_IOB_T < = ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
< br / > NOT iobm/ES(3) AND NOT iobm/ES(4))
< br / > OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
< br / > NOT iobm/ES(3) AND NOT iobm/ES(4) AND IOACT AND iobm/VPArf AND iobm/VPArr));
< / td > < / tr > < tr > < td >
< / td > < / tr > < tr > < td >
nVPA_FSB < = NOT ((fsb/VPA AND NOT nAS_FSB));
< / td > < / tr > < tr > < td >
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,CLK_FSB,'0','0');
< br / > ram/BACTr_D < = (nAS_FSB AND NOT fsb/ASrf);
< / td > < / tr > < tr > < td >
FTCPE_ram/Once: FTCPE port map (ram/Once,ram/Once_T,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > ram/Once_T < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
2022-01-16 15:56:37 +00:00
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
2021-10-29 10:04:59 +00:00
< br / > NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
2022-02-14 21:38:58 +00:00
< br / > NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
< br / > OR (ram/Once AND nAS_FSB AND NOT fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_ram/RAMDIS1: FDCPE port map (ram/RAMDIS1,ram/RAMDIS1_D,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > ram/RAMDIS1_D < = ((RA_4_OBUF.EXP)
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
2021-10-29 10:04:59 +00:00
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
< br / > OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
< br / > OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
< br / > OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd1 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND NOT fsb/ASrf)
< br / > OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
< br / > OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
< br / > OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/BACTr AND fsb/ASrf));
< / td > < / tr > < tr > < td >
FTCPE_ram/RAMDIS2: FTCPE port map (ram/RAMDIS2,ram/RAMDIS2_T,CLK_FSB,'0','0');
2022-01-16 15:56:37 +00:00
< br / > ram/RAMDIS2_T < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
< br / > NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
< br / > fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
2021-10-29 10:04:59 +00:00
< br / > NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
< br / > OR (ram/RAMDIS2 AND nAS_FSB AND NOT fsb/ASrf)
< br / > OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND
< br / > ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7))
< br / > OR (ram/Once AND NOT cnt/RefDone AND NOT ram/RAMDIS2 AND
< br / > ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND
< br / > cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND ram/Once AND
< br / > NOT cnt/RefDone AND NOT ram/RAMDIS2 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
2022-01-16 15:56:37 +00:00
< br / > cnt/RefCnt(7)));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FDCPE_ram/RAMReady: FDCPE port map (ram/RAMReady,ram/RAMReady_D,CLK_FSB,'0','0');
< br / > ram/RAMReady_D < = ((NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
< br / > NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
< br / > OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
2022-02-14 21:38:58 +00:00
< br / > OR (cnt/RefCnt(5).EXP)
2021-10-29 10:04:59 +00:00
< br / > OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
< br / > OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1)
< br / > OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/BACTr AND fsb/ASrf)
< br / > OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (NOT A_FSB(21) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd1));
< / td > < / tr > < tr > < td >
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,CLK_FSB,'0','0');
2022-02-14 21:38:58 +00:00
< br / > ram/RASEL_D < = ((A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
2021-10-29 10:04:59 +00:00
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (NOT cnt/RefDone AND nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
< br / > NOT fsb/ASrf)
< br / > OR (NOT cnt/RefDone AND nAS_FSB AND ram/RS_FSM_FFd1 AND
< br / > ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
< br / > NOT fsb/ASrf)
2022-02-14 21:38:58 +00:00
< br / > OR (nDinOE_OBUF.EXP)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND NOT nAS_FSB AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (A_FSB(22) AND NOT A_FSB(21) AND NOT cnt/RefDone AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (A_FSB(22) AND cs/nOverlay1 AND NOT cnt/RefDone AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
< br / > OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT nAS_FSB AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/BACTr AND fsb/ASrf)
< br / > OR (A_FSB(23) AND NOT cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7)));
< / td > < / tr > < tr > < td >
FTCPE_ram/RS_FSM_FFd1: FTCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_T,CLK_FSB,'0','0');
< br / > ram/RS_FSM_FFd1_T < = ((ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
< br / > NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT ram/Once AND
< br / > NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT ram/Once AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd2 AND
2022-01-16 15:56:37 +00:00
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FTCPE_ram/RS_FSM_FFd2: FTCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_T,CLK_FSB,'0','0');
2022-01-16 15:56:37 +00:00
< br / > ram/RS_FSM_FFd2_T < = ((nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
2021-10-29 10:04:59 +00:00
< br / > NOT cnt/RefCnt(5) AND NOT fsb/ASrf)
< br / > OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
< br / > NOT cnt/RefCnt(6) AND NOT fsb/ASrf)
< br / > OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
< br / > NOT cnt/RefCnt(7) AND NOT fsb/ASrf)
2022-01-16 15:56:37 +00:00
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND NOT nAS_FSB AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
< br / > OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay1 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
< br / > OR (NOT A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND
< br / > NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf)
< br / > OR (NOT cnt/RefDone AND nAS_FSB AND ram/RS_FSM_FFd2 AND
< br / > ram/RS_FSM_FFd1 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
< br / > NOT fsb/ASrf)
2021-10-29 10:04:59 +00:00
< br / > OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
< br / > OR (cnt/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
< br / > OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
2022-01-16 15:56:37 +00:00
< br / > NOT cnt/RefCnt(5) AND ram/BACTr)
< br / > OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
< br / > NOT cnt/RefCnt(6) AND ram/BACTr)
< br / > OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/BACTr AND
< br / > NOT cnt/RefCnt(7)));
2021-10-29 10:04:59 +00:00
< / td > < / tr > < tr > < td >
FTCPE_ram/RS_FSM_FFd3: FTCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,CLK_FSB,'0','0');
< br / > ram/RS_FSM_FFd3_T < = ((A_FSB(22) AND NOT A_FSB(21) AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
< br / > OR (A_FSB(22) AND cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
2022-02-07 05:21:01 +00:00
< br / > OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3 AND NOT fsb/ASrf)
2022-02-14 21:38:58 +00:00
< br / > OR (NOT A_FSB(22) AND NOT cs/nOverlay1 AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
2021-10-29 10:04:59 +00:00
< br / > OR (NOT cnt/RefDone AND NOT nAS_FSB AND ram/RS_FSM_FFd2 AND
< br / > ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND
< br / > cnt/RefCnt(7))
< br / > OR (NOT cnt/RefDone AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
< br / > ram/RS_FSM_FFd3 AND cnt/RefCnt(5) AND cnt/RefCnt(6) AND cnt/RefCnt(7) AND
< br / > fsb/ASrf)
< br / > OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3)
< br / > OR (ram/Once AND cnt/RefDone AND NOT ram/RS_FSM_FFd2 AND
< br / > NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
< br / > OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(5))
< br / > OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(6))
< br / > OR (ram/Once AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
< br / > NOT ram/RS_FSM_FFd3 AND NOT cnt/RefCnt(7)));
< / td > < / tr > < tr > < td >
Register Legend:
< br / > FDCPE (Q,D,C,CLR,PRE,CE);
< br / > FTCPE (Q,D,C,CLR,PRE,CE);
< br / > LDCP (Q,D,G,CLR,PRE);
< / td > < / tr > < tr > < td >
< / td > < / tr >
< / table >
< form > < span class = "pgRef" > < table width = "90%" align = "center" > < tr >
< td align = "left" > < input type = "button" onclick = "javascript:parent.leftnav.showTop()" onmouseover = "window.status='goto top of page'; return true;" onmouseout = "window.status=''" value = "back to top" > < / td >
< td align = "right" > < input type = "button" onclick = "window.print()" onmouseover = "window.status='print page'; return true;" onmouseout = "window.status=''" value = "print page" > < / td >
< / tr > < / table > < / span > < / form >
< / body > < / html >
