Warp-SE/cpld/FSB.v

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module FSB(
/* MC68HC000 interface */
input FCLK, input nAS, output reg nDTACK, output reg nVPA,
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/* AS cycle detection */
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output BACT,
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/* Ready inputs */
input ROMCS,
input RAMCS, input RAMReady,
input IOPWCS, input IOPWReady, input IONPReady,
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input QoSReady,
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/* Interrupt acknowledge select */
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input IACS);
/* AS cycle detection */
reg ASrf = 0;
always @(negedge FCLK) begin ASrf <= !nAS; end
assign BACT = !nAS || ASrf; // BACT - bus active
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/* DTACK/VPA control */
wire Ready = (QoSReady && RAMCS && RAMReady && !IOPWCS) ||
(QoSReady && RAMCS && RAMReady && IOPWCS && IOPWReady) ||
(QoSReady && ROMCS) || (IONPReady);
always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
always @(posedge FCLK, posedge nAS) begin
if (nAS) nVPA <= 1;
else nVPA <= !(Ready && BACT && IACS);
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end
endmodule