<tdwidth="60%">Global tristate zero (output enable)</td>
</tr>
<tr>
<tdwidth="20%">GTS1</td>
<tdwidth="60%">Global tristate one (output enable)</td>
</tr>
<tr>
<tdwidth="20%">GTS2</td>
<tdwidth="60%">Global tristate two (output enable)</td>
</tr>
<tr>
<tdwidth="20%">GTS3</td>
<tdwidth="60%">Global tristate three (output enable)</td>
</tr>
<tr>
<tdwidth="20%">I/O</td>
<tdwidth="60%">Input/Output</td>
</tr>
<tr>
<tdwidth="20%">INIT</td>
<tdwidth="60%">Initial state</td>
</tr>
<tr>
<tdwidth="20%">ISP</td>
<tdwidth="60%">The use of the JTAG port to program the chip while it is powered in a system.</td>
</tr>
<tr>
<tdwidth="20%">JTAG</td>
<tdwidth="60%">IEEE Standard 1149 (JTAG) boundary-scan test standard.</td>
</tr>
<tr>
<tdwidth="20%">KPR</td>
<tdwidth="60%">Unused I/O with weak keeper (leave unconnected)</td>
</tr>
<tr>
<tdwidth="20%">NC</td>
<tdwidth="60%">Not Connected, unbonded pin</td>
</tr>
<tr>
<tdwidth="20%">PGND</td>
<tdwidth="60%">Programmable ground pin</td>
</tr>
<tr>
<tdwidth="20%">PROHIBITED</td>
<tdwidth="60%">User reserved pin</td>
</tr>
<tr>
<tdwidth="20%">R</td>
<tdwidth="60%">Reset</td>
</tr>
<tr>
<tdwidth="20%">S</td>
<tdwidth="60%">Set</td>
</tr>
<tr>
<tdwidth="20%">TCK</td>
<tdwidth="60%">One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.</td>
</tr>
<tr>
<tdwidth="20%">TDI</td>
<tdwidth="60%">One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.</td>
</tr>
<tr>
<tdwidth="20%">TDO</td>
<tdwidth="60%">One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.</td>
</tr>
<tr>
<tdwidth="20%">TIE</td>
<tdwidth="60%">Unused I/O floating -- must tie to VCC, GND or other signal</td>
</tr>
<tr>
<tdwidth="20%">TMS</td>
<tdwidth="60%">One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.</td>
</tr>
<tr>
<tdwidth="20%">LVCMOS</td>
<tdwidth="60%">Low Voltage Complementary Metal Oxide Semiconductor 3.3 Volts</td>
</tr>
<tr>
<tdwidth="20%">LVCMOS25</td>
<tdwidth="60%">External I/O supply voltage for LVCMOS25</td>
</tr>
<tr>
<tdwidth="20%">LVCMOS33</td>
<tdwidth="60%">External I/O supply voltage for LVCMOS33</td>
</tr>
<tr>
<tdwidth="20%">LVTTL</td>
<tdwidth="60%">Low Voltage Transistor Transistor Logic 3.3Volts</td>
</tr>
<tr>
<tdwidth="20%">VCCIO</td>
<tdwidth="60%">External power for Inputs/Outputs</td>
</tr>
<tr>
<tdwidth="20%">VCC</td>
<tdwidth="60%">Dedicated Power Pin, Internal supply voltage for the device</td>
</tr>
<tr>
<tdwidth="20%">WPU</td>
<tdwidth="60%">Unused I/O with Internal Weak Pull Up (leave unconnected)</td>
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