2024-09-29 07:29:49 +00:00
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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2024-10-01 04:14:08 +00:00
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Design Name: WarpSE Date: 9-30-2024, 11:58PM
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2024-09-29 07:29:49 +00:00
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Device Used: XC95144XL-10-TQ100
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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2024-10-01 03:36:18 +00:00
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129/144 ( 90%) 410 /720 ( 57%) 260/432 ( 60%) 106/144 ( 74%) 73 /81 ( 90%)
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2024-09-29 07:29:49 +00:00
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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2024-10-01 03:36:18 +00:00
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FB1 12/18 11/54 13/90 11/11*
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FB2 18/18* 30/54 32/90 9/10
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FB3 18/18* 43/54 60/90 10/10*
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FB4 18/18* 36/54 40/90 10/10*
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2024-09-29 07:29:49 +00:00
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FB5 12/18 33/54 81/90 8/10
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2024-10-01 03:36:18 +00:00
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FB6 18/18* 34/54 67/90 10/10*
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FB7 18/18* 30/54 35/90 9/10
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FB8 15/18 43/54 82/90 6/10
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2024-09-29 07:29:49 +00:00
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----- ----- ----- -----
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2024-10-01 03:36:18 +00:00
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129/144 260/432 410/720 73/81
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2024-09-29 07:29:49 +00:00
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'C16M' mapped onto global clock net GCK1.
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Signal 'C8M' mapped onto global clock net GCK2.
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Signal 'FCLK' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 32 32 | I/O : 66 73
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2024-10-01 03:36:18 +00:00
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Output : 37 37 | GCK/IO : 3 3
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2024-09-29 07:29:49 +00:00
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Bidirectional : 1 1 | GTS/IO : 3 4
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2024-10-01 03:36:18 +00:00
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GCK : 3 3 | GSR/IO : 1 1
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2024-09-29 07:29:49 +00:00
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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2024-10-01 03:36:18 +00:00
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Total 73 73
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2024-09-29 07:29:49 +00:00
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** Power Data **
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2024-10-01 03:36:18 +00:00
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There are 129 macrocells in high performance mode (MCHP).
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2024-09-29 07:29:49 +00:00
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'WarpSE.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC
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constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC
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constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<0>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<1>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<2>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<3>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<4>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<5>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'nBG_IOB'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
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2024-10-01 03:36:18 +00:00
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** 38 Outputs **
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2024-09-29 07:29:49 +00:00
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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2024-10-01 03:36:18 +00:00
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RnW_IOB 5 10 FB2_2 99 GSR/I/O O STD FAST RESET
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2024-09-29 07:29:49 +00:00
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nDTACK_FSB 9 17 FB3_9 28 I/O O STD FAST RESET
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nROMWE 1 6 FB3_17 34 I/O O STD FAST
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nAoutOE 2 4 FB4_2 87 I/O O STD FAST SET
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2024-10-01 03:36:18 +00:00
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nDoutOE 2 4 FB4_5 89 I/O O STD FAST
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2024-09-29 07:29:49 +00:00
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nDinOE 3 6 FB4_6 90 I/O O STD FAST
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nRES 1 1 FB4_8 91 I/O I/O STD FAST
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nVPA_FSB 3 8 FB4_11 93 I/O O STD FAST RESET
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nROMOE 2 7 FB5_2 35 I/O O STD FAST
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nCAS 16 18 FB5_5 36 I/O O STD FAST RESET
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nOE 4 6 FB5_6 37 I/O O STD FAST RESET
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RA<4> 2 3 FB5_9 40 I/O O STD FAST
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RA<3> 2 3 FB5_11 41 I/O O STD FAST
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RA<5> 2 3 FB5_12 42 I/O O STD FAST
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RA<2> 2 3 FB5_14 43 I/O O STD FAST
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RA<6> 2 3 FB5_15 46 I/O O STD FAST
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nVMA_IOB 3 8 FB6_2 74 I/O O STD FAST RESET
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nLDS_IOB 6 10 FB6_9 79 I/O O STD FAST RESET
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nUDS_IOB 6 10 FB6_11 80 I/O O STD FAST RESET
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2024-10-01 03:36:18 +00:00
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nAS_IOB 4 8 FB6_12 81 I/O O STD FAST RESET
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2024-09-29 07:29:49 +00:00
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nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
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nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
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nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
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RA<1> 2 3 FB7_2 50 I/O O STD FAST
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RA<7> 2 3 FB7_5 52 I/O O STD FAST
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RA<0> 2 3 FB7_6 53 I/O O STD FAST
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RA<8> 2 3 FB7_8 54 I/O O STD FAST
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RA<10> 2 3 FB7_9 55 I/O O STD FAST
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RA<9> 2 3 FB7_11 56 I/O O STD FAST
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MCKE 1 1 FB7_12 58 I/O O STD FAST RESET
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GA<23> 1 1 FB7_15 60 I/O O STD FAST
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GA<22> 1 1 FB7_17 61 I/O O STD FAST
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RA<11> 2 3 FB8_2 63 I/O O STD FAST
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nRAS 3 7 FB8_5 64 I/O O STD FAST
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nRAMLWE 1 3 FB8_6 65 I/O O STD FAST
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nRAMUWE 1 3 FB8_8 66 I/O O STD FAST
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nBERR_FSB 4 6 FB8_12 70 I/O O STD FAST RESET
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nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET
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2024-10-01 03:36:18 +00:00
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** 91 Buried Nodes **
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2024-09-29 07:29:49 +00:00
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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2024-10-01 03:36:18 +00:00
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ram/RS_FSM_FFd4 1 2 FB1_7 STD RESET
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ram/RASrf 1 1 FB1_8 STD RESET
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ram/DTACKr 1 1 FB1_9 STD RESET
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iobs/IOACTr 1 1 FB1_10 STD RESET
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iobm/VPAr 1 1 FB1_11 STD RESET
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iobm/IOREQr 1 1 FB1_12 STD RESET
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iobm/Er 1 1 FB1_13 STD RESET
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fsb/ASrf 1 1 FB1_14 STD RESET
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cnt/nRESr 1 1 FB1_15 STD RESET
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cnt/nIPL2r 1 1 FB1_16 STD RESET
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cnt/Er<0> 1 1 FB1_17 STD RESET
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ram/RS_FSM_FFd5 2 3 FB1_18 STD RESET
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iobs/IODONEr 1 1 FB2_1 STD RESET
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iobm/IOS_FSM_FFd6 1 4 FB2_3 STD RESET
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iobm/IOS_FSM_FFd5 1 1 FB2_4 STD RESET
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iobm/IOS_FSM_FFd4 1 1 FB2_5 STD RESET
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iobm/IOS_FSM_FFd1 1 1 FB2_6 STD RESET
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iobm/C8Mr 1 1 FB2_7 STD RESET
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cnt/Er<1> 1 1 FB2_8 STD RESET
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cnt/C8Mr<0> 1 1 FB2_9 STD RESET
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ALE0S 1 1 FB2_10 STD RESET
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iobs/TS_FSM_FFd1 2 3 FB2_11 STD RESET
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iobs/IOU1 2 2 FB2_12 STD RESET
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iobs/IOL1 2 2 FB2_13 STD RESET
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iobm/IOS_FSM_FFd2 2 4 FB2_14 STD RESET
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cnt/Timer<0> 2 4 FB2_15 STD RESET
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IOBERR 2 2 FB2_16 STD RESET
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IOU0 3 5 FB2_17 STD RESET
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IOL0 3 5 FB2_18 STD RESET
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nRESout 1 2 FB3_1 STD RESET
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cnt/LTimer<0> 1 3 FB3_2 STD RESET
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2024-09-30 03:15:06 +00:00
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cnt/C8Mr<1> 1 1 FB3_3 STD RESET
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2024-10-01 03:36:18 +00:00
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ram/RS_FSM_FFd6 2 8 FB3_4 STD RESET
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cnt/IS_FSM_FFd2 2 6 FB3_5 STD RESET
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cnt/IS_FSM_FFd1 2 9 FB3_6 STD RESET
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cnt/IOQS<3> 2 8 FB3_7 STD RESET
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BACTr 2 3 FB3_8 STD RESET
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ram/RASEL 3 9 FB3_10 STD RESET
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cnt/IOQS<2> 3 8 FB3_11 STD RESET
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cs/Overlay 4 9 FB3_12 STD RESET
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2024-09-29 07:29:49 +00:00
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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2024-10-01 03:36:18 +00:00
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cnt/IOQS<1> 4 8 FB3_13 STD RESET
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MCKEi 4 7 FB3_14 STD RESET
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2024-09-30 03:15:06 +00:00
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IOQoSEN 4 8 FB3_15 STD RESET
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2024-10-01 03:36:18 +00:00
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cnt/IOQS<0> 5 8 FB3_16 STD RESET
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ram/RS_FSM_FFd7 10 12 FB3_18 STD RESET
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cnt/LookReset 2 4 FB4_1 STD RESET
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cnt/LTimerTC 2 14 FB4_3 STD RESET
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cnt/LTimer<9> 2 12 FB4_4 STD RESET
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cnt/LTimer<8> 2 11 FB4_7 STD RESET
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cnt/LTimer<7> 2 10 FB4_9 STD RESET
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cnt/LTimer<6> 2 9 FB4_10 STD RESET
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cnt/LTimer<5> 2 8 FB4_12 STD RESET
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cnt/LTimer<4> 2 7 FB4_13 STD RESET
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cnt/LTimer<3> 2 6 FB4_14 STD RESET
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cnt/LTimer<2> 2 5 FB4_15 STD RESET
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cnt/LTimer<1> 2 4 FB4_16 STD RESET
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cnt/LTimer<10> 2 13 FB4_17 STD RESET
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cnt/Timer<3> 5 7 FB4_18 STD RESET
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2024-09-29 07:29:49 +00:00
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ram/RASrr 13 14 FB5_8 STD RESET
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RAMReady 11 15 FB5_13 STD RESET
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ram/RS_FSM_FFd8 14 14 FB5_17 STD SET
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ram/RASEN 11 13 FB5_18 STD RESET
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2024-10-01 03:36:18 +00:00
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iobm/IOS_FSM_FFd7 2 5 FB6_1 STD SET
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iobm/IOS_FSM_FFd3 3 5 FB6_3 STD RESET
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iobm/ES<2> 3 5 FB6_4 STD RESET
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2024-09-29 07:29:49 +00:00
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iobm/ES<0> 3 6 FB6_5 STD RESET
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iobm/ES<3> 4 6 FB6_6 STD RESET
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iobm/ES<1> 4 6 FB6_7 STD RESET
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2024-10-01 03:36:18 +00:00
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IODONE 4 8 FB6_8 STD RESET
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ALE0M 4 9 FB6_10 STD RESET
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iobm/IOS0 5 11 FB6_13 STD RESET
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iobm/DoutOE 5 9 FB6_16 STD RESET
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IOACT 7 12 FB6_18 STD RESET
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2024-09-30 03:15:06 +00:00
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ram/RS_FSM_FFd3 1 1 FB7_1 STD RESET
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ram/RS_FSM_FFd2 1 1 FB7_3 STD RESET
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ram/RS_FSM_FFd1 1 1 FB7_4 STD RESET
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2024-10-01 03:36:18 +00:00
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ram/RefDone 2 7 FB7_7 STD RESET
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cnt/TimerTC 2 6 FB7_10 STD RESET
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RefUrg 2 5 FB7_13 STD RESET
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RefReq 2 6 FB7_14 STD RESET
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2024-09-29 07:29:49 +00:00
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|
|
|
|
|
|
|
|
Signal Total Total Loc Pwr Reg Init
|
|
|
|
|
|
Name Pts Inps Mode State
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/Timer<1> 4 5 FB7_16 STD RESET
|
|
|
|
|
|
cnt/Timer<2> 5 6 FB7_18 STD RESET
|
|
|
|
|
|
cnt/IOQoSCSr 15 21 FB8_1 STD RESET
|
|
|
|
|
|
IORW 3 5 FB8_3 STD RESET
|
|
|
|
|
|
iobs/Load1 4 17 FB8_4 STD RESET
|
|
|
|
|
|
iobs/IORW1 4 18 FB8_7 STD RESET
|
|
|
|
|
|
IONPReady 5 16 FB8_9 STD RESET
|
|
|
|
|
|
iobs/TS_FSM_FFd2 12 18 FB8_11 STD RESET
|
|
|
|
|
|
iobs/Sent 12 17 FB8_14 STD RESET
|
|
|
|
|
|
IOREQ 13 18 FB8_16 STD RESET
|
|
|
|
|
|
iobs/Clear1 1 2 FB8_17 STD RESET
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
** 35 Inputs **
|
|
|
|
|
|
|
|
|
|
|
|
Signal Loc Pin Pin Pin
|
|
|
|
|
|
Name No. Type Use
|
|
|
|
|
|
A_FSB<13> FB1_2 11 I/O I
|
|
|
|
|
|
A_FSB<14> FB1_3 12 I/O I
|
|
|
|
|
|
A_FSB<15> FB1_5 13 I/O I
|
|
|
|
|
|
A_FSB<16> FB1_6 14 I/O I
|
|
|
|
|
|
A_FSB<17> FB1_8 15 I/O I
|
|
|
|
|
|
A_FSB<18> FB1_9 16 I/O I
|
|
|
|
|
|
A_FSB<19> FB1_11 17 I/O I
|
|
|
|
|
|
A_FSB<20> FB1_12 18 I/O I
|
|
|
|
|
|
A_FSB<21> FB1_14 19 I/O I
|
|
|
|
|
|
A_FSB<22> FB1_15 20 I/O I
|
|
|
|
|
|
C16M FB1_17 22 GCK/I/O GCK
|
|
|
|
|
|
A_FSB<5> FB2_6 2 GTS/I/O I
|
|
|
|
|
|
A_FSB<6> FB2_8 3 GTS/I/O I
|
|
|
|
|
|
A_FSB<7> FB2_9 4 GTS/I/O I
|
|
|
|
|
|
A_FSB<8> FB2_11 6 I/O I
|
|
|
|
|
|
A_FSB<9> FB2_12 7 I/O I
|
|
|
|
|
|
A_FSB<10> FB2_14 8 I/O I
|
|
|
|
|
|
A_FSB<11> FB2_15 9 I/O I
|
|
|
|
|
|
A_FSB<12> FB2_17 10 I/O I
|
|
|
|
|
|
C8M FB3_2 23 GCK/I/O GCK/I
|
|
|
|
|
|
A_FSB<23> FB3_5 24 I/O I
|
|
|
|
|
|
E FB3_6 25 I/O I
|
|
|
|
|
|
FCLK FB3_8 27 GCK/I/O GCK
|
|
|
|
|
|
nWE_FSB FB3_11 29 I/O I
|
|
|
|
|
|
nLDS_FSB FB3_12 30 I/O I
|
|
|
|
|
|
nAS_FSB FB3_14 32 I/O I
|
|
|
|
|
|
nUDS_FSB FB3_15 33 I/O I
|
|
|
|
|
|
nIPL2 FB4_9 92 I/O I
|
|
|
|
|
|
A_FSB<1> FB4_12 94 I/O I
|
|
|
|
|
|
A_FSB<2> FB4_14 95 I/O I
|
|
|
|
|
|
A_FSB<3> FB4_15 96 I/O I
|
|
|
|
|
|
A_FSB<4> FB4_17 97 I/O I
|
|
|
|
|
|
nBERR_IOB FB6_5 76 I/O I
|
|
|
|
|
|
nVPA_IOB FB6_6 77 I/O I
|
|
|
|
|
|
nDTACK_IOB FB6_8 78 I/O I
|
|
|
|
|
|
|
|
|
|
|
|
Legend:
|
|
|
|
|
|
Pin No. - ~ - User Assigned
|
|
|
|
|
|
************************** Function Block Details ************************
|
|
|
|
|
|
Legend:
|
|
|
|
|
|
Total Pt - Total product terms used by the macrocell signal
|
|
|
|
|
|
Imp Pt - Product terms imported from other macrocells
|
|
|
|
|
|
Exp Pt - Product terms exported to other macrocells
|
|
|
|
|
|
in direction shown
|
|
|
|
|
|
Unused Pt - Unused local product terms remaining in macrocell
|
|
|
|
|
|
Loc - Location where logic was mapped in device
|
|
|
|
|
|
Pin Type/Use - I - Input GCK - Global Clock
|
|
|
|
|
|
O - Output GTS - Global Output Enable
|
|
|
|
|
|
(b) - Buried macrocell GSR - Global Set/Reset
|
|
|
|
|
|
X - Signal used as input to the macrocell logic.
|
|
|
|
|
|
Pin No. - ~ - User Assigned
|
|
|
|
|
|
*********************************** FB1 ***********************************
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Number of function block inputs used/remaining: 11/43
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 11
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 03:36:18 +00:00
|
|
|
|
(unused) 0 0 0 5 FB1_1 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB1_2 11 I/O I
|
|
|
|
|
|
(unused) 0 0 0 5 FB1_3 12 I/O I
|
|
|
|
|
|
(unused) 0 0 0 5 FB1_4 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB1_5 13 I/O I
|
|
|
|
|
|
(unused) 0 0 0 5 FB1_6 14 I/O I
|
|
|
|
|
|
ram/RS_FSM_FFd4 1 0 0 4 FB1_7 (b) (b)
|
|
|
|
|
|
ram/RASrf 1 0 0 4 FB1_8 15 I/O I
|
|
|
|
|
|
ram/DTACKr 1 0 0 4 FB1_9 16 I/O I
|
|
|
|
|
|
iobs/IOACTr 1 0 0 4 FB1_10 (b) (b)
|
|
|
|
|
|
iobm/VPAr 1 0 0 4 FB1_11 17 I/O I
|
|
|
|
|
|
iobm/IOREQr 1 0 0 4 FB1_12 18 I/O I
|
|
|
|
|
|
iobm/Er 1 0 0 4 FB1_13 (b) (b)
|
|
|
|
|
|
fsb/ASrf 1 0 0 4 FB1_14 19 I/O I
|
|
|
|
|
|
cnt/nRESr 1 0 0 4 FB1_15 20 I/O I
|
|
|
|
|
|
cnt/nIPL2r 1 0 0 4 FB1_16 (b) (b)
|
|
|
|
|
|
cnt/Er<0> 1 0 0 4 FB1_17 22 GCK/I/O GCK
|
|
|
|
|
|
ram/RS_FSM_FFd5 2 0 0 3 FB1_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-01 03:36:18 +00:00
|
|
|
|
1: E 5: nAS_FSB 9: ram/DTACKr
|
|
|
|
|
|
2: IOACT 6: nDTACK_FSB 10: ram/RS_FSM_FFd5
|
|
|
|
|
|
3: IOREQ 7: nIPL2 11: ram/RS_FSM_FFd6
|
|
|
|
|
|
4: nRES.PIN 8: nVPA_IOB
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-01 03:36:18 +00:00
|
|
|
|
ram/RS_FSM_FFd4 ........XX.............................. 2
|
|
|
|
|
|
ram/RASrf ..........X............................. 1
|
|
|
|
|
|
ram/DTACKr .....X.................................. 1
|
|
|
|
|
|
iobs/IOACTr .X...................................... 1
|
|
|
|
|
|
iobm/VPAr .......X................................ 1
|
|
|
|
|
|
iobm/IOREQr ..X..................................... 1
|
|
|
|
|
|
iobm/Er X....................................... 1
|
|
|
|
|
|
fsb/ASrf ....X................................... 1
|
|
|
|
|
|
cnt/nRESr ...X.................................... 1
|
|
|
|
|
|
cnt/nIPL2r ......X................................. 1
|
|
|
|
|
|
cnt/Er<0> X....................................... 1
|
|
|
|
|
|
ram/RS_FSM_FFd5 ........XXX............................. 3
|
2024-09-29 07:29:49 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
*********************************** FB2 ***********************************
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Number of function block inputs used/remaining: 30/24
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 30
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobs/IODONEr 1 0 0 4 FB2_1 (b) (b)
|
|
|
|
|
|
RnW_IOB 5 0 0 0 FB2_2 99 GSR/I/O O
|
|
|
|
|
|
iobm/IOS_FSM_FFd6 1 0 0 4 FB2_3 (b) (b)
|
|
|
|
|
|
iobm/IOS_FSM_FFd5 1 0 0 4 FB2_4 (b) (b)
|
|
|
|
|
|
iobm/IOS_FSM_FFd4 1 0 0 4 FB2_5 1 GTS/I/O (b)
|
|
|
|
|
|
iobm/IOS_FSM_FFd1 1 0 0 4 FB2_6 2 GTS/I/O I
|
|
|
|
|
|
iobm/C8Mr 1 0 0 4 FB2_7 (b) (b)
|
|
|
|
|
|
cnt/Er<1> 1 0 0 4 FB2_8 3 GTS/I/O I
|
|
|
|
|
|
cnt/C8Mr<0> 1 0 0 4 FB2_9 4 GTS/I/O I
|
|
|
|
|
|
ALE0S 1 0 0 4 FB2_10 (b) (b)
|
|
|
|
|
|
iobs/TS_FSM_FFd1 2 0 0 3 FB2_11 6 I/O I
|
|
|
|
|
|
iobs/IOU1 2 0 0 3 FB2_12 7 I/O I
|
|
|
|
|
|
iobs/IOL1 2 0 0 3 FB2_13 (b) (b)
|
|
|
|
|
|
iobm/IOS_FSM_FFd2 2 0 0 3 FB2_14 8 I/O I
|
|
|
|
|
|
cnt/Timer<0> 2 0 0 3 FB2_15 9 I/O I
|
|
|
|
|
|
IOBERR 2 0 0 3 FB2_16 (b) (b)
|
|
|
|
|
|
IOU0 3 0 0 2 FB2_17 10 I/O I
|
|
|
|
|
|
IOL0 3 0 0 2 FB2_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-01 03:36:18 +00:00
|
|
|
|
1: C8M 11: iobm/C8Mr 21: iobs/IOU1
|
|
|
|
|
|
2: IOBERR 12: iobm/IOREQr 22: iobs/Load1
|
|
|
|
|
|
3: IODONE 13: iobm/IOS_FSM_FFd2 23: iobs/TS_FSM_FFd1
|
|
|
|
|
|
4: IOL0 14: iobm/IOS_FSM_FFd3 24: iobs/TS_FSM_FFd2
|
|
|
|
|
|
5: IORW 15: iobm/IOS_FSM_FFd4 25: nADoutLE1
|
|
|
|
|
|
6: IOU0 16: iobm/IOS_FSM_FFd5 26: nAS_IOB
|
|
|
|
|
|
7: cnt/Er<0> 17: iobm/IOS_FSM_FFd6 27: nAoutOE
|
|
|
|
|
|
8: cnt/Er<1> 18: iobm/IOS_FSM_FFd7 28: nBERR_IOB
|
|
|
|
|
|
9: cnt/Timer<0> 19: iobs/IOACTr 29: nLDS_FSB
|
|
|
|
|
|
10: cnt/TimerTC 20: iobs/IOL1 30: nUDS_FSB
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobs/IODONEr ..X..................................... 1
|
|
|
|
|
|
RnW_IOB ....X.....XXXXXXXX........X............. 10
|
|
|
|
|
|
iobm/IOS_FSM_FFd6 ..........XX.....X........X............. 4
|
|
|
|
|
|
iobm/IOS_FSM_FFd5 ................X....................... 1
|
|
|
|
|
|
iobm/IOS_FSM_FFd4 ...............X........................ 1
|
|
|
|
|
|
iobm/IOS_FSM_FFd1 ............X........................... 1
|
2024-09-29 07:29:49 +00:00
|
|
|
|
iobm/C8Mr X....................................... 1
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/Er<1> ......X................................. 1
|
|
|
|
|
|
cnt/C8Mr<0> X....................................... 1
|
|
|
|
|
|
ALE0S .......................X................ 1
|
|
|
|
|
|
iobs/TS_FSM_FFd1 ..................X...XX................ 3
|
|
|
|
|
|
iobs/IOU1 .....................X.......X.......... 2
|
|
|
|
|
|
iobs/IOL1 .....................X......X........... 2
|
|
|
|
|
|
iobm/IOS_FSM_FFd2 .XX.......X..X.......................... 4
|
|
|
|
|
|
cnt/Timer<0> ......XXXX.............................. 4
|
|
|
|
|
|
IOBERR .........................X.X............ 2
|
|
|
|
|
|
IOU0 .....X..............X.X.X....X.......... 5
|
|
|
|
|
|
IOL0 ...X...............X..X.X...X........... 5
|
2024-09-29 07:29:49 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
*********************************** FB3 ***********************************
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Number of function block inputs used/remaining: 43/11
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 43
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 03:36:18 +00:00
|
|
|
|
nRESout 1 0 /\1 3 FB3_1 (b) (b)
|
|
|
|
|
|
cnt/LTimer<0> 1 0 0 4 FB3_2 23 GCK/I/O GCK/I
|
2024-09-30 03:15:06 +00:00
|
|
|
|
cnt/C8Mr<1> 1 0 0 4 FB3_3 (b) (b)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
ram/RS_FSM_FFd6 2 0 0 3 FB3_4 (b) (b)
|
|
|
|
|
|
cnt/IS_FSM_FFd2 2 0 0 3 FB3_5 24 I/O I
|
|
|
|
|
|
cnt/IS_FSM_FFd1 2 0 0 3 FB3_6 25 I/O I
|
|
|
|
|
|
cnt/IOQS<3> 2 0 0 3 FB3_7 (b) (b)
|
|
|
|
|
|
BACTr 2 0 \/2 1 FB3_8 27 GCK/I/O GCK
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nDTACK_FSB 9 4<- 0 0 FB3_9 28 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
ram/RASEL 3 0 /\2 0 FB3_10 (b) (b)
|
|
|
|
|
|
cnt/IOQS<2> 3 0 0 2 FB3_11 29 I/O I
|
|
|
|
|
|
cs/Overlay 4 0 0 1 FB3_12 30 I/O I
|
|
|
|
|
|
cnt/IOQS<1> 4 0 0 1 FB3_13 (b) (b)
|
|
|
|
|
|
MCKEi 4 0 0 1 FB3_14 32 I/O I
|
2024-09-30 03:15:06 +00:00
|
|
|
|
IOQoSEN 4 0 0 1 FB3_15 33 I/O I
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/IOQS<0> 5 0 0 0 FB3_16 (b) (b)
|
|
|
|
|
|
nROMWE 1 0 \/4 0 FB3_17 34 I/O O
|
|
|
|
|
|
ram/RS_FSM_FFd7 10 5<- 0 0 FB3_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-01 03:36:18 +00:00
|
|
|
|
1: A_FSB<16> 16: RefUrg 30: cnt/TimerTC
|
|
|
|
|
|
2: A_FSB<17> 17: cnt/C8Mr<0> 31: cnt/nIPL2r
|
|
|
|
|
|
3: A_FSB<18> 18: cnt/C8Mr<1> 32: cnt/nRESr
|
|
|
|
|
|
4: A_FSB<19> 19: cnt/Er<0> 33: cs/Overlay
|
|
|
|
|
|
5: A_FSB<20> 20: cnt/Er<1> 34: fsb/ASrf
|
|
|
|
|
|
6: A_FSB<21> 21: cnt/IOQS<0> 35: iobs/Sent
|
|
|
|
|
|
7: BACTr 22: cnt/IOQS<1> 36: nADoutLE1
|
|
|
|
|
|
8: A_FSB<22> 23: cnt/IOQS<2> 37: nAS_FSB
|
|
|
|
|
|
9: A_FSB<23> 24: cnt/IOQS<3> 38: nWE_FSB
|
|
|
|
|
|
10: IONPReady 25: cnt/IOQoSCSr 39: ram/RASEN
|
|
|
|
|
|
11: IOQoSEN 26: cnt/IS_FSM_FFd1 40: ram/RS_FSM_FFd4
|
|
|
|
|
|
12: MCKE 27: cnt/IS_FSM_FFd2 41: ram/RS_FSM_FFd6
|
|
|
|
|
|
13: nRES.PIN 28: cnt/LTimerTC 42: ram/RS_FSM_FFd8
|
|
|
|
|
|
14: RAMReady 29: cnt/LookReset 43: ram/RefDone
|
|
|
|
|
|
15: RefReq
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
|
|
|
|
nRESout .........................XX....................... 2
|
|
|
|
|
|
cnt/LTimer<0> ..................XX.........X.................... 3
|
|
|
|
|
|
cnt/C8Mr<1> ................X................................. 1
|
|
|
|
|
|
ram/RS_FSM_FFd6 .......XX..X....................XX..X.X..X........ 8
|
|
|
|
|
|
cnt/IS_FSM_FFd2 ..................XX.....XXX.X.................... 6
|
|
|
|
|
|
cnt/IS_FSM_FFd1 ..................XX.....XXXXXXX.................. 9
|
|
|
|
|
|
cnt/IOQS<3> ..................XXXXXXX....X.................... 8
|
|
|
|
|
|
BACTr ...........X.....................X..X............. 3
|
|
|
|
|
|
nDTACK_FSB XXXXXX.XXXXX.X...................XXXXX............ 17
|
|
|
|
|
|
ram/RASEL .......XX..X....................XX..X.X.XX........ 9
|
|
|
|
|
|
cnt/IOQS<2> ..................XXXXXXX....X.................... 8
|
|
|
|
|
|
cs/Overlay ....XX.XX..XX...................XX..X............. 9
|
|
|
|
|
|
cnt/IOQS<1> ..................XXXXXXX....X.................... 8
|
|
|
|
|
|
MCKEi ......X...XX....XX...............X..X............. 7
|
|
|
|
|
|
IOQoSEN ..........XX........XXXX.........X..X............. 8
|
|
|
|
|
|
cnt/IOQS<0> ..................XXXXXXX....X.................... 8
|
|
|
|
|
|
nROMWE ....XX.XX...........................XX............ 6
|
|
|
|
|
|
ram/RS_FSM_FFd7 ......XXX..X..XX.................X..X.XX.XX....... 12
|
|
|
|
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
|
|
|
|
0 0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
*********************************** FB4 ***********************************
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Number of function block inputs used/remaining: 36/18
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 36
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/LookReset 2 0 0 3 FB4_1 (b) (b)
|
|
|
|
|
|
nAoutOE 2 0 0 3 FB4_2 87 I/O O
|
|
|
|
|
|
cnt/LTimerTC 2 0 0 3 FB4_3 (b) (b)
|
|
|
|
|
|
cnt/LTimer<9> 2 0 0 3 FB4_4 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nDoutOE 2 0 0 3 FB4_5 89 I/O O
|
|
|
|
|
|
nDinOE 3 0 0 2 FB4_6 90 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/LTimer<8> 2 0 0 3 FB4_7 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nRES 1 0 0 4 FB4_8 91 I/O I/O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/LTimer<7> 2 0 0 3 FB4_9 92 I/O I
|
|
|
|
|
|
cnt/LTimer<6> 2 0 0 3 FB4_10 (b) (b)
|
|
|
|
|
|
nVPA_FSB 3 0 0 2 FB4_11 93 I/O O
|
|
|
|
|
|
cnt/LTimer<5> 2 0 0 3 FB4_12 94 I/O I
|
|
|
|
|
|
cnt/LTimer<4> 2 0 0 3 FB4_13 (b) (b)
|
|
|
|
|
|
cnt/LTimer<3> 2 0 0 3 FB4_14 95 I/O I
|
|
|
|
|
|
cnt/LTimer<2> 2 0 0 3 FB4_15 96 I/O I
|
|
|
|
|
|
cnt/LTimer<1> 2 0 0 3 FB4_16 (b) (b)
|
|
|
|
|
|
cnt/LTimer<10> 2 0 0 3 FB4_17 97 I/O I
|
|
|
|
|
|
cnt/Timer<3> 5 0 0 0 FB4_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-01 03:36:18 +00:00
|
|
|
|
1: A_FSB<20> 13: cnt/LTimer<1> 25: cnt/Timer<2>
|
|
|
|
|
|
2: A_FSB<21> 14: cnt/LTimer<2> 26: cnt/Timer<3>
|
|
|
|
|
|
3: A_FSB<22> 15: cnt/LTimer<3> 27: cnt/TimerTC
|
|
|
|
|
|
4: A_FSB<23> 16: cnt/LTimer<4> 28: fsb/ASrf
|
|
|
|
|
|
5: IONPReady 17: cnt/LTimer<5> 29: iobm/DoutOE
|
|
|
|
|
|
6: MCKE 18: cnt/LTimer<6> 30: iobm/IOREQr
|
|
|
|
|
|
7: cnt/Er<0> 19: cnt/LTimer<7> 31: iobm/IOS0
|
|
|
|
|
|
8: cnt/Er<1> 20: cnt/LTimer<8> 32: nAS_FSB
|
|
|
|
|
|
9: cnt/IS_FSM_FFd1 21: cnt/LTimer<9> 33: nAoutOE
|
|
|
|
|
|
10: cnt/IS_FSM_FFd2 22: cnt/LookReset 34: nBR_IOB
|
|
|
|
|
|
11: cnt/LTimer<0> 23: cnt/Timer<0> 35: nRESout
|
|
|
|
|
|
12: cnt/LTimer<10> 24: cnt/Timer<1> 36: nWE_FSB
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
|
|
|
|
cnt/LookReset ......XX.............X............X..... 4
|
|
|
|
|
|
nAoutOE ........XX......................XX...... 4
|
|
|
|
|
|
cnt/LTimerTC ......XX..XXXXXXXXXXX.....X............. 14
|
|
|
|
|
|
cnt/LTimer<9> ......XX..X.XXXXXXXX......X............. 12
|
|
|
|
|
|
nDoutOE ............................XXX.X....... 4
|
|
|
|
|
|
nDinOE XXXX...........................X...X.... 6
|
|
|
|
|
|
cnt/LTimer<8> ......XX..X.XXXXXXX.......X............. 11
|
|
|
|
|
|
nRES ..................................X..... 1
|
|
|
|
|
|
cnt/LTimer<7> ......XX..X.XXXXXX........X............. 10
|
|
|
|
|
|
cnt/LTimer<6> ......XX..X.XXXXX.........X............. 9
|
|
|
|
|
|
nVPA_FSB XXXXXX.....................X...X........ 8
|
|
|
|
|
|
cnt/LTimer<5> ......XX..X.XXXX..........X............. 8
|
|
|
|
|
|
cnt/LTimer<4> ......XX..X.XXX...........X............. 7
|
|
|
|
|
|
cnt/LTimer<3> ......XX..X.XX............X............. 6
|
|
|
|
|
|
cnt/LTimer<2> ......XX..X.X.............X............. 5
|
|
|
|
|
|
cnt/LTimer<1> ......XX..X...............X............. 4
|
|
|
|
|
|
cnt/LTimer<10> ......XX..X.XXXXXXXXX.....X............. 13
|
|
|
|
|
|
cnt/Timer<3> ......XX..............XXXXX............. 7
|
|
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
*********************************** FB5 ***********************************
|
|
|
|
|
|
Number of function block inputs used/remaining: 33/21
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 33
|
|
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
|
|
|
|
|
(unused) 0 0 /\5 0 FB5_1 (b) (b)
|
|
|
|
|
|
nROMOE 2 0 /\3 0 FB5_2 35 I/O O
|
|
|
|
|
|
(unused) 0 0 \/5 0 FB5_3 (b) (b)
|
|
|
|
|
|
(unused) 0 0 \/5 0 FB5_4 (b) (b)
|
|
|
|
|
|
nCAS 16 11<- 0 0 FB5_5 36 I/O O
|
|
|
|
|
|
nOE 4 0 /\1 0 FB5_6 37 I/O O
|
|
|
|
|
|
(unused) 0 0 \/5 0 FB5_7 (b) (b)
|
|
|
|
|
|
ram/RASrr 13 8<- 0 0 FB5_8 39 I/O (b)
|
|
|
|
|
|
RA<4> 2 0 /\3 0 FB5_9 40 I/O O
|
|
|
|
|
|
(unused) 0 0 0 5 FB5_10 (b)
|
|
|
|
|
|
RA<3> 2 0 0 3 FB5_11 41 I/O O
|
|
|
|
|
|
RA<5> 2 0 \/3 0 FB5_12 42 I/O O
|
|
|
|
|
|
RAMReady 11 6<- 0 0 FB5_13 (b) (b)
|
|
|
|
|
|
RA<2> 2 0 /\3 0 FB5_14 43 I/O O
|
|
|
|
|
|
RA<6> 2 0 \/2 1 FB5_15 46 I/O O
|
|
|
|
|
|
(unused) 0 0 \/5 0 FB5_16 (b) (b)
|
|
|
|
|
|
ram/RS_FSM_FFd8 14 9<- 0 0 FB5_17 49 I/O (b)
|
|
|
|
|
|
ram/RASEN 11 8<- /\2 0 FB5_18 (b) (b)
|
|
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
|
|
|
|
|
1: A_FSB<11> 12: BACTr 23: ram/RASEL
|
|
|
|
|
|
2: A_FSB<12> 13: A_FSB<22> 24: ram/RASEN
|
|
|
|
|
|
3: A_FSB<13> 14: A_FSB<23> 25: ram/RS_FSM_FFd1
|
|
|
|
|
|
4: A_FSB<16> 15: MCKE 26: ram/RS_FSM_FFd2
|
|
|
|
|
|
5: A_FSB<19> 16: RefReq 27: ram/RS_FSM_FFd3
|
|
|
|
|
|
6: A_FSB<20> 17: RefUrg 28: ram/RS_FSM_FFd4
|
|
|
|
|
|
7: A_FSB<21> 18: cs/Overlay 29: ram/RS_FSM_FFd5
|
|
|
|
|
|
8: A_FSB<3> 19: fsb/ASrf 30: ram/RS_FSM_FFd6
|
|
|
|
|
|
9: A_FSB<4> 20: nAS_FSB 31: ram/RS_FSM_FFd7
|
|
|
|
|
|
10: A_FSB<5> 21: nWE_FSB 32: ram/RS_FSM_FFd8
|
|
|
|
|
|
11: A_FSB<7> 22: ram/DTACKr 33: ram/RefDone
|
|
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
|
|
|
|
nROMOE .....XX.....XX...X.XX................... 7
|
|
|
|
|
|
nCAS ...........XXXXXX.XX.X.XXXXXX.XXX....... 18
|
|
|
|
|
|
nOE ...........X..X...XXXX.................. 6
|
|
|
|
|
|
ram/RASrr ...........XXXXXXXXX...X...X..XXX....... 14
|
|
|
|
|
|
RA<4> X......X..............X................. 3
|
|
|
|
|
|
RA<3> ....XX................X................. 3
|
|
|
|
|
|
RA<5> .X......X.............X................. 3
|
|
|
|
|
|
RAMReady ...........XXXXXX.XX...XX..XXX.XX....... 15
|
|
|
|
|
|
RA<2> ...X......X...........X................. 3
|
|
|
|
|
|
RA<6> ..X......X............X................. 3
|
|
|
|
|
|
ram/RS_FSM_FFd8 ...........XXXXXXXXX...XX..X...XX....... 14
|
|
|
|
|
|
ram/RASEN ...........XXXXXX.XX...XX..X...XX....... 13
|
|
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
*********************************** FB6 ***********************************
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Number of function block inputs used/remaining: 34/20
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 34
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/IOS_FSM_FFd7 2 0 0 3 FB6_1 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/IOS_FSM_FFd3 3 0 0 2 FB6_3 (b) (b)
|
|
|
|
|
|
iobm/ES<2> 3 0 0 2 FB6_4 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
iobm/ES<0> 3 0 0 2 FB6_5 76 I/O I
|
|
|
|
|
|
iobm/ES<3> 4 0 0 1 FB6_6 77 I/O I
|
|
|
|
|
|
iobm/ES<1> 4 0 0 1 FB6_7 (b) (b)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
IODONE 4 0 \/1 0 FB6_8 78 I/O I
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nLDS_IOB 6 1<- 0 0 FB6_9 79 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
ALE0M 4 0 \/1 0 FB6_10 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nUDS_IOB 6 1<- 0 0 FB6_11 80 I/O O
|
|
|
|
|
|
nAS_IOB 4 0 0 1 FB6_12 81 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/IOS0 5 0 0 0 FB6_13 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
|
|
|
|
|
|
nADoutLE0 1 0 0 4 FB6_15 85 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/DoutOE 5 0 0 0 FB6_16 (b) (b)
|
|
|
|
|
|
nDinLE 1 0 \/2 2 FB6_17 86 I/O O
|
|
|
|
|
|
IOACT 7 2<- 0 0 FB6_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-01 03:36:18 +00:00
|
|
|
|
1: ALE0M 13: iobm/ES<0> 24: iobm/IOS_FSM_FFd5
|
|
|
|
|
|
2: ALE0S 14: iobm/ES<1> 25: iobm/IOS_FSM_FFd6
|
|
|
|
|
|
3: E 15: iobm/ES<2> 26: iobm/IOS_FSM_FFd7
|
|
|
|
|
|
4: IOACT 16: iobm/ES<3> 27: iobm/VPAr
|
|
|
|
|
|
5: IOBERR 17: iobm/Er 28: iobs/Clear1
|
|
|
|
|
|
6: IODONE 18: iobm/IOREQr 29: iobs/Load1
|
|
|
|
|
|
7: IOL0 19: iobm/IOS0 30: nADoutLE1
|
|
|
|
|
|
8: IORW 20: iobm/IOS_FSM_FFd1 31: nAS_IOB
|
|
|
|
|
|
9: IOU0 21: iobm/IOS_FSM_FFd2 32: nAoutOE
|
|
|
|
|
|
10: nRES.PIN 22: iobm/IOS_FSM_FFd3 33: nDTACK_IOB
|
|
|
|
|
|
11: iobm/C8Mr 23: iobm/IOS_FSM_FFd4 34: nVMA_IOB
|
|
|
|
|
|
12: iobm/DoutOE
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/IOS_FSM_FFd7 ..........X......X.X.....X.....X........ 5
|
|
|
|
|
|
nVMA_IOB ...X........XXXX..........X....X.X...... 8
|
|
|
|
|
|
iobm/IOS_FSM_FFd3 ....XX....X..........XX................. 5
|
|
|
|
|
|
iobm/ES<2> ..X.........XXX.X....................... 5
|
|
|
|
|
|
iobm/ES<0> ..X.........XXXXX....................... 6
|
|
|
|
|
|
iobm/ES<3> ..X.........XXXXX....................... 6
|
|
|
|
|
|
iobm/ES<1> ..X.........XXXXX....................... 6
|
|
|
|
|
|
IODONE .........X..XXXX..............X.XX...... 8
|
|
|
|
|
|
nLDS_IOB ......XX..X......X...XXXXX.....X........ 10
|
|
|
|
|
|
ALE0M X................X.XXXXXXX.............. 9
|
|
|
|
|
|
nUDS_IOB .......XX.X......X...XXXXX.....X........ 10
|
|
|
|
|
|
nAS_IOB ..........X......X...XXXXX.....X........ 8
|
|
|
|
|
|
iobm/IOS0 ..........X......XXXXXXXXX.....X........ 11
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nADoutLE1 ...........................XXX.......... 3
|
|
|
|
|
|
nADoutLE0 XX...................................... 2
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/DoutOE .......X..XX.....X...XXXXX.............. 9
|
|
|
|
|
|
nDinLE .....................XX................. 2
|
|
|
|
|
|
IOACT ...XXX....X......X.XXXXXXX.............. 12
|
2024-09-29 07:29:49 +00:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
*********************************** FB7 ***********************************
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Number of function block inputs used/remaining: 30/24
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 30
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 03:36:18 +00:00
|
|
|
|
ram/RS_FSM_FFd3 1 0 0 4 FB7_1 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<1> 2 0 0 3 FB7_2 50 I/O O
|
2024-09-30 03:15:06 +00:00
|
|
|
|
ram/RS_FSM_FFd2 1 0 0 4 FB7_3 (b) (b)
|
|
|
|
|
|
ram/RS_FSM_FFd1 1 0 0 4 FB7_4 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<7> 2 0 0 3 FB7_5 52 I/O O
|
|
|
|
|
|
RA<0> 2 0 0 3 FB7_6 53 I/O O
|
2024-09-30 03:15:06 +00:00
|
|
|
|
ram/RefDone 2 0 0 3 FB7_7 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<8> 2 0 0 3 FB7_8 54 I/O O
|
|
|
|
|
|
RA<10> 2 0 0 3 FB7_9 55 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/TimerTC 2 0 0 3 FB7_10 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<9> 2 0 0 3 FB7_11 56 I/O O
|
|
|
|
|
|
MCKE 1 0 0 4 FB7_12 58 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
RefUrg 2 0 0 3 FB7_13 (b) (b)
|
|
|
|
|
|
RefReq 2 0 0 3 FB7_14 59 I/O (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
GA<23> 1 0 0 4 FB7_15 60 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/Timer<1> 4 0 0 1 FB7_16 (b) (b)
|
|
|
|
|
|
GA<22> 1 0 0 4 FB7_17 61 I/O O
|
|
|
|
|
|
cnt/Timer<2> 5 0 0 0 FB7_18 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-01 03:36:18 +00:00
|
|
|
|
1: A_FSB<10> 11: A_FSB<8> 21: cnt/Timer<1>
|
|
|
|
|
|
2: A_FSB<14> 12: A_FSB<9> 22: cnt/Timer<2>
|
|
|
|
|
|
3: A_FSB<15> 13: A_FSB<22> 23: cnt/Timer<3>
|
|
|
|
|
|
4: A_FSB<17> 14: A_FSB<23> 24: cnt/TimerTC
|
|
|
|
|
|
5: A_FSB<18> 15: MCKEi 25: ram/RASEL
|
|
|
|
|
|
6: A_FSB<1> 16: RefReq 26: ram/RS_FSM_FFd1
|
|
|
|
|
|
7: A_FSB<21> 17: RefUrg 27: ram/RS_FSM_FFd2
|
|
|
|
|
|
8: A_FSB<2> 18: cnt/Er<0> 28: ram/RS_FSM_FFd3
|
|
|
|
|
|
9: A_FSB<6> 19: cnt/Er<1> 29: ram/RS_FSM_FFd7
|
|
|
|
|
|
10: A_FSB<7> 20: cnt/Timer<0> 30: ram/RefDone
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Signal 1 2 3 4 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Inputs
|
|
|
|
|
|
ram/RS_FSM_FFd3 ............................X........... 1
|
|
|
|
|
|
RA<1> X......X................X............... 3
|
|
|
|
|
|
ram/RS_FSM_FFd2 ...........................X............ 1
|
|
|
|
|
|
ram/RS_FSM_FFd1 ..........................X............. 1
|
|
|
|
|
|
RA<7> .X......X...............X............... 3
|
|
|
|
|
|
RA<0> .....X.....X............X............... 3
|
|
|
|
|
|
ram/RefDone ...............XX........XXXXX.......... 7
|
|
|
|
|
|
RA<8> ....X.X.................X............... 3
|
|
|
|
|
|
RA<10> ...X.....X..............X............... 3
|
|
|
|
|
|
cnt/TimerTC .................XXXXXX................. 6
|
|
|
|
|
|
RA<9> ..X.......X.............X............... 3
|
|
|
|
|
|
MCKE ..............X......................... 1
|
|
|
|
|
|
RefUrg .................XX.XXX................. 5
|
|
|
|
|
|
RefReq .................XXXXXX................. 6
|
|
|
|
|
|
GA<23> .............X.......................... 1
|
|
|
|
|
|
cnt/Timer<1> .................XXXX..X................ 5
|
|
|
|
|
|
GA<22> ............X........................... 1
|
|
|
|
|
|
cnt/Timer<2> .................XXXXX.X................ 6
|
|
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
*********************************** FB8 ***********************************
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Number of function block inputs used/remaining: 43/11
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 43
|
2024-09-29 07:29:49 +00:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt # Type Use
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/IOQoSCSr 15 10<- 0 0 FB8_1 (b) (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
RA<11> 2 2<- /\5 0 FB8_2 63 I/O O
|
2024-10-01 03:36:18 +00:00
|
|
|
|
IORW 3 0 /\2 0 FB8_3 (b) (b)
|
|
|
|
|
|
iobs/Load1 4 0 0 1 FB8_4 (b) (b)
|
|
|
|
|
|
nRAS 3 0 0 2 FB8_5 64 I/O O
|
|
|
|
|
|
nRAMLWE 1 0 0 4 FB8_6 65 I/O O
|
|
|
|
|
|
iobs/IORW1 4 0 0 1 FB8_7 (b) (b)
|
|
|
|
|
|
nRAMUWE 1 0 \/4 0 FB8_8 66 I/O O
|
|
|
|
|
|
IONPReady 5 4<- \/4 0 FB8_9 67 I/O (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
(unused) 0 0 \/5 0 FB8_10 (b) (b)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobs/TS_FSM_FFd2 12 9<- \/2 0 FB8_11 68 I/O (b)
|
|
|
|
|
|
nBERR_FSB 4 2<- \/3 0 FB8_12 70 I/O O
|
2024-09-29 07:29:49 +00:00
|
|
|
|
(unused) 0 0 \/5 0 FB8_13 (b) (b)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobs/Sent 12 8<- \/1 0 FB8_14 71 I/O (b)
|
|
|
|
|
|
nBR_IOB 2 1<- \/4 0 FB8_15 72 I/O O
|
|
|
|
|
|
IOREQ 13 8<- 0 0 FB8_16 (b) (b)
|
|
|
|
|
|
iobs/Clear1 1 0 /\4 0 FB8_17 73 I/O (b)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
(unused) 0 0 \/5 0 FB8_18 (b) (b)
|
|
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2024-10-01 03:36:18 +00:00
|
|
|
|
1: A_FSB<10> 16: A_FSB<23> 30: iobs/Sent
|
|
|
|
|
|
2: A_FSB<11> 17: IOBERR 31: iobs/TS_FSM_FFd1
|
|
|
|
|
|
3: A_FSB<12> 18: IONPReady 32: iobs/TS_FSM_FFd2
|
|
|
|
|
|
4: A_FSB<13> 19: IOQoSEN 33: nADoutLE1
|
|
|
|
|
|
5: A_FSB<14> 20: MCKE 34: nAS_FSB
|
|
|
|
|
|
6: A_FSB<15> 21: cnt/IS_FSM_FFd1 35: nBERR_FSB
|
|
|
|
|
|
7: A_FSB<16> 22: cnt/IS_FSM_FFd2 36: nBR_IOB
|
|
|
|
|
|
8: A_FSB<17> 23: cnt/nIPL2r 37: nLDS_FSB
|
|
|
|
|
|
9: A_FSB<18> 24: cnt/nRESr 38: nUDS_FSB
|
|
|
|
|
|
10: A_FSB<19> 25: cs/Overlay 39: nWE_FSB
|
|
|
|
|
|
11: A_FSB<20> 26: fsb/ASrf 40: ram/RASEL
|
|
|
|
|
|
12: A_FSB<21> 27: iobs/IOACTr 41: ram/RASEN
|
|
|
|
|
|
13: A_FSB<8> 28: iobs/IODONEr 42: ram/RASrf
|
|
|
|
|
|
14: A_FSB<9> 29: iobs/IORW1 43: ram/RASrr
|
|
|
|
|
|
15: A_FSB<22>
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
Signal 1 2 3 4 5 FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
|
|
|
|
|
cnt/IOQoSCSr XXXXXXXXXXXXXXXX...X...X.X.......X....X........... 21
|
|
|
|
|
|
RA<11> .........XX............................X.......... 3
|
|
|
|
|
|
IORW ............................X.XXX.....X........... 5
|
|
|
|
|
|
iobs/Load1 ......XXXXXX..XX..XX.....X...XXXXX....X........... 17
|
|
|
|
|
|
nRAS ..............XX........X........X......XXX....... 7
|
|
|
|
|
|
nRAMLWE ....................................X.XX.......... 3
|
|
|
|
|
|
iobs/IORW1 ......XXXXXX..XX..XX.....X..XXXXXX....X........... 18
|
|
|
|
|
|
nRAMUWE .....................................XXX.......... 3
|
|
|
|
|
|
IONPReady ......XXXXXX..XX.XXX.....X.X.X...X....X........... 16
|
|
|
|
|
|
iobs/TS_FSM_FFd2 ......XXXXXX..XX..XX.....XX..XXXXX....X........... 18
|
|
|
|
|
|
nBERR_FSB ................X..X.....X...X...XX............... 6
|
|
|
|
|
|
iobs/Sent ......XXXXXX..XX..XX.....X...XXXXX....X........... 17
|
|
|
|
|
|
nBR_IOB ....................XXX............X.............. 4
|
|
|
|
|
|
IOREQ ......XXXXXX..XX..XX.....XX..XXXXX....X........... 18
|
|
|
|
|
|
iobs/Clear1 ..............................XX.................. 2
|
|
|
|
|
|
0----+----1----+----2----+----3----+----4----+----5
|
|
|
|
|
|
0 0 0 0 0
|
2024-09-29 07:29:49 +00:00
|
|
|
|
******************************* Equations ********************************
|
|
|
|
|
|
|
|
|
|
|
|
********** Mapped Logic **********
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
ALE0M_D <= ((iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd6)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
iobm/IOS_FSM_FFd2)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/IOS_FSM_FFd1)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_BACTr: FDCPE port map (BACTr,BACTr_D,FCLK,'0','0');
|
|
|
|
|
|
BACTr_D <= ((NOT nAS_FSB AND MCKE)
|
|
|
|
|
|
OR (MCKE AND fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
GA(22) <= A_FSB(22);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
GA(23) <= A_FSB(23);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
|
|
|
|
|
|
IOACT_D <= ((iobm/IOS_FSM_FFd4)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd5)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd2 AND IOACT AND NOT iobm/IOS_FSM_FFd1)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND iobm/IOREQr)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_IOBERR: FDCPE port map (IOBERR,NOT nBERR_IOB,NOT C8M,nAS_IOB,'0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,NOT C8M,nAS_IOB,'0');
|
|
|
|
|
|
IODONE_D <= ((NOT nRES.PIN)
|
|
|
|
|
|
OR (NOT nDTACK_IOB)
|
|
|
|
|
|
OR (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
iobm/ES(3)));
|
|
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,FCLK,'0','0');
|
|
|
|
|
|
IOL0_D <= ((iobs/TS_FSM_FFd1 AND IOL0)
|
|
|
|
|
|
OR (NOT nLDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/IOL1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0');
|
|
|
|
|
|
IONPReady_D <= ((NOT MCKE)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT iobs/Sent AND NOT IONPReady)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT IONPReady AND NOT iobs/IODONEr)
|
|
|
|
|
|
OR (nAS_FSB AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT IOQoSEN AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
NOT IONPReady AND NOT nWE_FSB));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_IOQoSEN: FDCPE port map (IOQoSEN,IOQoSEN_D,FCLK,'0','0');
|
|
|
|
|
|
IOQoSEN_D <= ((NOT IOQoSEN AND NOT nAS_FSB AND MCKE)
|
|
|
|
|
|
OR (NOT IOQoSEN AND MCKE AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND NOT cnt/IOQS(2) AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
NOT cnt/IOQS(3) AND NOT MCKE)
|
|
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND NOT cnt/IOQS(2) AND
|
|
|
|
|
|
NOT cnt/IOQS(3) AND nAS_FSB AND NOT fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,FCLK,'0','0');
|
|
|
|
|
|
IOREQ_D <= ((A_FSB(23) AND NOT iobs/Sent AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT iobs/Sent AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
fsb/ASrf)
|
|
|
|
|
|
OR (NOT iobs/Sent AND IOQoSEN AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1)
|
|
|
|
|
|
OR (NOT iobs/Sent AND IOQoSEN AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND NOT iobs/TS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND NOT iobs/TS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1)
|
2024-10-01 04:14:08 +00:00
|
|
|
|
OR (iobs/TS_FSM_FFd2 AND NOT iobs/IOACTr)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT nWE_FSB AND NOT nAS_FSB AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
MCKE AND NOT iobs/TS_FSM_FFd1)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT nWE_FSB AND MCKE AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_IORW: FDCPE port map (IORW,IORW_D,FCLK,'0','0',IORW_CE);
|
|
|
|
|
|
IORW_D <= ((nWE_FSB AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/IORW1 AND NOT nADoutLE1));
|
|
|
|
|
|
IORW_CE <= (NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,FCLK,'0','0');
|
|
|
|
|
|
IOU0_D <= ((iobs/TS_FSM_FFd1 AND IOU0)
|
|
|
|
|
|
OR (NOT nUDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/IOU1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_MCKE: FDCPE port map (MCKE,MCKEi,NOT FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_MCKEi: FDCPE port map (MCKEi,MCKEi_D,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
MCKEi_D <= ((IOQoSEN AND NOT MCKE AND NOT BACTr AND cnt/C8Mr(0))
|
|
|
|
|
|
OR (IOQoSEN AND NOT MCKE AND NOT BACTr AND NOT cnt/C8Mr(1))
|
|
|
|
|
|
OR (IOQoSEN AND nAS_FSB AND NOT BACTr AND cnt/C8Mr(0) AND
|
|
|
|
|
|
NOT fsb/ASrf)
|
|
|
|
|
|
OR (IOQoSEN AND nAS_FSB AND NOT BACTr AND NOT cnt/C8Mr(1) AND
|
|
|
|
|
|
NOT fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(0) <= ((ram/RASEL AND A_FSB(1))
|
|
|
|
|
|
OR (NOT ram/RASEL AND A_FSB(9)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(1) <= ((A_FSB(10) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(2)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(2) <= ((A_FSB(16) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(7)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(3) <= ((A_FSB(20) AND ram/RASEL)
|
|
|
|
|
|
OR (A_FSB(19) AND NOT ram/RASEL));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(4) <= ((A_FSB(11) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(3)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(5) <= ((A_FSB(12) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(4)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(6) <= ((A_FSB(13) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(5)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(7) <= ((A_FSB(14) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(6)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(8) <= ((A_FSB(21) AND ram/RASEL)
|
|
|
|
|
|
OR (A_FSB(18) AND NOT ram/RASEL));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(9) <= ((A_FSB(15) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(8)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(10) <= ((A_FSB(17) AND NOT ram/RASEL)
|
|
|
|
|
|
OR (ram/RASEL AND A_FSB(7)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RA(11) <= ((A_FSB(20) AND ram/RASEL)
|
|
|
|
|
|
OR (A_FSB(19) AND NOT ram/RASEL));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_RAMReady: FDCPE port map (RAMReady,RAMReady_D,FCLK,'0','0');
|
|
|
|
|
|
RAMReady_D <= ((RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
MCKE AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6 AND NOT BACTr)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND MCKE AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd6 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
MCKE AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6 AND NOT BACTr)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND MCKE AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd6 AND NOT BACTr AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT MCKE AND NOT ram/RS_FSM_FFd1 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd5 AND NOT ram/RS_FSM_FFd6));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
|
|
|
|
|
|
RefReq_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
|
|
|
|
|
cnt/Timer(3));
|
|
|
|
|
|
RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_RefUrg: FDCPE port map (RefUrg,RefUrg_D,FCLK,'0','0',RefUrg_CE);
|
|
|
|
|
|
RefUrg_D <= (NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3));
|
|
|
|
|
|
RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
FDCPE_RnW_IOB: FDCPE port map (RnW_IOB_I,RnW_IOB,NOT C16M,'0','0');
|
|
|
|
|
|
RnW_IOB <= ((IORW)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd2)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd2)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd2));
|
|
|
|
|
|
RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
RnW_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
2024-09-29 07:29:49 +00:00
|
|
|
|
FDCPE_cnt/C8Mr0: FDCPE port map (cnt/C8Mr(0),C8M,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/C8Mr1: FDCPE port map (cnt/C8Mr(1),cnt/C8Mr(0),FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
|
|
|
|
|
|
|
2024-09-30 03:15:06 +00:00
|
|
|
|
FDCPE_cnt/IOQS0: FDCPE port map (cnt/IOQS(0),cnt/IOQS_D(0),FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/IOQS_D(0) <= ((NOT cnt/IOQS(0) AND NOT cnt/TimerTC AND NOT cnt/IOQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQoSCSr AND cnt/Er(0))
|
|
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQoSCSr AND NOT cnt/Er(1))
|
|
|
|
|
|
OR (cnt/IOQS(0) AND cnt/TimerTC AND NOT cnt/IOQoSCSr AND
|
|
|
|
|
|
NOT cnt/Er(0) AND cnt/Er(1))
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND NOT cnt/IOQS(2) AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
NOT cnt/IOQS(3) AND NOT cnt/IOQoSCSr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/IOQS1: FTCPE port map (cnt/IOQS(1),cnt/IOQS_T(1),FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/IOQS_T(1) <= ((NOT cnt/IOQS(1) AND cnt/IOQoSCSr)
|
|
|
|
|
|
OR (NOT cnt/IOQS(0) AND cnt/IOQS(1) AND cnt/TimerTC AND
|
|
|
|
|
|
NOT cnt/IOQoSCSr AND NOT cnt/Er(0) AND cnt/Er(1))
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND cnt/IOQS(2) AND
|
|
|
|
|
|
cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1))
|
|
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND cnt/IOQS(3) AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/IOQS2: FTCPE port map (cnt/IOQS(2),cnt/IOQS_T(2),FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/IOQS_T(2) <= ((NOT cnt/IOQS(2) AND cnt/IOQoSCSr)
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND cnt/IOQS(2) AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/TimerTC AND NOT cnt/IOQoSCSr AND NOT cnt/Er(0) AND cnt/Er(1))
|
|
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND NOT cnt/IOQS(2) AND
|
|
|
|
|
|
cnt/IOQS(3) AND cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
|
2024-09-30 03:15:06 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/IOQS3: FDCPE port map (cnt/IOQS(3),cnt/IOQS_D(3),FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/IOQS_D(3) <= ((NOT cnt/IOQS(3) AND NOT cnt/IOQoSCSr)
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (NOT cnt/IOQS(0) AND NOT cnt/IOQS(1) AND NOT cnt/IOQS(2) AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/TimerTC AND NOT cnt/IOQoSCSr AND NOT cnt/Er(0) AND cnt/Er(1)));
|
2024-09-30 03:15:06 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/IOQoSCSr: FDCPE port map (cnt/IOQoSCSr,cnt/IOQoSCSr_D,FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
cnt/IOQoSCSr_D <= ((NOT cnt/nRESr)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(23) AND NOT nAS_FSB AND MCKE)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(23) AND MCKE AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
MCKE)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND MCKE AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
fsb/ASrf)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND A_FSB(23) AND NOT nAS_FSB AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
MCKE)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND A_FSB(23) AND MCKE AND
|
|
|
|
|
|
fsb/ASrf)
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nWE_FSB AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
NOT nAS_FSB AND MCKE AND A_FSB(8))
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nWE_FSB AND
|
|
|
|
|
|
MCKE AND A_FSB(8) AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nWE_FSB AND
|
|
|
|
|
|
MCKE AND A_FSB(8) AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nWE_FSB AND
|
|
|
|
|
|
NOT nAS_FSB AND MCKE AND A_FSB(9))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND NOT nWE_FSB AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
MCKE AND A_FSB(9) AND fsb/ASrf)
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nWE_FSB AND
|
|
|
|
|
|
NOT nAS_FSB AND MCKE AND A_FSB(9))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nWE_FSB AND
|
|
|
|
|
|
NOT nAS_FSB AND MCKE AND A_FSB(8))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(22) AND
|
|
|
|
|
|
NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND NOT nWE_FSB AND
|
|
|
|
|
|
MCKE AND A_FSB(9) AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/IS_FSM_FFd1: FTCPE port map (cnt/IS_FSM_FFd1,cnt/IS_FSM_FFd1_T,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
cnt/IS_FSM_FFd1_T <= ((cnt/LookReset AND NOT cnt/IS_FSM_FFd2 AND
|
|
|
|
|
|
cnt/IS_FSM_FFd1 AND NOT cnt/nRESr)
|
|
|
|
|
|
OR (cnt/TimerTC AND cnt/LTimerTC AND cnt/IS_FSM_FFd2 AND
|
|
|
|
|
|
NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/nIPL2r AND cnt/Er(1)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/IS_FSM_FFd2: FTCPE port map (cnt/IS_FSM_FFd2,cnt/IS_FSM_FFd2_T,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
cnt/IS_FSM_FFd2_T <= ((cnt/TimerTC AND cnt/LTimerTC AND cnt/IS_FSM_FFd2 AND
|
|
|
|
|
|
cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1))
|
|
|
|
|
|
OR (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/IS_FSM_FFd2 AND
|
|
|
|
|
|
NOT cnt/IS_FSM_FFd1 AND NOT cnt/Er(0) AND cnt/Er(1)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/LTimer_CE(0));
|
|
|
|
|
|
cnt/LTimer_CE(0) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/LTimer_CE(1));
|
|
|
|
|
|
cnt/LTimer_CE(1) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/LTimer_CE(2));
|
|
|
|
|
|
cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1));
|
|
|
|
|
|
cnt/LTimer_CE(2) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/LTimer_CE(3));
|
|
|
|
|
|
cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2));
|
|
|
|
|
|
cnt/LTimer_CE(3) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/LTimer_CE(4));
|
|
|
|
|
|
cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3));
|
|
|
|
|
|
cnt/LTimer_CE(4) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/LTimer_CE(5));
|
|
|
|
|
|
cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4));
|
|
|
|
|
|
cnt/LTimer_CE(5) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/LTimer_CE(6));
|
|
|
|
|
|
cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5));
|
|
|
|
|
|
cnt/LTimer_CE(6) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/LTimer_CE(7));
|
|
|
|
|
|
cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6));
|
|
|
|
|
|
cnt/LTimer_CE(7) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/LTimer_CE(8));
|
|
|
|
|
|
cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
|
|
|
|
cnt/LTimer(7));
|
|
|
|
|
|
cnt/LTimer_CE(8) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/LTimer_CE(9));
|
|
|
|
|
|
cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
|
|
|
|
cnt/LTimer(7) AND cnt/LTimer(8));
|
|
|
|
|
|
cnt/LTimer_CE(9) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/LTimer_CE(10));
|
|
|
|
|
|
cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
|
|
|
|
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
|
|
|
|
|
cnt/LTimer_CE(10) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/LTimerTC: FDCPE port map (cnt/LTimerTC,cnt/LTimerTC_D,FCLK,'0','0',cnt/LTimerTC_CE);
|
2024-09-30 03:15:06 +00:00
|
|
|
|
cnt/LTimerTC_D <= (NOT cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
|
|
|
|
|
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
|
|
|
|
|
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND cnt/LTimer(10));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
cnt/LTimerTC_CE <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
2024-09-30 03:15:06 +00:00
|
|
|
|
FDCPE_cnt/LookReset: FDCPE port map (cnt/LookReset,cnt/LookReset_D,FCLK,'0','0');
|
|
|
|
|
|
cnt/LookReset_D <= ((cnt/LookReset AND nRESout)
|
|
|
|
|
|
OR (nRESout AND NOT cnt/Er(0) AND cnt/Er(1)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
|
|
|
|
|
|
cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/TimerTC AND NOT cnt/Er(0) AND
|
|
|
|
|
|
cnt/Er(1));
|
|
|
|
|
|
cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/Timer1: FDCPE port map (cnt/Timer(1),cnt/Timer_D(1),FCLK,'0','0',cnt/Timer_CE(1));
|
|
|
|
|
|
cnt/Timer_D(1) <= ((cnt/Timer(0) AND cnt/Timer(1))
|
|
|
|
|
|
OR (NOT cnt/Timer(0) AND NOT cnt/Timer(1))
|
|
|
|
|
|
OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
|
|
|
|
|
|
cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/Timer2: FDCPE port map (cnt/Timer(2),cnt/Timer_D(2),FCLK,'0','0',cnt/Timer_CE(2));
|
|
|
|
|
|
cnt/Timer_D(2) <= ((NOT cnt/Timer(0) AND NOT cnt/Timer(2))
|
|
|
|
|
|
OR (NOT cnt/Timer(1) AND NOT cnt/Timer(2))
|
|
|
|
|
|
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
|
|
|
|
|
|
OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
|
|
|
|
|
|
cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cnt/Timer3: FTCPE port map (cnt/Timer(3),cnt/Timer_T(3),FCLK,'0','0',cnt/Timer_CE(3));
|
|
|
|
|
|
cnt/Timer_T(3) <= ((cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
|
|
|
|
|
|
NOT cnt/TimerTC)
|
|
|
|
|
|
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
|
|
|
|
|
|
cnt/Er(0))
|
|
|
|
|
|
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
|
|
|
|
|
|
NOT cnt/Er(1))
|
|
|
|
|
|
OR (cnt/Timer(3) AND cnt/TimerTC AND NOT cnt/Er(0) AND
|
|
|
|
|
|
cnt/Er(1)));
|
|
|
|
|
|
cnt/Timer_CE(3) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/TimerTC: FDCPE port map (cnt/TimerTC,cnt/TimerTC_D,FCLK,'0','0',cnt/TimerTC_CE);
|
|
|
|
|
|
cnt/TimerTC_D <= (cnt/Timer(0) AND NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
|
|
|
|
|
cnt/Timer(3));
|
|
|
|
|
|
cnt/TimerTC_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/nIPL2r: FDCPE port map (cnt/nIPL2r,nIPL2,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_cnt/nRESr: FDCPE port map (cnt/nRESr,nRES.PIN,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cs/Overlay: FTCPE port map (cs/Overlay,cs/Overlay_T,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
cs/Overlay_T <= ((NOT nRES.PIN AND NOT cs/Overlay AND NOT MCKE)
|
|
|
|
|
|
OR (NOT nRES.PIN AND NOT cs/Overlay AND nAS_FSB AND NOT fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
|
|
|
|
|
cs/Overlay AND NOT nAS_FSB AND MCKE)
|
|
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
2024-09-30 03:15:06 +00:00
|
|
|
|
cs/Overlay AND MCKE AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0');
|
|
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
FDCPE_iobm/DoutOE: FDCPE port map (iobm/DoutOE,iobm/DoutOE_D,C16M,'0','0');
|
|
|
|
|
|
iobm/DoutOE_D <= ((iobm/IOS_FSM_FFd3 AND iobm/DoutOE)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd4 AND iobm/DoutOE)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd5 AND iobm/DoutOE)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd6 AND iobm/DoutOE)
|
|
|
|
|
|
OR (NOT IORW AND iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND
|
|
|
|
|
|
iobm/IOREQr));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0');
|
|
|
|
|
|
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT E AND iobm/Er)
|
|
|
|
|
|
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3) AND E)
|
|
|
|
|
|
OR (NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3) AND NOT iobm/Er));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0');
|
|
|
|
|
|
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
|
|
|
|
|
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
|
|
|
|
|
OR (NOT E AND iobm/Er)
|
|
|
|
|
|
OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3)));
|
|
|
|
|
|
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FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0');
|
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|
|
iobm/ES_T(2) <= ((iobm/ES(0) AND iobm/ES(1) AND E)
|
|
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|
|
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er)
|
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|
OR (iobm/ES(2) AND NOT E AND iobm/Er));
|
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|
|
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0');
|
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|
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|
|
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT E AND iobm/Er)
|
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|
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|
|
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND E)
|
|
|
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|
|
OR (iobm/ES(0) AND iobm/ES(2) AND iobm/ES(1) AND NOT iobm/Er)
|
|
|
|
|
|
OR (iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
iobm/ES(3)));
|
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|
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
|
|
|
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|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,C16M,'0','0');
|
2024-09-29 07:29:49 +00:00
|
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|
|
|
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FDCPE_iobm/IOS0: FDCPE port map (iobm/IOS0,iobm/IOS0_D,C16M,'0','0');
|
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|
|
|
iobm/IOS0_D <= ((iobm/IOS_FSM_FFd1)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND iobm/C8Mr)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND NOT iobm/IOREQr)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (iobm/IOS_FSM_FFd7 AND nAoutOE)
|
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|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
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|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd2 AND iobm/IOS0));
|
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|
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0');
|
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|
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0');
|
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|
|
|
|
iobm/IOS_FSM_FFd2_D <= ((IOBERR AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)
|
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|
|
OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr));
|
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|
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|
|
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
|
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|
|
|
|
iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd4)
|
|
|
|
|
|
OR (iobm/IOS_FSM_FFd3 AND iobm/C8Mr)
|
|
|
|
|
|
OR (NOT IOBERR AND NOT IODONE AND iobm/IOS_FSM_FFd3));
|
|
|
|
|
|
|
|
|
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|
|
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0');
|
|
|
|
|
|
|
|
|
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|
|
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0');
|
|
|
|
|
|
|
|
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|
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobm/IOS_FSM_FFd6_D <= (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOREQr AND
|
|
|
|
|
|
NOT nAoutOE);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0');
|
|
|
|
|
|
iobm/IOS_FSM_FFd7_D <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT iobm/C8Mr AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1 AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT nAoutOE));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
|
|
|
|
|
|
iobs/Clear1_D <= (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IODONEr: FDCPE port map (iobs/IODONEr,IODONE,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
|
|
|
|
|
|
iobs/IORW1_T <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
iobs/TS_FSM_FFd1 AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND iobs/IORW1 AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND iobs/IORW1 AND MCKE AND iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
fsb/ASrf AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND iobs/IORW1 AND MCKE AND iobs/TS_FSM_FFd2 AND
|
|
|
|
|
|
fsb/ASrf AND nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
|
|
|
|
|
|
iobs/Load1_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND NOT nAS_FSB AND MCKE AND iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND NOT nAS_FSB AND MCKE AND iobs/TS_FSM_FFd2 AND
|
|
|
|
|
|
nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND MCKE AND iobs/TS_FSM_FFd1 AND fsb/ASrf AND
|
|
|
|
|
|
nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
|
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(22) AND NOT A_FSB(23) AND NOT iobs/Sent AND
|
|
|
|
|
|
NOT IOQoSEN AND NOT nWE_FSB AND MCKE AND iobs/TS_FSM_FFd2 AND fsb/ASrf AND
|
|
|
|
|
|
nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/Sent: FDCPE port map (iobs/Sent,iobs/Sent_D,FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobs/Sent_D <= ((nBERR_FSB_OBUF.EXP)
|
|
|
|
|
|
OR (A_FSB(23) AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
|
|
|
|
|
|
OR (IOQoSEN AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf AND nADoutLE1)
|
|
|
|
|
|
OR (iobs/Sent AND NOT nAS_FSB AND MCKE)
|
|
|
|
|
|
OR (iobs/Sent AND MCKE AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT nAS_FSB AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
|
|
|
|
|
OR (IOQoSEN AND NOT nAS_FSB AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0');
|
|
|
|
|
|
iobs/TS_FSM_FFd1_D <= ((iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_iobs/TS_FSM_FFd2: FTCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_T,FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
iobs/TS_FSM_FFd2_T <= ((IONPReady.EXP)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(23) AND NOT iobs/Sent AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf)
|
|
|
|
|
|
OR (NOT iobs/Sent AND IOQoSEN AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (NOT iobs/Sent AND IOQoSEN AND MCKE AND NOT iobs/TS_FSM_FFd1 AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd2 AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
|
|
|
|
|
OR (iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2 AND
|
|
|
|
|
|
iobs/IOACTr)
|
|
|
|
|
|
OR (NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND NOT nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT iobs/Sent AND NOT nAS_FSB AND MCKE AND
|
|
|
|
|
|
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
|
|
|
|
|
|
nADoutLE1_D <= ((iobs/Load1)
|
|
|
|
|
|
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
|
|
|
|
|
|
nAS_IOB <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nAS_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
nAoutOE_D <= ((NOT nBR_IOB AND cnt/IS_FSM_FFd2 AND cnt/IS_FSM_FFd1)
|
|
|
|
|
|
OR (NOT cnt/IS_FSM_FFd2 AND cnt/IS_FSM_FFd1 AND NOT nAoutOE));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_nBERR_FSB: FDCPE port map (nBERR_FSB,nBERR_FSB_D,FCLK,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
nBERR_FSB_D <= ((iobs/Sent AND IOBERR AND NOT nAS_FSB AND MCKE)
|
|
|
|
|
|
OR (iobs/Sent AND IOBERR AND MCKE AND fsb/ASrf)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (NOT nAS_FSB AND NOT nBERR_FSB AND MCKE)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT nBERR_FSB AND MCKE AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FTCPE_nBR_IOB: FTCPE port map (nBR_IOB,nBR_IOB_T,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
nBR_IOB_T <= ((NOT nBR_IOB AND cnt/IS_FSM_FFd2 AND NOT cnt/IS_FSM_FFd1 AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT cnt/nIPL2r)
|
2024-09-30 03:15:06 +00:00
|
|
|
|
OR (nBR_IOB AND NOT cnt/IS_FSM_FFd2 AND NOT cnt/IS_FSM_FFd1));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_nCAS: FDCPE port map (nCAS,nCAS_D,NOT FCLK,'0','0');
|
|
|
|
|
|
nCAS_D <= ((ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (ram/RS_FSM_FFd2)
|
|
|
|
|
|
OR (ram/RS_FSM_FFd3)
|
|
|
|
|
|
OR (EXP11_.EXP)
|
|
|
|
|
|
OR (NOT RefUrg AND ram/RS_FSM_FFd4)
|
|
|
|
|
|
OR (NOT RefUrg AND ram/RS_FSM_FFd7)
|
|
|
|
|
|
OR (ram/RefDone AND ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (ram/RefDone AND ram/RS_FSM_FFd4)
|
|
|
|
|
|
OR (NOT RefUrg AND ram/RS_FSM_FFd8 AND BACTr)
|
|
|
|
|
|
OR (NOT RefUrg AND NOT RefReq AND ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (ram/RefDone AND ram/RS_FSM_FFd7)
|
|
|
|
|
|
OR (ram/DTACKr AND ram/RS_FSM_FFd5));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0');
|
|
|
|
|
|
nDTACK_FSB_D <= ((NOT MCKE)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND NOT IONPReady)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23))
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT IONPReady AND NOT nWE_FSB AND
|
2024-09-29 07:29:49 +00:00
|
|
|
|
NOT nADoutLE1)
|
|
|
|
|
|
OR (A_FSB(23) AND NOT IONPReady)
|
|
|
|
|
|
OR (IOQoSEN AND NOT IONPReady)
|
|
|
|
|
|
OR (nAS_FSB AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND NOT IONPReady));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
|
|
|
|
|
|
nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nDinOE <= NOT (((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
|
|
|
|
|
|
OR (A_FSB(21) AND A_FSB(22) AND nWE_FSB AND NOT nAS_FSB)
|
|
|
|
|
|
OR (A_FSB(20) AND A_FSB(22) AND nWE_FSB AND NOT nAS_FSB)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nDoutOE <= NOT (((iobm/DoutOE AND NOT nAoutOE)
|
2024-10-01 03:36:18 +00:00
|
|
|
|
OR (NOT iobm/IOREQr AND iobm/IOS0 AND NOT nAoutOE)));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
nLDS_IOB <= ((NOT IOL0)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nLDS_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nOE: FDCPE port map (nOE,nOE_D,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
nOE_D <= ((nWE_FSB AND NOT nAS_FSB AND MCKE AND NOT ram/DTACKr)
|
|
|
|
|
|
OR (nWE_FSB AND NOT nAS_FSB AND MCKE AND NOT BACTr)
|
|
|
|
|
|
OR (nWE_FSB AND MCKE AND NOT ram/DTACKr AND fsb/ASrf)
|
|
|
|
|
|
OR (nWE_FSB AND MCKE AND NOT BACTr AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
2024-10-01 03:36:18 +00:00
|
|
|
|
nRAMLWE <= NOT ((NOT nLDS_FSB AND NOT nWE_FSB AND ram/RASEL));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND ram/RASEL));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nRAS <= NOT (((ram/RASrf)
|
|
|
|
|
|
OR (ram/RASrr)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
|
|
|
|
|
ram/RASEN)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nRES_I <= '0';
|
|
|
|
|
|
nRES <= nRES_I when nRES_OE = '1' else 'Z';
|
|
|
|
|
|
nRES_OE <= NOT nRESout;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
|
2024-09-30 03:15:06 +00:00
|
|
|
|
nRESout_D <= (NOT cnt/IS_FSM_FFd2 AND cnt/IS_FSM_FFd1);
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nROMOE <= NOT (((cs/Overlay AND nWE_FSB AND NOT nAS_FSB)
|
|
|
|
|
|
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
|
|
|
|
|
nWE_FSB AND NOT nAS_FSB)));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
nROMWE <= NOT ((NOT A_FSB(21) AND NOT A_FSB(20) AND A_FSB(22) AND NOT A_FSB(23) AND
|
|
|
|
|
|
NOT nWE_FSB AND NOT nAS_FSB));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
|
2024-10-01 03:36:18 +00:00
|
|
|
|
nUDS_IOB <= ((NOT IOU0)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd3 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
|
|
|
|
|
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nUDS_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C8M,'0','0');
|
|
|
|
|
|
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3))
|
|
|
|
|
|
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(2) AND NOT iobm/ES(1) AND
|
|
|
|
|
|
NOT iobm/ES(3) AND IOACT AND iobm/VPAr));
|
|
|
|
|
|
nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
|
|
|
|
|
|
nVMA_IOB_OE <= NOT nAoutOE;
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
|
|
|
|
|
|
nVPA_FSB_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23) AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
IONPReady AND NOT nAS_FSB AND MCKE)
|
2024-09-29 07:29:49 +00:00
|
|
|
|
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(22) AND A_FSB(23) AND
|
2024-10-01 03:36:18 +00:00
|
|
|
|
IONPReady AND MCKE AND fsb/ASrf));
|
2024-09-29 07:29:49 +00:00
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/DTACKr: FDCPE port map (ram/DTACKr,NOT nDTACK_FSB,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RASEL_D <= ((ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND ram/RS_FSM_FFd8 AND ram/RASEN)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND MCKE AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN AND fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASEN: FDCPE port map (ram/RASEN,ram/RASEN_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RASEN_D <= ((nROMOE_OBUF.EXP)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT MCKE AND NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
|
|
|
|
|
|
OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
NOT ram/RS_FSM_FFd1));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASrf: FDCPE port map (ram/RASrf,ram/RS_FSM_FFd6,NOT FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RASrr: FDCPE port map (ram/RASrr,ram/RASrr_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RASrr_D <= ((ram/RS_FSM_FFd7)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT MCKE AND ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND ram/RS_FSM_FFd8 AND NOT BACTr)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND ram/RS_FSM_FFd8 AND ram/RASEN)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND MCKE AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND MCKE AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND ram/RS_FSM_FFd8 AND NOT BACTr)
|
|
|
|
|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND MCKE AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd4)
|
|
|
|
|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
|
|
|
|
|
ram/RS_FSM_FFd8)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND
|
|
|
|
|
|
NOT ram/RASEN));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd1: FDCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd2,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd2: FDCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd3,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd3: FDCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd7,FCLK,'0','0');
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd4: FDCPE port map (ram/RS_FSM_FFd4,ram/RS_FSM_FFd4_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RS_FSM_FFd4_D <= (ram/DTACKr AND ram/RS_FSM_FFd5);
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd5: FDCPE port map (ram/RS_FSM_FFd5,ram/RS_FSM_FFd5_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RS_FSM_FFd5_D <= ((ram/RS_FSM_FFd6)
|
|
|
|
|
|
OR (NOT ram/DTACKr AND ram/RS_FSM_FFd5));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd6: FDCPE port map (ram/RS_FSM_FFd6,ram/RS_FSM_FFd6_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RS_FSM_FFd6_D <= ((NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND ram/RS_FSM_FFd8 AND ram/RASEN)
|
|
|
|
|
|
OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND MCKE AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND ram/RASEN AND fsb/ASrf));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_ram/RS_FSM_FFd7: FDCPE port map (ram/RS_FSM_FFd7,ram/RS_FSM_FFd7_D,FCLK,'0','0');
|
|
|
|
|
|
ram/RS_FSM_FFd7_D <= ((A_FSB(23) AND RefReq AND NOT ram/RefDone AND MCKE AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
|
|
|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT fsb/ASrf)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
|
|
|
|
|
MCKE AND ram/RS_FSM_FFd8 AND NOT BACTr)
|
|
|
|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND MCKE AND
|
|
|
|
|
|
ram/RS_FSM_FFd8 AND NOT BACTr AND fsb/ASrf)
|
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|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
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MCKE AND ram/RS_FSM_FFd8 AND NOT BACTr)
|
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OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd4)
|
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OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
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ram/RS_FSM_FFd8)
|
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OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
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ram/RS_FSM_FFd8)
|
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OR (RefUrg AND NOT ram/RefDone AND NOT MCKE AND ram/RS_FSM_FFd8)
|
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OR (RefUrg AND NOT ram/RefDone AND ram/RS_FSM_FFd8 AND
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NOT ram/RASEN));
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FDCPE_ram/RS_FSM_FFd8: FDCPE port map (ram/RS_FSM_FFd8,ram/RS_FSM_FFd8_D,FCLK,'0','0');
|
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|
|
ram/RS_FSM_FFd8_D <= ((RA_6_OBUF.EXP)
|
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|
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OR (RefUrg AND NOT ram/RefDone AND NOT MCKE AND NOT ram/RS_FSM_FFd1)
|
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OR (RefUrg AND NOT ram/RefDone AND NOT ram/RS_FSM_FFd8 AND
|
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NOT ram/RS_FSM_FFd1)
|
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OR (RefUrg AND NOT ram/RefDone AND nAS_FSB AND
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NOT ram/RS_FSM_FFd1 AND NOT fsb/ASrf)
|
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OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND NOT nAS_FSB AND
|
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|
|
MCKE AND NOT ram/RS_FSM_FFd4 AND ram/RASEN AND NOT ram/RS_FSM_FFd1)
|
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|
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OR (NOT A_FSB(22) AND NOT A_FSB(23) AND NOT cs/Overlay AND MCKE AND
|
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|
|
NOT ram/RS_FSM_FFd4 AND ram/RASEN AND NOT ram/RS_FSM_FFd1 AND fsb/ASrf)
|
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|
|
|
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
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|
|
MCKE AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
|
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|
|
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT nAS_FSB AND
|
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|
|
MCKE AND NOT ram/RS_FSM_FFd4 AND NOT ram/RS_FSM_FFd1 AND NOT BACTr)
|
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OR (NOT ram/RS_FSM_FFd8 AND NOT ram/RS_FSM_FFd4 AND
|
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|
|
NOT ram/RS_FSM_FFd1)
|
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|
|
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND
|
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|
|
NOT ram/RS_FSM_FFd1)
|
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|
|
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND
|
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|
|
NOT ram/RS_FSM_FFd1)
|
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|
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|
|
OR (RefUrg AND NOT cs/Overlay AND NOT ram/RefDone AND
|
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|
|
NOT ram/RS_FSM_FFd1)
|
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|
|
|
|
OR (RefUrg AND NOT ram/RefDone AND NOT ram/RASEN AND
|
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|
|
|
NOT ram/RS_FSM_FFd1));
|
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|
|
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
|
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|
|
|
ram/RefDone_D <= ((NOT RefUrg AND NOT RefReq)
|
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|
|
OR (NOT ram/RefDone AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd7 AND
|
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|
|
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3));
|
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|
Register Legend:
|
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|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
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FTCPE (Q,D,C,CLR,PRE,CE);
|
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|
LDCP (Q,D,G,CLR,PRE);
|
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|
|
|
|
****************************** Device Pin Out *****************************
|
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|
|
Device : XC95144XL-10-TQ100
|
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|
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|
|
|
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|
|
--------------------------------------------------
|
|
|
|
|
|
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
|
|
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|
|
| 99 97 95 93 91 89 87 85 83 81 79 77 |
|
|
|
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|
|
| 1 75 |
|
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|
| 2 74 |
|
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| 3 73 |
|
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| 4 72 |
|
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| 5 71 |
|
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| 6 70 |
|
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|
| 7 69 |
|
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|
|
| 8 68 |
|
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| 9 67 |
|
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| 10 66 |
|
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|
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| 11 65 |
|
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|
|
| 12 64 |
|
|
|
|
|
|
| 13 XC95144XL-10-TQ100 63 |
|
|
|
|
|
|
| 14 62 |
|
|
|
|
|
|
| 15 61 |
|
|
|
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|
|
| 16 60 |
|
|
|
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|
|
| 17 59 |
|
|
|
|
|
|
| 18 58 |
|
|
|
|
|
|
| 19 57 |
|
|
|
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|
|
| 20 56 |
|
|
|
|
|
|
| 21 55 |
|
|
|
|
|
|
| 22 54 |
|
|
|
|
|
|
| 23 53 |
|
|
|
|
|
|
| 24 52 |
|
|
|
|
|
|
| 25 51 |
|
|
|
|
|
|
| 27 29 31 33 35 37 39 41 43 45 47 49 |
|
|
|
|
|
|
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
|
|
|
|
|
|
--------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
|
|
|
|
No. Name No. Name
|
|
|
|
|
|
1 KPR 51 VCC
|
|
|
|
|
|
2 A_FSB<5> 52 RA<7>
|
|
|
|
|
|
3 A_FSB<6> 53 RA<0>
|
|
|
|
|
|
4 A_FSB<7> 54 RA<8>
|
|
|
|
|
|
5 VCC 55 RA<10>
|
|
|
|
|
|
6 A_FSB<8> 56 RA<9>
|
|
|
|
|
|
7 A_FSB<9> 57 VCC
|
|
|
|
|
|
8 A_FSB<10> 58 MCKE
|
|
|
|
|
|
9 A_FSB<11> 59 KPR
|
|
|
|
|
|
10 A_FSB<12> 60 GA<23>
|
|
|
|
|
|
11 A_FSB<13> 61 GA<22>
|
|
|
|
|
|
12 A_FSB<14> 62 GND
|
|
|
|
|
|
13 A_FSB<15> 63 RA<11>
|
|
|
|
|
|
14 A_FSB<16> 64 nRAS
|
|
|
|
|
|
15 A_FSB<17> 65 nRAMLWE
|
|
|
|
|
|
16 A_FSB<18> 66 nRAMUWE
|
|
|
|
|
|
17 A_FSB<19> 67 KPR
|
|
|
|
|
|
18 A_FSB<20> 68 KPR
|
|
|
|
|
|
19 A_FSB<21> 69 GND
|
|
|
|
|
|
20 A_FSB<22> 70 nBERR_FSB
|
|
|
|
|
|
21 GND 71 KPR
|
|
|
|
|
|
22 C16M 72 nBR_IOB
|
|
|
|
|
|
23 C8M 73 KPR
|
|
|
|
|
|
24 A_FSB<23> 74 nVMA_IOB
|
|
|
|
|
|
25 E 75 GND
|
|
|
|
|
|
26 VCC 76 nBERR_IOB
|
|
|
|
|
|
27 FCLK 77 nVPA_IOB
|
|
|
|
|
|
28 nDTACK_FSB 78 nDTACK_IOB
|
|
|
|
|
|
29 nWE_FSB 79 nLDS_IOB
|
|
|
|
|
|
30 nLDS_FSB 80 nUDS_IOB
|
|
|
|
|
|
31 GND 81 nAS_IOB
|
|
|
|
|
|
32 nAS_FSB 82 nADoutLE1
|
|
|
|
|
|
33 nUDS_FSB 83 TDO
|
|
|
|
|
|
34 nROMWE 84 GND
|
|
|
|
|
|
35 nROMOE 85 nADoutLE0
|
|
|
|
|
|
36 nCAS 86 nDinLE
|
|
|
|
|
|
37 nOE 87 nAoutOE
|
|
|
|
|
|
38 VCC 88 VCC
|
|
|
|
|
|
39 KPR 89 nDoutOE
|
|
|
|
|
|
40 RA<4> 90 nDinOE
|
|
|
|
|
|
41 RA<3> 91 nRES
|
|
|
|
|
|
42 RA<5> 92 nIPL2
|
|
|
|
|
|
43 RA<2> 93 nVPA_FSB
|
|
|
|
|
|
44 GND 94 A_FSB<1>
|
|
|
|
|
|
45 TDI 95 A_FSB<2>
|
|
|
|
|
|
46 RA<6> 96 A_FSB<3>
|
|
|
|
|
|
47 TMS 97 A_FSB<4>
|
|
|
|
|
|
48 TCK 98 VCC
|
2024-10-01 03:36:18 +00:00
|
|
|
|
49 KPR 99 RnW_IOB
|
2024-09-29 07:29:49 +00:00
|
|
|
|
50 RA<1> 100 GND
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
|
|
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
|
|
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
|
|
|
|
KPR = Unused I/O with weak keeper (leave unconnected)
|
|
|
|
|
|
VCC = Dedicated Power Pin
|
|
|
|
|
|
GND = Dedicated Ground Pin
|
|
|
|
|
|
TDI = Test Data In, JTAG pin
|
|
|
|
|
|
TDO = Test Data Out, JTAG pin
|
|
|
|
|
|
TCK = Test Clock, JTAG pin
|
|
|
|
|
|
TMS = Test Mode Select, JTAG pin
|
|
|
|
|
|
PROHIBITED = User reserved pin
|
|
|
|
|
|
**************************** Compiler Options ****************************
|
|
|
|
|
|
|
|
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
|
|
|
|
|
|
|
|
Device(s) Specified : xc95144xl-10-TQ100
|
|
|
|
|
|
Optimization Method : SPEED
|
|
|
|
|
|
Multi-Level Logic Optimization : ON
|
|
|
|
|
|
Ignore Timing Specifications : OFF
|
|
|
|
|
|
Default Register Power Up Value : LOW
|
|
|
|
|
|
Keep User Location Constraints : ON
|
|
|
|
|
|
What-You-See-Is-What-You-Get : OFF
|
|
|
|
|
|
Exhaustive Fitting : OFF
|
|
|
|
|
|
Keep Unused Inputs : OFF
|
|
|
|
|
|
Slew Rate : FAST
|
|
|
|
|
|
Power Mode : STD
|
|
|
|
|
|
Ground on Unused IOs : OFF
|
|
|
|
|
|
Set I/O Pin Termination : KEEPER
|
|
|
|
|
|
Global Clock Optimization : ON
|
|
|
|
|
|
Global Set/Reset Optimization : ON
|
|
|
|
|
|
Global Ouput Enable Optimization : ON
|
|
|
|
|
|
Input Limit : 54
|
|
|
|
|
|
Pterm Limit : 25
|
