2023-03-20 05:13:11 +00:00
Release 14.7 - xst P.20131013 (nt64)
2021-10-29 10:04:59 +00:00
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
2023-03-20 05:13:11 +00:00
Total REAL time to Xst completion: 0.00 secs
2023-04-01 12:25:24 +00:00
Total CPU time to Xst completion: 0.09 secs
2021-10-29 10:04:59 +00:00
--> Parameter xsthdpdir set to xst
2023-03-20 05:13:11 +00:00
Total REAL time to Xst completion: 0.00 secs
2023-04-01 12:25:24 +00:00
Total CPU time to Xst completion: 0.09 secs
2021-10-29 10:04:59 +00:00
2022-03-29 08:23:54 +00:00
--> Reading design: WarpSE.prj
2021-10-29 10:04:59 +00:00
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
2022-03-29 08:23:54 +00:00
Input File Name : "WarpSE.prj"
2021-10-29 10:04:59 +00:00
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
2022-03-29 08:23:54 +00:00
Output File Name : "WarpSE"
2021-10-29 10:04:59 +00:00
Output Format : NGC
Target Device : XC9500XL CPLDs
---- Source Options
2022-03-29 08:23:54 +00:00
Top Module Name : WarpSE
2021-10-29 10:04:59 +00:00
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
2023-03-26 08:33:59 +00:00
Optimization Effort : 1
Keep Hierarchy : Yes
2021-10-29 10:04:59 +00:00
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
2023-04-07 06:33:04 +00:00
Compiling verilog file "RAM.v" in library work
Compiling verilog file "IOBS.v" in library work
2023-03-20 05:13:11 +00:00
Module <RAM> compiled
2023-04-07 06:33:04 +00:00
Compiling verilog file "IOBM.v" in library work
2021-10-29 10:04:59 +00:00
Module <IOBS> compiled
2023-04-07 06:33:04 +00:00
Compiling verilog file "FSB.v" in library work
2021-10-29 10:04:59 +00:00
Module <IOBM> compiled
2023-04-07 06:33:04 +00:00
Compiling verilog file "CS.v" in library work
2021-10-29 10:04:59 +00:00
Module <FSB> compiled
2023-04-07 06:33:04 +00:00
Compiling verilog file "CNT.v" in library work
2021-10-29 10:04:59 +00:00
Module <CS> compiled
2023-04-07 06:33:04 +00:00
Compiling verilog file "WarpSE.v" in library work
2023-03-20 05:13:11 +00:00
Module <CNT> compiled
2022-03-29 08:23:54 +00:00
Module <WarpSE> compiled
2023-03-22 01:11:58 +00:00
No errors in compilation
Analysis of file <"WarpSE.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <WarpSE> in library <work>.
Analyzing hierarchy for module <CS> in library <work>.
Analyzing hierarchy for module <RAM> in library <work>.
Analyzing hierarchy for module <IOBS> in library <work>.
Analyzing hierarchy for module <IOBM> in library <work>.
Analyzing hierarchy for module <CNT> in library <work>.
Analyzing hierarchy for module <FSB> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <WarpSE>.
Module <WarpSE> is correct for synthesis.
Analyzing module <CS> in library <work>.
Module <CS> is correct for synthesis.
Analyzing module <RAM> in library <work>.
Module <RAM> is correct for synthesis.
Analyzing module <IOBS> in library <work>.
Module <IOBS> is correct for synthesis.
Analyzing module <IOBM> in library <work>.
Module <IOBM> is correct for synthesis.
Analyzing module <CNT> in library <work>.
Module <CNT> is correct for synthesis.
Analyzing module <FSB> in library <work>.
Module <FSB> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <CS>.
2023-04-07 06:33:04 +00:00
Related source file is "CS.v".
WARNING:Xst:1305 - Output <SndRAMCSWR> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <A<11:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
2023-03-26 08:33:59 +00:00
Found 1-bit register for signal <nOverlay>.
2023-04-01 08:46:47 +00:00
Found 1-bit register for signal <ODCSr>.
2023-03-22 01:11:58 +00:00
Summary:
2023-04-01 08:46:47 +00:00
inferred 2 D-type flip-flop(s).
2023-03-22 01:11:58 +00:00
Unit <CS> synthesized.
Synthesizing Unit <RAM>.
2023-04-07 06:33:04 +00:00
Related source file is "RAM.v".
2023-03-22 01:11:58 +00:00
Found finite state machine <FSM_0> for signal <RS>.
-----------------------------------------------------------------------
| States | 8 |
2023-04-07 04:41:16 +00:00
| Transitions | 11 |
| Inputs | 3 |
| Outputs | 8 |
2023-03-22 01:11:58 +00:00
| Clock | CLK (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <nCAS>.
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <RAMReady>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <BACTr>.
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <CAS>.
Found 1-bit register for signal <Once>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <RAMEN>.
Found 1-bit register for signal <RASEL>.
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <RASrf>.
Found 1-bit register for signal <RASrr>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <RefDone>.
Summary:
inferred 1 Finite State Machine(s).
2023-04-07 06:33:04 +00:00
inferred 7 D-type flip-flop(s).
2023-03-22 01:11:58 +00:00
Unit <RAM> synthesized.
Synthesizing Unit <IOBS>.
2023-04-07 06:33:04 +00:00
Related source file is "IOBS.v".
2023-04-01 08:46:47 +00:00
Found finite state machine <FSM_1> for signal <TS>.
2023-03-22 01:11:58 +00:00
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 10 |
| Inputs | 5 |
2023-04-07 04:41:16 +00:00
| Outputs | 5 |
2023-03-22 01:11:58 +00:00
| Clock | CLK (rising_edge) |
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <IOPWReady>.
Found 1-bit register for signal <IORDREQ>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <IOL0>.
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <IOWRREQ>.
Found 1-bit register for signal <IONPReady>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <IOU0>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <ALE1>.
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <nBERR_FSB>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <Clear1>.
Found 1-bit register for signal <IOACTr>.
2023-04-07 06:33:04 +00:00
Found 1-bit register for signal <IODONEr>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <IOL1>.
Found 1-bit register for signal <IORW1>.
Found 1-bit register for signal <IOU1>.
Found 1-bit register for signal <Load1>.
2023-04-01 08:46:47 +00:00
Found 1-bit register for signal <Sent>.
2023-03-22 01:11:58 +00:00
Summary:
inferred 1 Finite State Machine(s).
2023-04-07 06:33:04 +00:00
inferred 10 D-type flip-flop(s).
2023-03-22 01:11:58 +00:00
Unit <IOBS> synthesized.
Synthesizing Unit <IOBM>.
2023-04-07 06:33:04 +00:00
Related source file is "IOBM.v".
2023-03-22 01:11:58 +00:00
Found finite state machine <FSM_2> for signal <IOS>.
-----------------------------------------------------------------------
2023-04-07 04:41:16 +00:00
| States | 7 |
| Transitions | 13 |
| Inputs | 5 |
| Outputs | 7 |
2023-03-22 01:11:58 +00:00
| Clock | C16M (rising_edge) |
| Power Up State | 000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <IOBERR>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <nASout>.
Found 1-bit register for signal <IOACT>.
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <IODONE>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <nLDS>.
Found 1-bit register for signal <nUDS>.
Found 1-bit register for signal <nDinLE>.
Found 1-bit register for signal <ALE0>.
Found 1-bit register for signal <nVMA>.
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <C8Mr>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <DoutOE>.
Found 1-bit register for signal <Er>.
2023-04-07 04:41:16 +00:00
Found 4-bit up counter for signal <ES>.
Found 1-bit register for signal <IORDREQr>.
Found 1-bit register for signal <IOS0>.
Found 1-bit register for signal <IOWRREQr>.
2023-04-01 08:46:47 +00:00
Found 1-bit register for signal <VPAr>.
2023-03-22 01:11:58 +00:00
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
2023-04-01 08:46:47 +00:00
inferred 15 D-type flip-flop(s).
2023-03-22 01:11:58 +00:00
Unit <IOBM> synthesized.
Synthesizing Unit <CNT>.
2023-04-07 06:33:04 +00:00
Related source file is "CNT.v".
2023-03-26 08:33:59 +00:00
Found finite state machine <FSM_3> for signal <INITS>.
2023-03-22 01:11:58 +00:00
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 8 |
| Inputs | 2 |
| Outputs | 4 |
2023-03-26 08:33:59 +00:00
| Clock | CLK (rising_edge) |
2023-03-22 01:11:58 +00:00
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <RefReq>.
Found 1-bit register for signal <nBR_IOB>.
Found 1-bit register for signal <nRESout>.
Found 1-bit register for signal <AoutOE>.
2023-03-26 08:33:59 +00:00
Found 2-bit register for signal <Er>.
Found 13-bit up counter for signal <LTimer>.
Found 1-bit register for signal <LTimerTC>.
Found 1-bit register for signal <nIPL2r>.
2023-03-22 01:11:58 +00:00
Found 4-bit up counter for signal <Timer>.
Found 1-bit register for signal <TimerTC>.
Summary:
inferred 1 Finite State Machine(s).
inferred 2 Counter(s).
inferred 7 D-type flip-flop(s).
Unit <CNT> synthesized.
Synthesizing Unit <FSB>.
2023-04-07 06:33:04 +00:00
Related source file is "FSB.v".
2023-04-07 04:41:16 +00:00
Found 1-bit register for signal <nVPA>.
2023-03-22 01:11:58 +00:00
Found 1-bit register for signal <nDTACK>.
Found 1-bit register for signal <ASrf>.
Summary:
2023-04-07 04:41:16 +00:00
inferred 3 D-type flip-flop(s).
2023-03-22 01:11:58 +00:00
Unit <FSB> synthesized.
Synthesizing Unit <WarpSE>.
2023-04-07 06:33:04 +00:00
Related source file is "WarpSE.v".
2023-03-26 08:33:59 +00:00
WARNING:Xst:647 - Input <SW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
2023-03-25 07:49:44 +00:00
WARNING:Xst:647 - Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
2023-03-22 01:11:58 +00:00
Found 1-bit tristate buffer for signal <nAS_IOB>.
Found 1-bit tristate buffer for signal <nLDS_IOB>.
Found 1-bit tristate buffer for signal <nRES>.
Found 1-bit tristate buffer for signal <nUDS_IOB>.
Found 1-bit tristate buffer for signal <nVMA_IOB>.
Summary:
inferred 5 Tristate(s).
Unit <WarpSE> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 3
2023-03-26 08:33:59 +00:00
13-bit up counter : 1
2023-04-07 04:41:16 +00:00
4-bit up counter : 2
# Registers : 56
2023-04-07 06:33:04 +00:00
1-bit register : 55
2-bit register : 1
2023-03-22 01:11:58 +00:00
# Tristates : 5
1-bit tristate buffer : 5
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_3> for best encoding.
2023-03-26 08:33:59 +00:00
Optimizing FSM <cnt/INITS/FSM> on signal <INITS[1:2]> with johnson encoding.
2023-03-22 01:11:58 +00:00
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 11
11 | 10
-------------------
Analyzing FSM <FSM_2> for best encoding.
2023-04-07 04:41:16 +00:00
Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:7]> with one-hot encoding.
2023-03-22 01:11:58 +00:00
-------------------
State | Encoding
-------------------
2023-04-07 04:41:16 +00:00
000 | 0000001
010 | 0000010
011 | 0000100
100 | 0001000
101 | 0010000
110 | 0100000
111 | 1000000
2023-03-22 01:11:58 +00:00
-------------------
Analyzing FSM <FSM_1> for best encoding.
2023-04-01 08:46:47 +00:00
Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
2023-03-22 01:11:58 +00:00
-------------------
State | Encoding
-------------------
00 | 00
11 | 01
10 | 11
01 | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
2023-04-07 04:41:16 +00:00
Optimizing FSM <ram/RS/FSM> on signal <RS[1:8]> with one-hot encoding.
2023-03-22 01:11:58 +00:00
-------------------
State | Encoding
-------------------
2023-04-07 04:41:16 +00:00
000 | 00000001
001 | 00000010
011 | 00000100
010 | 00001000
111 | 00010000
100 | 00100000
101 | 01000000
110 | 10000000
2023-03-22 01:11:58 +00:00
-------------------
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 4
# Counters : 3
2023-03-26 08:33:59 +00:00
13-bit up counter : 1
2023-04-07 04:41:16 +00:00
4-bit up counter : 2
2023-04-07 06:33:04 +00:00
# Registers : 44
Flip-Flops : 44
2023-03-22 01:11:58 +00:00
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <WarpSE> ...
2023-03-26 08:33:59 +00:00
Optimizing unit <CS> ...
implementation constraint: INIT=r : nOverlay
Optimizing unit <RAM> ...
2023-04-07 04:41:16 +00:00
implementation constraint: INIT=s : RS_FSM_FFd8
2023-03-26 08:33:59 +00:00
implementation constraint: INIT=r : RASEL
2023-04-07 04:41:16 +00:00
implementation constraint: INIT=r : CAS
implementation constraint: INIT=r : RASrr
implementation constraint: INIT=r : RS_FSM_FFd7
implementation constraint: INIT=r : Once
2023-04-07 06:33:04 +00:00
implementation constraint: INIT=r : RASrf
2023-04-07 04:41:16 +00:00
implementation constraint: INIT=r : RAMEN
2023-03-26 08:33:59 +00:00
implementation constraint: INIT=r : RS_FSM_FFd1
implementation constraint: INIT=r : RS_FSM_FFd2
implementation constraint: INIT=r : RS_FSM_FFd3
2023-04-07 04:41:16 +00:00
implementation constraint: INIT=r : RS_FSM_FFd4
implementation constraint: INIT=r : RS_FSM_FFd5
2023-04-07 06:33:04 +00:00
implementation constraint: INIT=r : RS_FSM_FFd6
2023-03-26 08:33:59 +00:00
Optimizing unit <IOBS> ...
implementation constraint: INIT=r : IOACTr
2023-04-01 08:46:47 +00:00
implementation constraint: INIT=r : TS_FSM_FFd2
implementation constraint: INIT=r : Sent
implementation constraint: INIT=r : TS_FSM_FFd1
2023-03-26 08:33:59 +00:00
2023-04-07 06:33:04 +00:00
Optimizing unit <FSB> ...
implementation constraint: INIT=r : ASrf
2023-03-26 08:33:59 +00:00
Optimizing unit <IOBM> ...
2023-04-07 04:41:16 +00:00
implementation constraint: INIT=s : IOS_FSM_FFd7
2023-03-26 08:33:59 +00:00
implementation constraint: INIT=r : DoutOE
2023-04-07 04:41:16 +00:00
implementation constraint: INIT=r : IOS_FSM_FFd6
2023-03-26 08:33:59 +00:00
implementation constraint: INIT=r : IOS_FSM_FFd1
implementation constraint: INIT=r : IOS_FSM_FFd2
implementation constraint: INIT=r : IOS_FSM_FFd3
2023-04-07 04:41:16 +00:00
implementation constraint: INIT=r : IOS_FSM_FFd4
implementation constraint: INIT=r : IOS_FSM_FFd5
2023-03-26 08:33:59 +00:00
Optimizing unit <CNT> ...
implementation constraint: INIT=r : Timer_3
implementation constraint: INIT=r : Timer_0
implementation constraint: INIT=r : Timer_1
implementation constraint: INIT=r : INITS_FSM_FFd2
implementation constraint: INIT=r : Timer_2
implementation constraint: INIT=r : INITS_FSM_FFd1
2023-03-22 01:11:58 +00:00
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : WarpSE.ngr
Top Level Output File Name : WarpSE
Output Format : NGC
Optimization Goal : Speed
2023-03-26 08:33:59 +00:00
Keep Hierarchy : Yes
2023-03-22 01:11:58 +00:00
Target Technology : XC9500XL CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 75
Cell Usage :
2023-04-07 06:33:04 +00:00
# BELS : 559
# AND2 : 172
# AND3 : 25
# AND4 : 9
2023-04-01 12:25:24 +00:00
# AND5 : 2
2023-04-07 04:41:16 +00:00
# AND6 : 1
# AND7 : 1
# AND8 : 1
# GND : 6
2023-04-07 06:33:04 +00:00
# INV : 214
# OR2 : 96
# OR3 : 11
2023-04-07 04:41:16 +00:00
# OR4 : 2
2023-04-01 08:46:47 +00:00
# VCC : 1
2023-04-07 04:41:16 +00:00
# XOR2 : 18
2023-04-07 06:33:04 +00:00
# FlipFlops/Latches : 97
# FD : 61
2023-04-07 04:41:16 +00:00
# FDC : 2
# FDCE : 33
# FDP : 1
2023-04-07 06:33:04 +00:00
# IO Buffers : 71
# IBUF : 35
2023-03-22 01:11:58 +00:00
# IOBUFE : 1
# OBUF : 31
# OBUFE : 4
=========================================================================
2023-03-26 08:33:59 +00:00
Total REAL time to Xst completion: 5.00 secs
2023-04-07 06:33:04 +00:00
Total CPU time to Xst completion: 5.04 secs
2023-03-22 01:11:58 +00:00
2021-10-29 10:04:59 +00:00
-->
2023-04-07 06:33:04 +00:00
Total memory usage is 261508 kilobytes
2021-10-29 10:04:59 +00:00
2023-03-22 01:11:58 +00:00
Number of errors : 0 ( 0 filtered)
2023-04-07 06:33:04 +00:00
Number of warnings : 5 ( 0 filtered)
2021-10-29 10:04:59 +00:00
Number of infos : 0 ( 0 filtered)
