2021-10-29 10:04:59 +00:00
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Release 14.7 - xst P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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2022-02-07 05:21:01 +00:00
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.09 secs
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2021-10-29 10:04:59 +00:00
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--> Parameter xsthdpdir set to xst
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2022-02-07 05:21:01 +00:00
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.09 secs
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2021-10-29 10:04:59 +00:00
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--> Reading design: MXSE.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "MXSE.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "MXSE"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : MXSE
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../RAM.v" in library work
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Compiling verilog file "../IOBS.v" in library work
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Module <RAM> compiled
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Compiling verilog file "../IOBM.v" in library work
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Module <IOBS> compiled
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Compiling verilog file "../FSB.v" in library work
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Module <IOBM> compiled
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Compiling verilog file "../CS.v" in library work
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Module <FSB> compiled
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Compiling verilog file "../CNT.v" in library work
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Module <CS> compiled
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Compiling verilog file "../MXSE.v" in library work
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Module <CNT> compiled
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Module <MXSE> compiled
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No errors in compilation
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Analysis of file <"MXSE.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <MXSE> in library <work>.
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Analyzing hierarchy for module <CS> in library <work>.
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Analyzing hierarchy for module <RAM> in library <work>.
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Analyzing hierarchy for module <IOBS> in library <work>.
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Analyzing hierarchy for module <IOBM> in library <work>.
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Analyzing hierarchy for module <CNT> in library <work>.
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Analyzing hierarchy for module <FSB> in library <work>.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <MXSE>.
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Module <MXSE> is correct for synthesis.
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Analyzing module <CS> in library <work>.
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Module <CS> is correct for synthesis.
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Analyzing module <RAM> in library <work>.
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Module <RAM> is correct for synthesis.
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Analyzing module <IOBS> in library <work>.
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Module <IOBS> is correct for synthesis.
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Analyzing module <IOBM> in library <work>.
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Module <IOBM> is correct for synthesis.
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Analyzing module <CNT> in library <work>.
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Module <CNT> is correct for synthesis.
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Analyzing module <FSB> in library <work>.
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Module <FSB> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <CS>.
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Related source file is "../CS.v".
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Found 1-bit register for signal <nOverlay0>.
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Found 1-bit register for signal <nOverlay1>.
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Summary:
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inferred 2 D-type flip-flop(s).
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Unit <CS> synthesized.
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Synthesizing Unit <RAM>.
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Related source file is "../RAM.v".
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Found finite state machine <FSM_0> for signal <RS>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 18 |
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| Inputs | 6 |
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| Outputs | 9 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <nCAS>.
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Found 1-bit register for signal <BACTr>.
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Found 1-bit register for signal <Once>.
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Found 1-bit register for signal <RAMDIS1>.
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Found 1-bit register for signal <RAMDIS2>.
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Found 1-bit register for signal <RAMReady>.
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Found 1-bit register for signal <RASEL>.
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Found 1-bit register for signal <RefRAS>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 6 D-type flip-flop(s).
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Unit <RAM> synthesized.
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Synthesizing Unit <IOBS>.
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Related source file is "../IOBS.v".
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Found finite state machine <FSM_1> for signal <PS>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 10 |
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| Inputs | 5 |
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| Outputs | 5 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <BERR>.
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Found 1-bit register for signal <IOREQ>.
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Found 1-bit register for signal <IORW0>.
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Found 1-bit register for signal <IOL0>.
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Found 1-bit register for signal <IOU0>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <ALE1>.
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2022-01-16 15:56:37 +00:00
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Found 1-bit register for signal <Clear1>.
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2021-10-29 10:04:59 +00:00
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Found 1-bit register for signal <IOACTr>.
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Found 1-bit register for signal <IOL1>.
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Found 1-bit register for signal <IOReady>.
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Found 1-bit register for signal <IORW1>.
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Found 1-bit register for signal <IOU1>.
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Found 1-bit register for signal <Load1>.
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Found 1-bit register for signal <Once>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 9 D-type flip-flop(s).
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Unit <IOBS> synthesized.
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Synthesizing Unit <IOBM>.
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Related source file is "../IOBM.v".
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Found finite state machine <FSM_2> for signal <IOS>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 15 |
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| Inputs | 6 |
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2022-02-07 05:21:01 +00:00
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| Outputs | 8 |
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2021-10-29 10:04:59 +00:00
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| Clock | C16M (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <IOBERR>.
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Found 1-bit register for signal <IOACT>.
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Found 1-bit register for signal <nAS>.
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Found 1-bit register for signal <nLDS>.
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Found 1-bit register for signal <nUDS>.
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Found 1-bit register for signal <nDinLE>.
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Found 1-bit register for signal <nDoutOE>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <nVMA>.
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Found 1-bit register for signal <BERRrf>.
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Found 1-bit register for signal <BERRrr>.
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Found 1-bit register for signal <DTACKrf>.
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Found 1-bit register for signal <DTACKrr>.
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Found 1-bit register for signal <Er>.
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Found 1-bit register for signal <Er2>.
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Found 5-bit up counter for signal <ES>.
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Found 1-bit register for signal <ETACK>.
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Found 1-bit register for signal <IOREQr>.
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Found 1-bit register for signal <RESrf>.
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Found 1-bit register for signal <RESrr>.
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Found 1-bit register for signal <VPArf>.
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Found 1-bit register for signal <VPArr>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 20 D-type flip-flop(s).
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Unit <IOBM> synthesized.
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Synthesizing Unit <CNT>.
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Related source file is "../CNT.v".
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Found 1-bit register for signal <TimeoutA>.
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Found 1-bit register for signal <TimeoutB>.
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Found 8-bit up counter for signal <RefCnt>.
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Found 1-bit register for signal <RefDone>.
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2022-01-16 15:56:37 +00:00
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Found 1-bit register for signal <TimeoutBPre>.
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2021-10-29 10:04:59 +00:00
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Summary:
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inferred 1 Counter(s).
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Unit <CNT> synthesized.
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Synthesizing Unit <FSB>.
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Related source file is "../FSB.v".
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Found 1-bit register for signal <nDTACK>.
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Found 1-bit register for signal <ASrf>.
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Found 1-bit register for signal <BERR0r>.
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Found 1-bit register for signal <BERR1r>.
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Found 1-bit register for signal <Ready0r>.
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Found 1-bit register for signal <Ready1r>.
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Found 1-bit register for signal <Ready2r>.
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Found 1-bit register for signal <VPA>.
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Summary:
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inferred 1 D-type flip-flop(s).
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Unit <FSB> synthesized.
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Synthesizing Unit <MXSE>.
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Related source file is "../MXSE.v".
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Unit <MXSE> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Counters : 2
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5-bit up counter : 1
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8-bit up counter : 1
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2022-01-16 15:56:37 +00:00
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# Registers : 58
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1-bit register : 58
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2021-10-29 10:04:59 +00:00
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_2> for best encoding.
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2022-02-07 05:21:01 +00:00
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Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:4]> with johnson encoding.
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2021-10-29 10:04:59 +00:00
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-------------------
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State | Encoding
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-------------------
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000 | 0000
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001 | 0001
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010 | 0011
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011 | 0111
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100 | 1111
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101 | 1110
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110 | 1100
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111 | 1000
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2021-10-29 10:04:59 +00:00
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-------------------
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Analyzing FSM <FSM_1> for best encoding.
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Optimizing FSM <iobs/PS/FSM> on signal <PS[1:2]> with johnson encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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11 | 01
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10 | 11
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01 | 10
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-------------------
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <ram/RS/FSM> on signal <RS[1:3]> with user encoding.
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-------------------
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State | Encoding
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-------------------
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000 | 000
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010 | 010
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101 | 101
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001 | 001
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011 | 011
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100 | 100
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|
|
111 | 111
|
|
|
|
|
110 | 110
|
|
|
|
|
-------------------
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|
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|
=========================================================================
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|
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|
|
Advanced HDL Synthesis Report
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|
|
|
|
|
|
|
|
Macro Statistics
|
|
|
|
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# FSMs : 3
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|
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# Counters : 2
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5-bit up counter : 1
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8-bit up counter : 1
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# Registers : 38
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|
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Flip-Flops : 38
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|
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|
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=========================================================================
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|
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=========================================================================
|
|
|
|
|
* Low Level Synthesis *
|
|
|
|
|
=========================================================================
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Optimizing unit <MXSE> ...
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Optimizing unit <CS> ...
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implementation constraint: INIT=r : nOverlay0
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implementation constraint: INIT=r : nOverlay1
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|
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Optimizing unit <RAM> ...
|
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|
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implementation constraint: INIT=r : RAMReady
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|
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implementation constraint: INIT=r : RASEL
|
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|
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implementation constraint: INIT=r : RAMDIS1
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|
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implementation constraint: INIT=r : RefRAS
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|
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implementation constraint: INIT=r : RAMDIS2
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|
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implementation constraint: INIT=r : Once
|
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|
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implementation constraint: INIT=r : RS_FSM_FFd1
|
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|
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implementation constraint: INIT=r : RS_FSM_FFd2
|
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|
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implementation constraint: INIT=r : RS_FSM_FFd3
|
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|
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|
|
|
Optimizing unit <IOBS> ...
|
|
|
|
|
implementation constraint: INIT=r : IOACTr
|
2022-01-16 15:56:37 +00:00
|
|
|
implementation constraint: INIT=r : PS_FSM_FFd2
|
2021-10-29 10:04:59 +00:00
|
|
|
implementation constraint: INIT=r : Once
|
|
|
|
|
implementation constraint: INIT=r : PS_FSM_FFd1
|
|
|
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|
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Optimizing unit <FSB> ...
|
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|
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implementation constraint: INIT=r : ASrf
|
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|
|
Optimizing unit <IOBM> ...
|
|
|
|
|
implementation constraint: INIT=r : IOREQr
|
2022-02-07 05:21:01 +00:00
|
|
|
implementation constraint: INIT=r : ETACK
|
2021-10-29 10:04:59 +00:00
|
|
|
implementation constraint: INIT=r : IOS_FSM_FFd1
|
|
|
|
|
implementation constraint: INIT=r : IOS_FSM_FFd2
|
|
|
|
|
implementation constraint: INIT=r : IOS_FSM_FFd3
|
|
|
|
|
implementation constraint: INIT=r : IOS_FSM_FFd4
|
|
|
|
|
|
|
|
|
|
Optimizing unit <CNT> ...
|
|
|
|
|
implementation constraint: INIT=r : RefDone
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_7
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_6
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_5
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_4
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_3
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_2
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_1
|
|
|
|
|
implementation constraint: INIT=r : RefCnt_0
|
|
|
|
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
* Partition Report *
|
|
|
|
|
=========================================================================
|
|
|
|
|
|
|
|
|
|
Partition Implementation Status
|
|
|
|
|
-------------------------------
|
|
|
|
|
|
|
|
|
|
No Partitions were found in this design.
|
|
|
|
|
|
|
|
|
|
-------------------------------
|
|
|
|
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
* Final Report *
|
|
|
|
|
=========================================================================
|
|
|
|
|
Final Results
|
|
|
|
|
RTL Top Level Output File Name : MXSE.ngr
|
|
|
|
|
Top Level Output File Name : MXSE
|
|
|
|
|
Output Format : NGC
|
|
|
|
|
Optimization Goal : Speed
|
|
|
|
|
Keep Hierarchy : Yes
|
|
|
|
|
Target Technology : XC9500XL CPLDs
|
|
|
|
|
Macro Preserve : YES
|
|
|
|
|
XOR Preserve : YES
|
|
|
|
|
Clock Enable : YES
|
|
|
|
|
wysiwyg : NO
|
|
|
|
|
|
|
|
|
|
Design Statistics
|
|
|
|
|
# IOs : 67
|
|
|
|
|
|
|
|
|
|
Cell Usage :
|
2022-02-07 05:21:01 +00:00
|
|
|
# BELS : 605
|
|
|
|
|
# AND2 : 170
|
|
|
|
|
# AND3 : 24
|
|
|
|
|
# AND4 : 14
|
|
|
|
|
# AND6 : 2
|
2022-01-16 15:56:37 +00:00
|
|
|
# AND7 : 1
|
2021-10-29 10:04:59 +00:00
|
|
|
# AND8 : 3
|
|
|
|
|
# GND : 6
|
2022-02-07 05:21:01 +00:00
|
|
|
# INV : 255
|
|
|
|
|
# OR2 : 107
|
|
|
|
|
# OR3 : 9
|
|
|
|
|
# OR4 : 1
|
2021-10-29 10:04:59 +00:00
|
|
|
# VCC : 1
|
|
|
|
|
# XOR2 : 12
|
2022-02-07 05:21:01 +00:00
|
|
|
# FlipFlops/Latches : 80
|
|
|
|
|
# FD : 54
|
|
|
|
|
# FDCE : 26
|
2021-10-29 10:04:59 +00:00
|
|
|
# IO Buffers : 67
|
|
|
|
|
# IBUF : 35
|
|
|
|
|
# OBUF : 32
|
|
|
|
|
=========================================================================
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Total REAL time to Xst completion: 3.00 secs
|
2022-02-07 05:21:01 +00:00
|
|
|
Total CPU time to Xst completion: 2.63 secs
|
2021-10-29 10:04:59 +00:00
|
|
|
|
|
|
|
|
-->
|
|
|
|
|
|
2022-02-07 05:21:01 +00:00
|
|
|
Total memory usage is 232880 kilobytes
|
2021-10-29 10:04:59 +00:00
|
|
|
|
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
|
|
|
Number of warnings : 0 ( 0 filtered)
|
|
|
|
|
Number of infos : 0 ( 0 filtered)
|
|
|
|
|
|
