mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-12-01 09:50:00 +00:00
512 lines
19 KiB
Plaintext
512 lines
19 KiB
Plaintext
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Release 14.7 - xst P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 2.00 secs
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Total CPU time to Xst completion: 1.09 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 2.00 secs
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Total CPU time to Xst completion: 1.11 secs
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--> Reading design: WarpSE.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "WarpSE.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "WarpSE"
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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Top Module Name : WarpSE
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : Yes
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../RAM.v" in library work
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Compiling verilog file "../IOBS.v" in library work
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Module <RAM> compiled
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Compiling verilog file "../IOBM.v" in library work
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Module <IOBS> compiled
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Compiling verilog file "../FSB.v" in library work
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Module <IOBM> compiled
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Compiling verilog file "../CS.v" in library work
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Module <FSB> compiled
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Compiling verilog file "../CNT.v" in library work
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Module <CS> compiled
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Compiling verilog file "../WarpSE.v" in library work
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Module <CNT> compiled
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Module <WarpSE> compiled
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No errors in compilation
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Analysis of file <"WarpSE.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <WarpSE> in library <work>.
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Analyzing hierarchy for module <CS> in library <work>.
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Analyzing hierarchy for module <RAM> in library <work>.
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Analyzing hierarchy for module <IOBS> in library <work>.
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Analyzing hierarchy for module <IOBM> in library <work>.
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Analyzing hierarchy for module <CNT> in library <work>.
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Analyzing hierarchy for module <FSB> in library <work>.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <WarpSE>.
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Module <WarpSE> is correct for synthesis.
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Analyzing module <CS> in library <work>.
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Module <CS> is correct for synthesis.
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Analyzing module <RAM> in library <work>.
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Module <RAM> is correct for synthesis.
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Analyzing module <IOBS> in library <work>.
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Module <IOBS> is correct for synthesis.
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Analyzing module <IOBM> in library <work>.
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Module <IOBM> is correct for synthesis.
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Analyzing module <CNT> in library <work>.
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Module <CNT> is correct for synthesis.
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Analyzing module <FSB> in library <work>.
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Module <FSB> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <CS>.
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Related source file is "../CS.v".
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Found 1-bit register for signal <Overlay>.
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Unit <CS> synthesized.
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Synthesizing Unit <RAM>.
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Related source file is "../RAM.v".
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Found finite state machine <FSM_0> for signal <RS>.
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-----------------------------------------------------------------------
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| States | 8 |
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| Transitions | 14 |
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| Inputs | 6 |
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| Outputs | 8 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <nCAS>.
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Found 1-bit register for signal <nOE>.
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Found 1-bit register for signal <RAMReady>.
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Found 1-bit register for signal <DTACKr>.
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Found 1-bit register for signal <RASEL>.
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Found 1-bit register for signal <RASEN>.
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Found 1-bit register for signal <RASrf>.
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Found 1-bit register for signal <RASrr>.
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Found 1-bit register for signal <RefDone>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 8 D-type flip-flop(s).
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Unit <RAM> synthesized.
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Synthesizing Unit <IOBS>.
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Related source file is "../IOBS.v".
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Found finite state machine <FSM_1> for signal <TS>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 10 |
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| Inputs | 5 |
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| Outputs | 5 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <IORDREQ>.
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Found 1-bit register for signal <IOL0>.
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Found 1-bit register for signal <IOWRREQ>.
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Found 1-bit register for signal <IONPReady>.
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Found 1-bit register for signal <IOU0>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <ALE1>.
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Found 1-bit register for signal <nBERR_FSB>.
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Found 1-bit register for signal <Clear1>.
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Found 1-bit register for signal <IOACTr>.
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Found 1-bit register for signal <IODONEr>.
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Found 1-bit register for signal <IOL1>.
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Found 1-bit register for signal <IORW1>.
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Found 1-bit register for signal <IOU1>.
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Found 1-bit register for signal <Load1>.
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Found 1-bit register for signal <Sent>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 10 D-type flip-flop(s).
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Unit <IOBS> synthesized.
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Synthesizing Unit <IOBM>.
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Related source file is "../IOBM.v".
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Found finite state machine <FSM_2> for signal <IOS>.
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-----------------------------------------------------------------------
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| States | 7 |
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| Transitions | 13 |
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| Inputs | 5 |
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| Outputs | 7 |
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| Clock | C16M (rising_edge) |
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| Power Up State | 000 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <IOBERR>.
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Found 1-bit register for signal <nASout>.
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Found 1-bit register for signal <IOACT>.
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Found 1-bit register for signal <IODONE>.
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Found 1-bit register for signal <nLDS>.
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Found 1-bit register for signal <nUDS>.
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Found 1-bit register for signal <nDinLE>.
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Found 1-bit register for signal <ALE0>.
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Found 1-bit register for signal <nVMA>.
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Found 1-bit register for signal <C8Mr>.
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Found 1-bit register for signal <DoutOE>.
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Found 1-bit register for signal <Er>.
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Found 4-bit up counter for signal <ES>.
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Found 1-bit register for signal <IORDREQr>.
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Found 1-bit register for signal <IOS0>.
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Found 1-bit register for signal <IOWRREQr>.
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Found 1-bit register for signal <VPAr>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 Counter(s).
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inferred 15 D-type flip-flop(s).
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Unit <IOBM> synthesized.
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Synthesizing Unit <CNT>.
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Related source file is "../CNT.v".
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Found finite state machine <FSM_3> for signal <IS>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 8 |
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| Inputs | 2 |
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| Outputs | 4 |
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| Clock | CLK (rising_edge) |
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| Power Up State | 00 |
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| Encoding | automatic |
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| Implementation | automatic |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <RefUrg>.
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Found 1-bit register for signal <RefReq>.
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Found 1-bit register for signal <nBR_IOB>.
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Found 1-bit register for signal <IOQoSEN>.
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Found 1-bit register for signal <nRESout>.
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Found 1-bit register for signal <AoutOE>.
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Found 1-bit register for signal <MCKE>.
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Found 2-bit register for signal <C8Mr>.
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Found 2-bit register for signal <Er>.
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Found 3-bit up counter for signal <IOQS>.
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Found 12-bit up counter for signal <LTimer>.
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Found 1-bit register for signal <LTimerTC>.
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Found 1-bit register for signal <nIPL2r>.
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Found 1-bit register for signal <nRESr>.
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Found 1-bit register for signal <QoSCSr>.
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Found 4-bit up counter for signal <Timer>.
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Found 1-bit register for signal <TimerTC>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 3 Counter(s).
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inferred 12 D-type flip-flop(s).
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Unit <CNT> synthesized.
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Synthesizing Unit <FSB>.
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Related source file is "../FSB.v".
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Found 1-bit register for signal <nVPA>.
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Found 1-bit register for signal <BACTr>.
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Found 1-bit register for signal <nDTACK>.
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Found 1-bit register for signal <MCKE>.
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Found 1-bit register for signal <ASrf>.
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Summary:
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inferred 5 D-type flip-flop(s).
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Unit <FSB> synthesized.
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Synthesizing Unit <WarpSE>.
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Related source file is "../WarpSE.v".
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WARNING:Xst:647 - Input <nBG_IOB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input <DBG> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 1-bit tristate buffer for signal <nAS_IOB>.
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Found 1-bit tristate buffer for signal <nLDS_IOB>.
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Found 1-bit tristate buffer for signal <nRES>.
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Found 1-bit tristate buffer for signal <nUDS_IOB>.
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Found 1-bit tristate buffer for signal <nVMA_IOB>.
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Summary:
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inferred 5 Tristate(s).
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Unit <WarpSE> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Counters : 4
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12-bit up counter : 1
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3-bit up counter : 1
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4-bit up counter : 2
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# Registers : 61
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1-bit register : 59
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2-bit register : 2
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# Tristates : 5
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1-bit tristate buffer : 5
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_3> for best encoding.
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Optimizing FSM <cnt/IS/FSM> on signal <IS[1:2]> with johnson encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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01 | 01
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10 | 11
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11 | 10
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-------------------
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Analyzing FSM <FSM_2> for best encoding.
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Optimizing FSM <iobm/IOS/FSM> on signal <IOS[1:7]> with one-hot encoding.
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-------------------
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State | Encoding
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-------------------
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000 | 0000001
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010 | 0000010
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011 | 0000100
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100 | 0001000
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101 | 0010000
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110 | 0100000
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111 | 1000000
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-------------------
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Analyzing FSM <FSM_1> for best encoding.
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Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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11 | 01
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10 | 11
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01 | 10
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-------------------
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <ram/RS/FSM> on signal <RS[1:8]> with one-hot encoding.
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-------------------
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State | Encoding
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-------------------
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000 | 00000001
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100 | 00000010
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001 | 00000100
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010 | 00001000
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011 | 00010000
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101 | 00100000
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110 | 01000000
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111 | 10000000
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-------------------
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 4
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# Counters : 4
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12-bit up counter : 1
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3-bit up counter : 1
|
||
|
|
4-bit up counter : 2
|
||
|
|
# Registers : 50
|
||
|
|
Flip-Flops : 50
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Low Level Synthesis *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Optimizing unit <WarpSE> ...
|
||
|
|
|
||
|
|
Optimizing unit <CS> ...
|
||
|
|
|
||
|
|
Optimizing unit <RAM> ...
|
||
|
|
implementation constraint: INIT=s : RS_FSM_FFd8
|
||
|
|
implementation constraint: INIT=r : RASEL
|
||
|
|
implementation constraint: INIT=r : RASrr
|
||
|
|
implementation constraint: INIT=r : RASEN
|
||
|
|
implementation constraint: INIT=r : RS_FSM_FFd1
|
||
|
|
implementation constraint: INIT=r : RS_FSM_FFd2
|
||
|
|
implementation constraint: INIT=r : RS_FSM_FFd3
|
||
|
|
implementation constraint: INIT=r : RS_FSM_FFd4
|
||
|
|
implementation constraint: INIT=r : RS_FSM_FFd5
|
||
|
|
implementation constraint: INIT=r : RS_FSM_FFd6
|
||
|
|
implementation constraint: INIT=r : RS_FSM_FFd7
|
||
|
|
implementation constraint: INIT=r : RASrf
|
||
|
|
|
||
|
|
Optimizing unit <IOBS> ...
|
||
|
|
implementation constraint: INIT=r : IOACTr
|
||
|
|
implementation constraint: INIT=r : TS_FSM_FFd2
|
||
|
|
implementation constraint: INIT=r : Sent
|
||
|
|
implementation constraint: INIT=r : TS_FSM_FFd1
|
||
|
|
|
||
|
|
Optimizing unit <FSB> ...
|
||
|
|
implementation constraint: INIT=r : ASrf
|
||
|
|
|
||
|
|
Optimizing unit <IOBM> ...
|
||
|
|
implementation constraint: INIT=s : IOS_FSM_FFd7
|
||
|
|
implementation constraint: INIT=r : DoutOE
|
||
|
|
implementation constraint: INIT=r : IOS_FSM_FFd6
|
||
|
|
implementation constraint: INIT=r : IOS_FSM_FFd1
|
||
|
|
implementation constraint: INIT=r : IOS_FSM_FFd2
|
||
|
|
implementation constraint: INIT=r : IOS_FSM_FFd3
|
||
|
|
implementation constraint: INIT=r : IOS_FSM_FFd4
|
||
|
|
implementation constraint: INIT=r : IOS_FSM_FFd5
|
||
|
|
|
||
|
|
Optimizing unit <CNT> ...
|
||
|
|
implementation constraint: INIT=r : Timer_3
|
||
|
|
implementation constraint: INIT=r : Timer_0
|
||
|
|
implementation constraint: INIT=r : Timer_1
|
||
|
|
implementation constraint: INIT=r : Timer_2
|
||
|
|
implementation constraint: INIT=r : IS_FSM_FFd2
|
||
|
|
implementation constraint: INIT=r : IS_FSM_FFd1
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Partition Report *
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
Partition Implementation Status
|
||
|
|
-------------------------------
|
||
|
|
|
||
|
|
No Partitions were found in this design.
|
||
|
|
|
||
|
|
-------------------------------
|
||
|
|
|
||
|
|
=========================================================================
|
||
|
|
* Final Report *
|
||
|
|
=========================================================================
|
||
|
|
Final Results
|
||
|
|
RTL Top Level Output File Name : WarpSE.ngr
|
||
|
|
Top Level Output File Name : WarpSE
|
||
|
|
Output Format : NGC
|
||
|
|
Optimization Goal : Speed
|
||
|
|
Keep Hierarchy : Yes
|
||
|
|
Target Technology : XC9500XL CPLDs
|
||
|
|
Macro Preserve : YES
|
||
|
|
XOR Preserve : YES
|
||
|
|
Clock Enable : YES
|
||
|
|
wysiwyg : NO
|
||
|
|
|
||
|
|
Design Statistics
|
||
|
|
# IOs : 79
|
||
|
|
|
||
|
|
Cell Usage :
|
||
|
|
# BELS : 630
|
||
|
|
# AND2 : 194
|
||
|
|
# AND3 : 32
|
||
|
|
# AND4 : 10
|
||
|
|
# AND5 : 2
|
||
|
|
# AND7 : 1
|
||
|
|
# AND8 : 2
|
||
|
|
# GND : 6
|
||
|
|
# INV : 244
|
||
|
|
# OR2 : 102
|
||
|
|
# OR3 : 14
|
||
|
|
# OR4 : 4
|
||
|
|
# XOR2 : 19
|
||
|
|
# FlipFlops/Latches : 105
|
||
|
|
# FD : 68
|
||
|
|
# FDC : 2
|
||
|
|
# FDCE : 34
|
||
|
|
# FDP : 1
|
||
|
|
# IO Buffers : 72
|
||
|
|
# IBUF : 35
|
||
|
|
# IOBUFE : 1
|
||
|
|
# OBUF : 32
|
||
|
|
# OBUFE : 4
|
||
|
|
=========================================================================
|
||
|
|
|
||
|
|
|
||
|
|
Total REAL time to Xst completion: 54.00 secs
|
||
|
|
Total CPU time to Xst completion: 53.17 secs
|
||
|
|
|
||
|
|
-->
|
||
|
|
|
||
|
|
Total memory usage is 237664 kilobytes
|
||
|
|
|
||
|
|
Number of errors : 0 ( 0 filtered)
|
||
|
|
Number of warnings : 2 ( 0 filtered)
|
||
|
|
Number of infos : 0 ( 0 filtered)
|
||
|
|
|