mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-29 12:49:33 +00:00
234 lines
9.5 KiB
Modula-2
234 lines
9.5 KiB
Modula-2
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MODEL
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MODEL_VERSION "v1998.8";
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DESIGN "WarpSE";
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/* port names and type */
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INPUT S:PIN7 = A_FSB<9>;
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INPUT S:PIN6 = A_FSB<8>;
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INPUT S:PIN13 = A_FSB<15>;
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INPUT S:PIN12 = A_FSB<14>;
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INPUT S:PIN11 = A_FSB<13>;
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INPUT S:PIN10 = A_FSB<12>;
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INPUT S:PIN9 = A_FSB<11>;
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INPUT S:PIN8 = A_FSB<10>;
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INPUT S:PIN24 = A_FSB<23>;
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INPUT S:PIN20 = A_FSB<22>;
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INPUT S:PIN19 = A_FSB<21>;
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INPUT S:PIN18 = A_FSB<20>;
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INPUT S:PIN17 = A_FSB<19>;
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INPUT S:PIN16 = A_FSB<18>;
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INPUT S:PIN15 = A_FSB<17>;
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INPUT S:PIN14 = A_FSB<16>;
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INPUT S:PIN22 = CLK2X_IOB;
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INPUT S:PIN27 = CLK_FSB;
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INPUT S:PIN32 = nAS_FSB;
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INPUT S:PIN29 = nWE_FSB;
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INPUT S:PIN60 = SW<1>;
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INPUT S:PIN91 = nRES;
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INPUT S:PIN30 = nLDS_FSB;
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INPUT S:PIN33 = nUDS_FSB;
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INPUT S:PIN23 = CLK_IOB;
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INPUT S:PIN76 = nBERR_IOB;
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INPUT S:PIN25 = E_IOB;
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INPUT S:PIN92 = nIPL2;
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INPUT S:PIN73 = nBG_IOB;
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INPUT S:PIN78 = nDTACK_IOB;
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INPUT S:PIN77 = nVPA_IOB;
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INPUT S:PIN94 = A_FSB<1>;
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INPUT S:PIN95 = A_FSB<2>;
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INPUT S:PIN96 = A_FSB<3>;
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INPUT S:PIN97 = A_FSB<4>;
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INPUT S:PIN2 = A_FSB<5>;
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INPUT S:PIN3 = A_FSB<6>;
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INPUT S:PIN4 = A_FSB<7>;
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INPUT S:PIN61 = SW<0>;
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TRIOUT S:PIN74 = nVMA_IOB;
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TRIOUT S:PIN81 = nAS_IOB;
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TRIOUT S:PIN79 = nLDS_IOB;
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TRIOUT S:PIN80 = nUDS_IOB;
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OUTPUT S:PIN28 = nDTACK_FSB;
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OUTPUT S:PIN53 = RA<0>;
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OUTPUT S:PIN50 = RA<1>;
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OUTPUT S:PIN43 = RA<2>;
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OUTPUT S:PIN41 = RA<3>;
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OUTPUT S:PIN40 = RA<4>;
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OUTPUT S:PIN42 = RA<5>;
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OUTPUT S:PIN46 = RA<6>;
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OUTPUT S:PIN52 = RA<7>;
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OUTPUT S:PIN54 = RA<8>;
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OUTPUT S:PIN56 = RA<9>;
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OUTPUT S:PIN70 = nBERR_FSB;
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OUTPUT S:PIN37 = nOE;
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OUTPUT S:PIN34 = nROMWE;
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OUTPUT S:PIN93 = nVPA_FSB;
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OUTPUT S:PIN85 = nADoutLE0;
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OUTPUT S:PIN36 = nCAS;
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OUTPUT S:PIN86 = nDinLE;
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OUTPUT S:PIN90 = nDinOE;
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OUTPUT S:PIN89 = nDoutOE;
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OUTPUT S:PIN64 = nRAS;
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OUTPUT S:PIN63 = RA<11>;
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OUTPUT S:PIN55 = RA<10>;
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OUTPUT S:PIN59 = CLK20EN;
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OUTPUT S:PIN58 = CLK25EN;
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OUTPUT S:PIN72 = nBR_IOB;
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OUTPUT S:PIN82 = nADoutLE1;
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OUTPUT S:PIN87 = nAoutOE;
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OUTPUT S:PIN65 = nRAMLWE;
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OUTPUT S:PIN66 = nRAMUWE;
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OUTPUT S:PIN35 = nROMCS;
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/* timing arc definitions */
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SW<0>_CLK20EN_delay: DELAY SW<0> CLK20EN;
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SW<0>_CLK25EN_delay: DELAY SW<0> CLK25EN;
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A_FSB<1>_RA<0>_delay: DELAY A_FSB<1> RA<0>;
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A_FSB<10>_RA<0>_delay: DELAY A_FSB<10> RA<0>;
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A_FSB<21>_RA<10>_delay: DELAY A_FSB<21> RA<10>;
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A_FSB<19>_RA<11>_delay: DELAY A_FSB<19> RA<11>;
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A_FSB<11>_RA<1>_delay: DELAY A_FSB<11> RA<1>;
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A_FSB<2>_RA<1>_delay: DELAY A_FSB<2> RA<1>;
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A_FSB<3>_RA<2>_delay: DELAY A_FSB<3> RA<2>;
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A_FSB<12>_RA<2>_delay: DELAY A_FSB<12> RA<2>;
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A_FSB<4>_RA<3>_delay: DELAY A_FSB<4> RA<3>;
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A_FSB<13>_RA<3>_delay: DELAY A_FSB<13> RA<3>;
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A_FSB<5>_RA<4>_delay: DELAY A_FSB<5> RA<4>;
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A_FSB<14>_RA<4>_delay: DELAY A_FSB<14> RA<4>;
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A_FSB<6>_RA<5>_delay: DELAY A_FSB<6> RA<5>;
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A_FSB<15>_RA<5>_delay: DELAY A_FSB<15> RA<5>;
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A_FSB<7>_RA<6>_delay: DELAY A_FSB<7> RA<6>;
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A_FSB<16>_RA<6>_delay: DELAY A_FSB<16> RA<6>;
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A_FSB<17>_RA<7>_delay: DELAY A_FSB<17> RA<7>;
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A_FSB<8>_RA<7>_delay: DELAY A_FSB<8> RA<7>;
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A_FSB<21>_RA<8>_delay: DELAY A_FSB<21> RA<8>;
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A_FSB<9>_RA<8>_delay: DELAY A_FSB<9> RA<8>;
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A_FSB<23>_RA<8>_delay: DELAY A_FSB<23> RA<8>;
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A_FSB<22>_RA<8>_delay: DELAY A_FSB<22> RA<8>;
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A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
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A_FSB<20>_RA<9>_delay: DELAY A_FSB<20> RA<9>;
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A_FSB<19>_RA<9>_delay: DELAY A_FSB<19> RA<9>;
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nAS_FSB_nBERR_FSB_delay: DELAY nAS_FSB nBERR_FSB;
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A_FSB<20>_nBERR_FSB_delay: DELAY A_FSB<20> nBERR_FSB;
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A_FSB<22>_nBERR_FSB_delay: DELAY A_FSB<22> nBERR_FSB;
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A_FSB<23>_nBERR_FSB_delay: DELAY A_FSB<23> nBERR_FSB;
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A_FSB<21>_nBERR_FSB_delay: DELAY A_FSB<21> nBERR_FSB;
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A_FSB<20>_nDinOE_delay: DELAY A_FSB<20> nDinOE;
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A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
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A_FSB<22>_nDinOE_delay: DELAY A_FSB<22> nDinOE;
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A_FSB<21>_nDinOE_delay: DELAY A_FSB<21> nDinOE;
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nAS_FSB_nDinOE_delay: DELAY nAS_FSB nDinOE;
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nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
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SW<1>_nDinOE_delay: DELAY SW<1> nDinOE;
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nAS_FSB_nOE_delay: DELAY nAS_FSB nOE;
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nWE_FSB_nOE_delay: DELAY nWE_FSB nOE;
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nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
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nWE_FSB_nRAMLWE_delay: DELAY nWE_FSB nRAMLWE;
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nAS_FSB_nRAMLWE_delay: DELAY nAS_FSB nRAMLWE;
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nWE_FSB_nRAMUWE_delay: DELAY nWE_FSB nRAMUWE;
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nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
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nAS_FSB_nRAMUWE_delay: DELAY nAS_FSB nRAMUWE;
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A_FSB<23>_nRAS_delay: DELAY A_FSB<23> nRAS;
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nAS_FSB_nRAS_delay: DELAY nAS_FSB nRAS;
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A_FSB<21>_nRAS_delay: DELAY A_FSB<21> nRAS;
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A_FSB<22>_nRAS_delay: DELAY A_FSB<22> nRAS;
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A_FSB<22>_nROMCS_delay: DELAY A_FSB<22> nROMCS;
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A_FSB<23>_nROMCS_delay: DELAY A_FSB<23> nROMCS;
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SW<1>_nROMCS_delay: DELAY SW<1> nROMCS;
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A_FSB<20>_nROMCS_delay: DELAY A_FSB<20> nROMCS;
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A_FSB<21>_nROMCS_delay: DELAY A_FSB<21> nROMCS;
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nAS_FSB_nROMWE_delay: DELAY nAS_FSB nROMWE;
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nWE_FSB_nROMWE_delay: DELAY nWE_FSB nROMWE;
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nAS_FSB_nVPA_FSB_delay: DELAY nAS_FSB nVPA_FSB;
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CLK_FSB_nDTACK_FSB_delay: DELAY CLK_FSB nDTACK_FSB;
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CLK_FSB_RA<0>_delay: DELAY CLK_FSB RA<0>;
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CLK_FSB_RA<1>_delay: DELAY CLK_FSB RA<1>;
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CLK_FSB_RA<2>_delay: DELAY CLK_FSB RA<2>;
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CLK_FSB_RA<3>_delay: DELAY CLK_FSB RA<3>;
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CLK_FSB_RA<4>_delay: DELAY CLK_FSB RA<4>;
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CLK_FSB_RA<5>_delay: DELAY CLK_FSB RA<5>;
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CLK_FSB_RA<6>_delay: DELAY CLK_FSB RA<6>;
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CLK_FSB_RA<7>_delay: DELAY CLK_FSB RA<7>;
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CLK_FSB_RA<8>_delay: DELAY CLK_FSB RA<8>;
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CLK_FSB_RA<9>_delay: DELAY CLK_FSB RA<9>;
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CLK_FSB_nBERR_FSB_delay: DELAY CLK_FSB nBERR_FSB;
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CLK_FSB_nVPA_FSB_delay: DELAY CLK_FSB nVPA_FSB;
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CLK_FSB_nADoutLE0_delay: DELAY CLK_FSB nADoutLE0;
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CLK_FSB_nCAS_delay: DELAY CLK_FSB nCAS;
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CLK_FSB_nRAS_delay: DELAY CLK_FSB nRAS;
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CLK_FSB_nBR_IOB_delay: DELAY CLK_FSB nBR_IOB;
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CLK_FSB_nADoutLE1_delay: DELAY CLK_FSB nADoutLE1;
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CLK_FSB_nRAMLWE_delay: DELAY CLK_FSB nRAMLWE;
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CLK_FSB_nRAMUWE_delay: DELAY CLK_FSB nRAMUWE;
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CLK_FSB_nROMCS_delay: DELAY CLK_FSB nROMCS;
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CLK2X_IOB_nVMA_IOB_delay: DELAY (ENABLE_HIGH) CLK2X_IOB nVMA_IOB;
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CLK2X_IOB_nAS_IOB_delay: DELAY (ENABLE_HIGH) CLK2X_IOB nAS_IOB;
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CLK2X_IOB_nLDS_IOB_delay: DELAY (ENABLE_HIGH) CLK2X_IOB nLDS_IOB;
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CLK2X_IOB_nUDS_IOB_delay: DELAY (ENABLE_HIGH) CLK2X_IOB nUDS_IOB;
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CLK2X_IOB_nADoutLE0_delay: DELAY CLK2X_IOB nADoutLE0;
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CLK2X_IOB_nDinLE_delay: DELAY CLK2X_IOB nDinLE;
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CLK2X_IOB_nDoutOE_delay: DELAY CLK2X_IOB nDoutOE;
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CLK2X_IOB_nAoutOE_delay: DELAY CLK2X_IOB nAoutOE;
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/* timing check arc definitions */
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E_IOB_CLK_IOB_setup: SETUP(POSEDGE) E_IOB CLK_IOB;
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E_IOB_CLK_IOB_hold: HOLD(POSEDGE) E_IOB CLK_IOB;
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A_FSB<10>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<10> CLK_FSB;
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A_FSB<11>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<11> CLK_FSB;
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A_FSB<12>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<12> CLK_FSB;
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A_FSB<13>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<13> CLK_FSB;
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A_FSB<14>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<14> CLK_FSB;
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A_FSB<15>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<15> CLK_FSB;
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A_FSB<16>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<16> CLK_FSB;
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A_FSB<17>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<17> CLK_FSB;
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A_FSB<18>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<18> CLK_FSB;
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A_FSB<19>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<19> CLK_FSB;
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A_FSB<20>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<20> CLK_FSB;
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A_FSB<21>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<21> CLK_FSB;
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A_FSB<22>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<22> CLK_FSB;
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A_FSB<23>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<23> CLK_FSB;
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A_FSB<8>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<8> CLK_FSB;
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A_FSB<9>_CLK_FSB_setup: SETUP(POSEDGE) A_FSB<9> CLK_FSB;
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SW<1>_CLK_FSB_setup: SETUP(POSEDGE) SW<1> CLK_FSB;
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nAS_FSB_CLK_FSB_setup: SETUP(POSEDGE) nAS_FSB CLK_FSB;
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nIPL2_CLK_FSB_setup: SETUP(POSEDGE) nIPL2 CLK_FSB;
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nLDS_FSB_CLK_FSB_setup: SETUP(POSEDGE) nLDS_FSB CLK_FSB;
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nRES_CLK_FSB_setup: SETUP(POSEDGE) nRES CLK_FSB;
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nUDS_FSB_CLK_FSB_setup: SETUP(POSEDGE) nUDS_FSB CLK_FSB;
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nWE_FSB_CLK_FSB_setup: SETUP(POSEDGE) nWE_FSB CLK_FSB;
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A_FSB<10>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<10> CLK_FSB;
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A_FSB<11>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<11> CLK_FSB;
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A_FSB<12>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<12> CLK_FSB;
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A_FSB<13>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<13> CLK_FSB;
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A_FSB<14>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<14> CLK_FSB;
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A_FSB<15>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<15> CLK_FSB;
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A_FSB<16>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<16> CLK_FSB;
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A_FSB<17>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<17> CLK_FSB;
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A_FSB<18>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<18> CLK_FSB;
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A_FSB<19>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<19> CLK_FSB;
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A_FSB<20>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<20> CLK_FSB;
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A_FSB<21>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<21> CLK_FSB;
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A_FSB<22>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<22> CLK_FSB;
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A_FSB<23>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<23> CLK_FSB;
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A_FSB<8>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<8> CLK_FSB;
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A_FSB<9>_CLK_FSB_hold: HOLD(POSEDGE) A_FSB<9> CLK_FSB;
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SW<1>_CLK_FSB_hold: HOLD(POSEDGE) SW<1> CLK_FSB;
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nAS_FSB_CLK_FSB_hold: HOLD(POSEDGE) nAS_FSB CLK_FSB;
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nIPL2_CLK_FSB_hold: HOLD(POSEDGE) nIPL2 CLK_FSB;
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nLDS_FSB_CLK_FSB_hold: HOLD(POSEDGE) nLDS_FSB CLK_FSB;
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nRES_CLK_FSB_hold: HOLD(POSEDGE) nRES CLK_FSB;
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nUDS_FSB_CLK_FSB_hold: HOLD(POSEDGE) nUDS_FSB CLK_FSB;
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nWE_FSB_CLK_FSB_hold: HOLD(POSEDGE) nWE_FSB CLK_FSB;
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CLK_IOB_CLK2X_IOB_setup: SETUP(POSEDGE) CLK_IOB CLK2X_IOB;
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nBERR_IOB_CLK2X_IOB_setup: SETUP(POSEDGE) nBERR_IOB CLK2X_IOB;
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nBG_IOB_CLK2X_IOB_setup: SETUP(POSEDGE) nBG_IOB CLK2X_IOB;
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nDTACK_IOB_CLK2X_IOB_setup: SETUP(POSEDGE) nDTACK_IOB CLK2X_IOB;
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nRES_CLK2X_IOB_setup: SETUP(POSEDGE) nRES CLK2X_IOB;
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nVPA_IOB_CLK2X_IOB_setup: SETUP(POSEDGE) nVPA_IOB CLK2X_IOB;
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CLK_IOB_CLK2X_IOB_hold: HOLD(POSEDGE) CLK_IOB CLK2X_IOB;
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nBERR_IOB_CLK2X_IOB_hold: HOLD(POSEDGE) nBERR_IOB CLK2X_IOB;
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nBG_IOB_CLK2X_IOB_hold: HOLD(POSEDGE) nBG_IOB CLK2X_IOB;
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nDTACK_IOB_CLK2X_IOB_hold: HOLD(POSEDGE) nDTACK_IOB CLK2X_IOB;
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nRES_CLK2X_IOB_hold: HOLD(POSEDGE) nRES CLK2X_IOB;
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nVPA_IOB_CLK2X_IOB_hold: HOLD(POSEDGE) nVPA_IOB CLK2X_IOB;
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ENDMODEL
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