From 02ab10bb5aa9303a77af699b35accb9b1a99bef5 Mon Sep 17 00:00:00 2001
From: Zane Kaminski <zanekaminski@gmail.com>
Date: Thu, 3 Oct 2024 18:45:35 -0400
Subject: [PATCH] Add CNT area reduction from 0.6e

---
 cpld/CNT.v | 45 +++++++++++++++++++--------------------------
 cpld/CS.v  |  2 +-
 2 files changed, 20 insertions(+), 27 deletions(-)

diff --git a/cpld/CNT.v b/cpld/CNT.v
index 96f8d8b..c8ab7e9 100644
--- a/cpld/CNT.v
+++ b/cpld/CNT.v
@@ -2,7 +2,7 @@ module CNT(
 	/* FSB clock and E clock inputs */
 	input CLK, input C8M, input E,
 	/* Refresh request */
-	output reg RefReq, output reg RefUrg,
+	output reg RefReq, output RefUrg,
 	/* Reset, button */
 	output reg nRESout, input nRESin, input nIPL2, 
 	/* Mac PDS bus master control outputs */
@@ -22,10 +22,6 @@ module CNT(
 	/* C8M clock synchronization */
 	reg [3:0] C8Mr; always @(posedge CLK) C8Mr[3:0] <= { C8Mr[2:0], C8M };
 	
-	/* NMI and reset synchronization */
-	reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
-	reg nRESr; always @(posedge CLK) nRESr <= nRESin;
-	
 	/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
     *	Refresh timer sequence
 	 * |  Timer  | RefReq |   RefUrg  |
@@ -38,46 +34,50 @@ module CNT(
 	 * | 5  0101 |   1    |     0     |
 	 * | 6  0110 |   1    |     0     |
 	 * | 7  0111 |   1    |     0     |
-	 * | 8  1000 |   1    |     0     |
+	 * | 8  1000 |   1    |     1     |
 	 * | 9  1001 |   1    |     1     |
 	 * | 10 1010 |   1    |     1     |
 	 * back to timer==0
 	 */
 	reg [3:0] Timer = 0;
 	wire TimerTC = Timer==10;
+	assign RefUrg = Timer[3];
 	reg TimerTick;
 	always @(posedge CLK) begin
 		if (EFall) begin
 			if (TimerTC) Timer <= 0;
 			else Timer <= Timer+1;
-			RefUrg <= Timer==8 || Timer==9;
 			RefReq <= Timer!=10;
 		end
 	end
 	always @(posedge CLK) TimerTick <= EFall && TimerTC;
 
-	/* QoS select latch */
-	reg QoSCSr;
-	always @(posedge CLK) QoSCSr <= (BACT && (QoSCS || SndQoSCS)) || !nRESr;
+	/* QoS select latches */
+	reg QoSCSr, SndQoSCSr;
+	always @(posedge CLK) QoSCSr <= (BACT && QoSCS) || !nRESin;
+	always @(posedge CLK) SndQoSCSr <= BACT && SndQoSCS;
+
+	/* Wait state timer */
+	reg [3:0] Wait;
+	always @(posedge CLK) begin
+		if (!BACT) Wait <= 0;
+		else Wait <= Wait+1;
+	end
 	
 	/* QoS timer
 	 * In the absence of a QoS trigger, QS==0.
 	 * When Qos triggered, QS is set to 1 and counts 1, 2, 3, 0.
 	 * While QS!=0, QoS is enabled.
-	 * QoS enable period is 28.124 us - 42.240 us */
+	 * QoS enable period is 196.588 us - 210.630 us */
 	reg [3:0] QS;
 	always @(posedge CLK) begin
-		if (QoSCSr) QS <= 15;
+		if (SndQoSCSr || QoSCSr) QS <= 15;
 		else if (QS==0) QS <= 0;
 		else if (TimerTick) QS <= QS-1;
 	end
 
 	/* QoS enable control */
 	always @(posedge CLK) if (!BACT) QoSEN <= QS!=0;
-
-	/* Sound QoS select latch */
-	reg SndQoSCSr;
-	always @(posedge CLK) SndQoSCSr <= BACT && SndQoSCS;
 	
 	/* Sound QoS timer */
 	reg [1:0] SndQS;
@@ -88,17 +88,10 @@ module CNT(
 		else if (TimerTick) SndQS <= SndQS-1;
 	end
 
-	/* Wait state timer */
-	reg [3:0] Wait;
-	always @(posedge CLK) begin
-		if (!BACT) Wait <= 0;
-		else Wait <= Wait+1;
-	end
-
 	/* Sound QoS ready control */
 	always @(posedge CLK) begin
 		if (!BACT) SndQoSReady <= SndQS==0;
-		else if (QoSCSr && !SndQoSCSr) SndQoSReady <= 1;
+		else if (QoSCSr) SndQoSReady <= 1;
 		else if (Wait==15) SndQoSReady <= 1;
 	end
 	
@@ -124,7 +117,7 @@ module CNT(
 		else case (IS[1:0])
 			0: if (LTimerTick) IS <= 1;
 			1: if (LTimerTick) IS <= 2;
-			2: if (LTimerTick && nIPL2r) IS <= 3;
+			2: if (LTimerTick && nIPL2) IS[0] <= 1;
 			3: IS <= 3;
 		endcase
 	end
@@ -139,7 +132,7 @@ module CNT(
 			end 2: begin
 				AoutOE <= 0;
 				nRESout <= 0;
-				if (!nIPL2r) nBR_IOB <= 1; // Disable bus request if NMI pressed
+				if (!nIPL2) nBR_IOB <= 1; // Disable bus request if NMI pressed
 			end 3: begin
 				AoutOE <= !nBR_IOB;
 				if (LTimerTick) nRESout <= 1; // Release reset after a while
diff --git a/cpld/CS.v b/cpld/CS.v
index b6707d4..863365e 100644
--- a/cpld/CS.v
+++ b/cpld/CS.v
@@ -49,7 +49,7 @@ module CS(
 	wire SndRAMCSWR = VidRAMCSWR64k && (
 		((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
 		((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
-	assign QoSCS = IACKCS || VIACS || IWMCS || SCCCS || SCSICS || SndRAMCSWR;
+	assign QoSCS = IACKCS || VIACS || IWMCS || SCCCS || SCSICS;
 	assign SndQoSCS = SndRAMCSWR;
 
 	/* Select signals - IOB domain */