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Update RAM module inputs/outputs

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This commit is contained in:
Zane Kaminski 2024-09-21 21:52:46 -04:00
parent 51d95a8f7d
commit 0d51f78cf7
2 changed files with 9 additions and 5 deletions
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6
cpld/RAM.v
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@ -5,7 +5,9 @@ module RAM(
/* AS cycle detection */
input BACT, input BACTr,
/* Select and ready signals */
input RAMCS, input RAMCS0X, input ROMCS, output reg RAMReady,
input RAMCS, input RAMCS0X, input ROMCS, input ROMCS4X,
/* RAM ready output */
output reg RAMReady,
/* Refresh Counter Interface */
input RefReqIn, input RefUrgIn,
/* DRAM and NOR flash interface */
@ -39,7 +41,7 @@ module RAM(
/* ROM control signals */
assign nROMOE = !(ROMCS && !nAS && nWE);
assign nROMWE = !(ROMCS && !nAS && !nWE);
assign nROMWE = !(ROMCS4X && !nAS && !nWE);
/* RAM address mux (and ROM address on RA8) */
// RA11 doesn't do anything so both should be identical.

8
cpld/WarpSE.v
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@ -86,10 +86,12 @@ module WarpSE(
/* MC68HC000 interface */
FCLK, A_FSB[21:1], nWE_FSB,
nAS_FSB, nLDS_FSB, nUDS_FSB, nDTACK_FSB,
/* AS cycle detection */
/* AS cycle detection inputs */
BACT, BACTr,
/* Select and ready signals */
RAMCS, RAMCS0X, ROMCS, RAMReady,
/* RAM and ROM select inputs */
RAMCS, RAMCS0X, ROMCS, ROMCS4X,
/* RAM ready output */
RAMReady,
/* Refresh Counter Interface */
RefReq, RefUrg,
/* DRAM and NOR flash interface */