diff --git a/cpld/CNT.v b/cpld/CNT.v
index d39c704..1e48f5c 100644
--- a/cpld/CNT.v
+++ b/cpld/CNT.v
@@ -1,6 +1,6 @@
 module CNT(
 	/* FSB clock and E clock inputs */
-	input CLK, input C8M, input E,
+	input CLK, input E,
 	/* Refresh request */
 	output reg RefReq, output reg RefUrg,
 	/* Reset, button */
@@ -9,21 +9,13 @@ module CNT(
 	output reg AoutOE, output reg nBR_IOB,
 	/* QoS control */
 	input BACT,
-	input BACTr,
-	input IOQoSCS,
-	input SndQoSCS,
-	input IACKCS,
-	output reg IOQoSEN,
-	output reg MCKE);
+	input QoSCS,
+	output reg QoSEN);
 	
 	/* E clock synchronization */
 	reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E };
 	wire EFall = Er[1] && !Er[0];
 	
-	/* C8M clock synchronization */
-	reg [1:0] C8Mr; always @(posedge CLK) C8Mr[1:0] <= { C8Mr[0], C8M };
-	wire C8MFall = C8Mr[1] && !C8Mr[0];
-	
 	/* NMI and reset synchronization */
 	reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
 	reg nRESr; always @(posedge CLK) nRESr <= nRESin;
@@ -60,39 +52,36 @@ module CNT(
 		end
 	end
 	
-	/* During init (IS!=3) long timer counts from 0 to 3072.
-	 * 3073 states == 43.151 ms */
+	/* During init (IS!=3) long timer counts from 0 to 4095.
+	 * 4096 states == 57.516 ms */
 	reg [11:0] LTimer;
-	wire LTimerTC = LTimer[11:10]==2'b11;
+	reg LTimerTC;
 	always @(posedge CLK) begin
-		if (EFall && TimerTC) LTimer <= LTimer+1;
+		if (EFall && TimerTC) begin
+			LTimer <= LTimer+1;
+			LTimerTC <= LTimer[11:0]==12'hFFE;
+		end
 	end
 
-	/* QoS select registers */
-	reg IOQoSCSr;
-	always @(posedge CLK) IOQoSCSr <= (BACT && (IOQoSCS || SndQoSCS || IACKCS)) || !nRESr;
+	/* QoS select latch */
+	reg QoSCSr;
+	always @(posedge CLK) if (BACT) QoSCSr <= QoSCS;
 	
-	/* I/O QoS timer */
-	reg [3:0] IOQS;
+	/* QoS timer
+	 * In the absence of a QoS trigger, QS==0.
+	 * When Qos triggered, QS is set to 1 and counts 1, 2, 3, 0.
+	 * While QS!=0, QoS is enabled.
+	 * QoS enable period is 28.124 us - 42.240 us */
+	reg [1:0] QS;
 	always @(posedge CLK) begin
-		if (IOQoSCSr) IOQS <= 4'hF;
-		else if (IOQS==0) IOQS <= 0;
-		else if (EFall && TimerTC) IOQS <= IOQS-1;
+		if (!nRESr || QoSCSr) QS[1:0] <= 1;
+		else if (QS==0) QS[1:0] <= 0;
+		else if (EFall && TimerTC) QS[1:0] <= QS+1;
 	end
 
-	/* I/O QoS enable */
-	always @(posedge CLK) if (!BACT) IOQoSEN <= IOQS!=0;
+	/* QoS enable control */
+	always @(posedge CLK) if (!BACT) QoSEN <= QoSCSr || QS!=0;
 
-	/* MC68K clock enable */
-	always @(posedge CLK) MCKE <= 1;//BACT || BACTr || !IOQoSEN || C8MFall;
-	
-	/* */
-	reg LookReset;
-	always @(posedge CLK) begin
-		if (!nRESout) LookReset <= 0;
-		else if (EFall) LookReset <= 1;
-	end
-	
 	/* Startup sequence state control */
 	wire ISTC = EFall && TimerTC && LTimerTC;
 	always @(posedge CLK) begin
@@ -113,8 +102,9 @@ module CNT(
 				if (ISTC) IS <= 3;
 			end 3: begin
 				nRESout <= 1; // Release reset
-				if (LookReset && !nRESr) IS <= 0;
+				IS <= 3;
 			end
 		endcase
 	end
+
 endmodule
diff --git a/cpld/CS.v b/cpld/CS.v
index 47bbb75..549a4a1 100644
--- a/cpld/CS.v
+++ b/cpld/CS.v
@@ -4,12 +4,11 @@ module CS(
 	/* AS cycle detection */
 	input BACT,
 	/* QoS enable input */
-	input IOQoSEN,
+	input QoSEN,
 	/* Device select outputs */
-	output IOCS, output IORealCS, output IOPWCS, output IACKCS,
+	output IOCS, output IORealCS, output IOPWCS, output IACS,
 	output ROMCS, output ROMCS4X,
-	output RAMCS, output RAMCS0X,
-	output IOQoSCS, output SndQoSCS);
+	output RAMCS, output RAMCS0X, output QoSCS);
 
 	/* Overlay control */
 	reg Overlay;
@@ -19,7 +18,7 @@ module CS(
 	end
 
 	/* I/O select signals */
-	assign IACKCS = A[23:20]==4'hF;
+	wire IACKCS = A[23:20]==4'hF;
 	wire VIACS = A[23:20]==4'hE;
 	wire IWMCS = A[23:20]==4'hD;
 	wire SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
@@ -46,13 +45,13 @@ module CS(
 		//A[15:12]==4'hD || // 4096 bytes video
 		//A[15:12]==4'hE || // 4096 bytes video
 		//A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
-	assign SndQoSCS = VidRAMCSWR64k && (
+	wire SndRAMCSWR = VidRAMCSWR64k && (
 		((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
 		((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
-	assign IOQoSCS =  IWMCS || VIACS || SCCCS || SCSICS;
+	assign QoSCS = IACKCS || VIACS || IWMCS || SCCCS || SCSICS || SndRAMCSWR;
 
 	/* Select signals - IOB domain */
-	assign IACKCS = A[23:20]==4'hF; // IACK
+	assign IACS = A[23:20]==4'hF; // IACK
 	assign IORealCS =
 		A[23:20]==4'hF || // IACK
 		A[23:20]==4'hE || // VIA
@@ -65,6 +64,6 @@ module CS(
 		A[23:20]==4'h7 || // empty (expansion RAM)
 		A[23:20]==4'h6 || // empty (expansion RAM)
 		A[23:20]==4'h5;   // SCSI
-	assign IOCS = IORealCS || VidRAMCSWR || IOQoSEN;
-	assign IOPWCS = VidRAMCSWR64k && !IOQoSEN; // Posted write to video RAM only when QoS disabled
+	assign IOCS = IORealCS || VidRAMCSWR || QoSEN;
+	assign IOPWCS = VidRAMCSWR64k && !QoSEN; // Posted write to video RAM only when QoS disabled
 endmodule
diff --git a/cpld/FSB.v b/cpld/FSB.v
index e7b9427..d932e5b 100644
--- a/cpld/FSB.v
+++ b/cpld/FSB.v
@@ -1,37 +1,31 @@
 module FSB(
 	/* MC68HC000 interface */
 	input FCLK, input nAS, output reg nDTACK, output reg nVPA,
-	/* MC68HC000 clock enable */
-	input MCKEi, output reg MCKE,
 	/* AS cycle detection */
 	output BACT, output reg BACTr,
 	/* Ready inputs */
 	input ROMCS,
 	input RAMCS, input RAMReady,
 	input IOPWCS, input IOPWReady, input IONPReady,
-	input IOQoSEN,
+	input QoSEN,
 	/* Interrupt acknowledge select */
-	input IACKCS);
-
-	/* MC68k clock enable */
-	always @(negedge FCLK) MCKE <= MCKEi;
+	input IACS);
 
 	/* AS cycle detection */
 	reg ASrf = 0;
 	always @(negedge FCLK) begin ASrf <= !nAS; end
-	assign BACTu = !nAS || ASrf;
-	assign BACT = BACTu && MCKE;
+	assign BACT = !nAS || ASrf; // BACT - bus active
 	always @(posedge FCLK) BACTr <= BACT;
 
 	/* DTACK/VPA control */
-	wire Ready = (RAMCS && !IOQoSEN && RAMReady && !IOPWCS) ||
-                 (RAMCS && !IOQoSEN && RAMReady &&  IOPWCS && IOPWReady) ||
-                 (ROMCS && !IOQoSEN) ||
+	wire Ready = (RAMCS && !QoSEN && RAMReady && !IOPWCS) ||
+                 (RAMCS && !QoSEN && RAMReady &&  IOPWCS && IOPWReady) ||
+                 (ROMCS && !QoSEN) ||
                  (IONPReady);
-	always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACKCS);
+	always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
 	always @(posedge FCLK, posedge nAS) begin
 		if (nAS) nVPA <= 1;
-		else nVPA <= !(Ready && BACT && IACKCS);
+		else nVPA <= !(Ready && BACT && IACS);
 	end
 	
 endmodule
diff --git a/cpld/IOBM.v b/cpld/IOBM.v
index 75e936f..331f2d8 100644
--- a/cpld/IOBM.v
+++ b/cpld/IOBM.v
@@ -1,19 +1,21 @@
 module IOBM(
 	/* PDS interface */
 	input C16M, input C8M, input E,
-	output reg nAS, output reg nLDS, output reg nUDS, output reg RnW, output reg nVMA,
+	output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
 	input nDTACK, input nVPA, input nBERR, input nRES,
 	/* PDS address and data latch control */
 	input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
 	/* IO bus slave port interface */
-	input IOREQ, input IORW, input IOLDS, input IOUDS,
+	input IORDREQ, input IOWRREQ, input IOLDS, input IOUDS,
 	output reg IOACT, output reg IODONE, output reg IOBERR);
 
 	/* C8M clock registration */
 	reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
 
 	/* I/O request input synchronization */
-	reg IOREQr; always @(posedge C16M) IOREQr <= IOREQ;
+	reg IORDREQr; always @(posedge C16M) IORDREQr <= IORDREQ;
+	reg IOWRREQr; always @(posedge C16M) IOWRREQr <= IOWRREQ;
+	wire IOREQr = IORDREQr || IOWRREQr;
 
 	/* VPA synchronization */
 	reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
@@ -37,8 +39,8 @@ module IOBM(
 	end
 	
 	/* DTACK and BERR synchronization */
-	always @(negedge C8M, posedge nAS) begin
-		if (nAS) begin
+	always @(negedge C8M, posedge nASout) begin
+		if (nASout) begin
 			IODONE <= 0;
 			IOBERR <= 0;
 		end else begin
@@ -50,8 +52,8 @@ module IOBM(
 	/* I/O bus state */
 	reg [2:0] IOS = 0;
 	reg IOS0;
-	always @(posedge C16M) case (IOS[2:0])
-		3'h0: begin
+	always @(posedge C16M) begin
+		if (IOS==0) begin
 			if (IOREQr && !C8Mr && AoutOE) begin // "IOS1"
 				IOS <= 2;
 				IOS0 <= 0;
@@ -59,24 +61,24 @@ module IOBM(
 				IOS <= 0;
 				IOS0 <= 1;
 			end
-			IOACT <= IOREQr;
-			ALE0 <= IOREQr;
-		end 3'h2: begin
+			IOACT <= IOREQr && AoutOE;
+			ALE0 <= IOREQr && AoutOE;
+		end else if (IOS==2) begin
 			IOS <= 3;
 			IOS0 <= 0;
 			IOACT <= 1;
 			ALE0 <= 1;
-		end 3'h3: begin
+		end else if (IOS==3) begin
 			IOS <= 4;
 			IOS0 <= 0;
 			IOACT <= 1;
 			ALE0 <= 1;
-		end 3'h4: begin
+		end else if (IOS==4) begin
 			IOS <= 5;
 			IOS0 <= 0;
 			IOACT <= 1;
 			ALE0 <= 1;
-		end 3'h5: begin
+		end else if (IOS==5) begin
 			if (!C8Mr && (IODONE || IOBERR)) begin
 				IOS <= 6;
 				IOACT <= 0;
@@ -86,55 +88,33 @@ module IOBM(
 			end
 			IOS0 <= 0;
 			ALE0 <= 1;
-		end 3'h6: begin
+		end else if (IOS==6) begin
 			IOS <= 7;
 			IOS0 <= 0;
 			IOACT <= 0;
 			ALE0 <= 0;
-		end 3'h7: begin
+		end else if (IOS==7) begin
 			IOS <= 0;
 			IOS0 <= 1;
 			IOACT <= 0;
 			ALE0 <= 0;
 		end
-	endcase
+	end
 
 	/* PDS address and data latch control */
 	always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
 	reg DoutOE = 0;
 	always @(posedge C16M) begin
-		DoutOE <= (IOS==0 && IOREQr && !IORW && !C8Mr) ||
+		DoutOE <= (IOS==0 && IOWRREQr && !C8Mr) ||
 				  (DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
 	end
 	assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
 
-	/* AS, DS, RW control */
+	/* AS, DS control */
 	always @(negedge C16M) begin
-		nAS <= !(
-			(IOS==0 && IOREQr && !C8Mr) || 
-			(IOS==2) || 
-			(IOS==3) || 
-			(IOS==4) || 
-			(IOS==5));
-		RnW <= !(
-			(IOS==0 && IOREQr && !IORW && !C8Mr) || 
-			(!IORW && IOS==2) || 
-			(!IORW && IOS==3) || 
-			(!IORW && IOS==4) || 
-			(!IORW && IOS==5) || 
-			(!IORW && IOS==6));
-		nLDS <= !(
-			(IOS==0 && IOREQr && IORW && IOLDS && !C8Mr) ||
-			(IOS==2 && IOLDS) ||
-			(IOS==3 && IOLDS) ||
-			(IOS==4 && IOLDS) ||
-			(IOS==5 && IOLDS));
-		nUDS <= !(
-			(IOS==0 && IOREQr && IORW && IOUDS && !C8Mr) ||
-			(IOS==2 && IOUDS) ||
-			(IOS==3 && IOUDS) ||
-			(IOS==4 && IOUDS) ||
-			(IOS==5 && IOUDS));
+		nASout <= !((IOS==0 && IOREQr && !C8Mr) || IOS==2 || IOS==3 || IOS==4 || IOS==5);
+		nLDS <= !(IOLDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nLDS) || IOS==3 || IOS==4 || IOS==5));
+		nUDS <= !(IOUDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nUDS) || IOS==3 || IOS==4 || IOS==5));
 	end
 
 endmodule
diff --git a/cpld/IOBS.v b/cpld/IOBS.v
index 9ea6344..958f1fb 100644
--- a/cpld/IOBS.v
+++ b/cpld/IOBS.v
@@ -10,7 +10,7 @@ module IOBS(
 	/* Read data OE control */
 	output nDinOE,
 	/* IOB master controller interface */
-	output reg IOREQ, output reg IORW,
+	output reg IORDREQ, output reg IOWRREQ,
 	input IOACT, input IODONEin, input IOBERR,
 	/* FIFO primary level control */
 	output reg ALE0, output reg IOL0, output reg IOU0,
@@ -56,7 +56,7 @@ module IOBS(
 	always @(posedge CLK) begin // ALE clear control
 		// Make address latch transparent in cycle after TS3
 		// (i.e. first TS2 cycle that's not part of current write)
-		if (TS==1) Clear1 <= 1;
+		if (TS==3) Clear1 <= 1;
 		else Clear1 <= 0;
 	end
 	always @(posedge CLK) begin // LDS, UDS, ALE control
@@ -70,32 +70,30 @@ module IOBS(
 	/* FIFO primary level control */
 	always @(posedge CLK) begin
 		if (TS==0) begin
-			// Start IOREQ if FIFO secondary level occupied or FSB request
-			if (ALE1 || (BACT && IOCS && !ALE1 && !Sent)) begin 
-				// Request transfer from IOBM
-				TS <= 1;
-				IOREQ <= 1;
-			end else begin // Otherwise stay in idle
-				TS <= 0;
-				IOREQ <= 0;
-			end
-			// Latch R/W and data strobes from FIFO secondary or FSB
-			if (ALE1) begin
-				IORW <= IORW1;
+			if (ALE1) begin // If FIFO secondary level occupied
+				// Request transfer from IOBM and latch R/W from FIFO
+				TS <= 3;
+				IORDREQ <= IORW1;
+				IOWRREQ <= !IORW1;
 				IOL0 <= IOL1;
 				IOU0 <= IOU1;
-			end else begin
-				IORW <= nWE;
+			end else if (BACT && IOCS && !ALE1 && !Sent) begin // FSB request
+				// Request transfer from IOBM and latch R/W from FSB
+				TS <= 3;
+				IORDREQ <= nWE;
+				IOWRREQ <= !nWE;
 				IOL0 <= !nLDS;
 				IOU0 <= !nUDS;
+			end else begin // Otherwise stay in idle
+				TS <= 0;
+				IORDREQ <= 0;
+				IOWRREQ <= 0;
 			end
-
 			ALE0 <= 0;
-		end else if (TS==1) begin
-			TS <= 2; // Always go to TS2
-			IOREQ <= 1; // Keep IOREQ active
+		end else if (TS==3) begin
+			TS <= 2; // Always go to TS2. Keep IORDREQ/IOWRREQ active
 			ALE0 <= 1; // Latch address (and data)
-			// Latch data strobes again from FIFO or FSB as appropriate
+			// Latch data strobes from FIFO or FSB as appropriate
 			if (ALE1) begin
 				IOL0 <= IOL1;
 				IOU0 <= IOU1;
@@ -104,20 +102,19 @@ module IOBS(
 				IOU0 <= !nUDS;
 			end
 		end else if (TS==2) begin
-			// Wait for IOACT (transfer started) then withdraw IOREQ and enter TS1
+			// Wait for IOACT then withdraw IOREQ and enter TS1
 			if (IOACTr) begin
-				TS <= 3;
-				IOREQ <= 0;
-			end else begin
-				TS <= 2;
-				IOREQ <= 1;
-			end
+				TS <= 1;
+				IORDREQ <= 0;
+				IOWRREQ <= 0;
+			end else TS <= 2;
 			ALE0 <= 1; // Keep address latched
-		end else if (TS==3) begin
+		end else if (TS==1) begin
 			// Wait for IOACT low (transfer over) before going back to idle
 			if (!IOACTr) TS <= 0;
-			else TS <= 3;
-			IOREQ <= 0;
+			else TS <= 1;
+			IORDREQ <= 0;
+			IOWRREQ <= 0;
 			ALE0 <= 0; // Release addr latch since it's controlled by IOBM now
 		end
 	end
diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v
index 72fb23e..d00d65c 100644
--- a/cpld/WarpSE.v
+++ b/cpld/WarpSE.v
@@ -18,7 +18,6 @@ module WarpSE(
 	output nAS_IOB,
 	output nUDS_IOB,
 	output nLDS_IOB,
-	output RnW_IOB,
 	output nBR_IOB,
 	input nBG_IOB,
 	input nBERR_IOB,
@@ -41,15 +40,18 @@ module WarpSE(
 	output MCKE,
 	input [5:0] DBG);
 
+	/* MC68k clock enable */
+	assign MCKE = 1;
+
 	/* GA gated (translated) address output */
-	assign GA[23:22] = A_FSB[23:22];
-	/*assign GA[23:22] = (
+	//assign GA[23:22] = A_FSB[23:22];
+	assign GA[23:22] = (
 		// $800000-$8FFFFF to $000000-$0FFFFF (1 MB)
 		(A_FSB[23:20]==4'h8) ||
 		// $700000-$7EFFFF to $300000-$3EFFFF (960 kB)
 		(A_FSB[23:20]==4'h7 && A_FSB[19:16]!=4'hF) ||
 		// $600000-$6FFFFF to $200000-$2FFFFF (1 MB)
-		(A_FSB[23:20]==4'h6)) ? 2'b00 : A_FSB[23:22];*/
+		(A_FSB[23:20]==4'h6)) ? 2'b00 : A_FSB[23:22];
 
 	/* Reset input and open-drain output */
 	wire nRESin = nRES;
@@ -57,34 +59,30 @@ module WarpSE(
 	assign nRES = !nRESout ? 1'b0 : 1'bZ;
 
 	/* AS cycle detection */
-	wire BACT, BACTr;
-
-	/* MC68k clock enable */
-	wire MCKEi;
+	wire BACT;
+	wire BACTr;
 
 	/* Refresh request/ack signals */
 	wire RefReq, RefUrg;
 	
 	/* QoS enable */
-	wire IOQoSEN;
+	wire QoSEN;
 	
 	/* FSB chip select signals */
-	wire IOCS, IORealCS, IOPWCS, IACKCS;
+	wire IOCS, IORealCS, IOPWCS, IACS;
 	wire ROMCS, ROMCS4X;
-	wire RAMCS, RAMCS0X;
-	wire IOQoSCS, SndQoSCS;
+	wire RAMCS, RAMCS0X, QoSCS;
 	CS cs(
 		/* MC68HC000 interface */
 		A_FSB[23:08], FCLK, nRESin, nWE_FSB,
 		/* /AS cycle detection */
 		BACT,
 		/* QoS enable input */
-		IOQoSEN,
+		QoSEN,
 		/* Device select outputs */
-		IOCS, IORealCS, IOPWCS, IACKCS,
+		IOCS, IORealCS, IOPWCS, IACS,
 		ROMCS, ROMCS4X,
-		RAMCS, RAMCS0X,
-		IOQoSCS, SndQoSCS);
+		RAMCS, RAMCS0X, QoSCS);
 
 	wire RAMReady;
 	RAM ram(
@@ -104,7 +102,7 @@ module WarpSE(
 		nRAMLWE, nRAMUWE, nOE, nROMOE, nROMWE);
 
 	wire IONPReady, IOPWReady;
-	wire IOREQ, IORW;
+	wire IORDREQ, IOWRREQ;
 	wire IOL0, IOU0;
 	wire ALE0S, ALE0M, ALE1;
 	assign nADoutLE0 = ~(ALE0S || ALE0M);
@@ -122,7 +120,7 @@ module WarpSE(
 		/* Read data OE control */
 		nDinOE,
 		/* IOB Master Controller Interface */
-		IOREQ, IORW,
+		IORDREQ, IOWRREQ,
 		IOACT, IODONE, IOBERR,
 		/* FIFO primary level control */
 		ALE0S, IOL0, IOU0,
@@ -131,26 +129,25 @@ module WarpSE(
 	
 	wire AoutOE;
 	assign nAoutOE = !AoutOE;
-	wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, RnW_IOBout, nVMA_IOBout;
+	wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
 	assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
 	assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
 	assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
-	assign RnW_IOB = AoutOE ? RnW_IOBout : 1'bZ;
 	assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
 	IOBM iobm(
 		/* PDS interface */
 		C16M, C8M, E,
-		nAS_IOBout, nLDS_IOBout, nUDS_IOBout, RnW_IOBout, nVMA_IOBout,
+		nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
 		nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
 		/* PDS address and data latch control */
 		AoutOE, nDoutOE, ALE0M, nDinLE,
 		/* IO bus slave port interface */
-		IOREQ, IORW, IOL0, IOU0,
+		IORDREQ, IOWRREQ, IOL0, IOU0,
 		IOACT, IODONE, IOBERR);
 
 	CNT cnt(
 		/* FSB clock and E clock inputs */
-		FCLK, C8M, E,
+		FCLK, E,
 		/* Refresh request */
 		RefReq, RefUrg,
 		/* Reset, button */
@@ -158,23 +155,19 @@ module WarpSE(
 		/* Mac PDS bus master control outputs */
 		AoutOE, nBR_IOB,
 		/* QoS control */
-		BACT, BACTr,
-		IOQoSCS, SndQoSCS, IACKCS,
-		IOQoSEN, MCKEi);
+		BACT, QoSCS, QoSEN);
 	
 	FSB fsb(
 		/* MC68HC000 interface */
 		FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
-		/* MC68HC000 clock enable */
-		MCKEi, MCKE,
 		/* FSB cycle detection */
 		BACT, BACTr,
 		/* Ready inputs */
 		ROMCS4X,
 		RAMCS0X, RAMReady,
 		IOPWCS, IOPWReady, IONPReady,
-		IOQoSEN,
+		QoSEN,
 		/* Interrupt acknowledge select */
-		IACKCS);
+		IACS);
 
 endmodule