0.7a-fastiack-fastscsi

2024-11-21 17:31:47 +00:00 · 2024-10-12 00:39:35 -04:00 · 2024-10-12 00:39:35 -04:00 · 1ea0196721
commit 1ea0196721
parent de00b7801e
42 changed files with 5308 additions and 117 deletions
--- a/cpld/SET.v
+++ b/cpld/SET.v
@ -22,9 +22,9 @@ module SET(
 			SlowVIA  <= 1;
 			SlowIWM  <= 1;
 			SlowSCC  <= 1;
-			SlowSCSI <= 1;
+			SlowSCSI <= 0;
 			SlowSnd  <= 1;
-			SlowClockGate <= 0;
+			SlowClockGate <= 1;
 		end else if (SetWRr) begin
 			SlowTimeout[3:0] <= A[11:8];
 			SlowIACK <= A[7];
--- a/cpld/XC95144XL/WarpSE-0.7a-fastiack-fastscsi.svf
+++ b/cpld/XC95144XL/WarpSE-0.7a-fastiack-fastscsi.svf
--- a/cpld/XC95144XL/WarpSE.bld
+++ b/cpld/XC95144XL/WarpSE.bld
@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

-Total memory usage is 154560 kilobytes
+Total memory usage is 155072 kilobytes

 Writing NGD file "WarpSE.ngd" ...
 Total REAL time to NGDBUILD completion:  3 sec
--- a/cpld/XC95144XL/WarpSE.cmd_log
+++ b/cpld/XC95144XL/WarpSE.cmd_log
@ -1351,3 +1351,10 @@ XSLTProcess WarpSE_build.xml
 tsim -intstyle ise WarpSE WarpSE.nga 
 taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm 
 hprep6 -s IEEE1149 -n WarpSE -i WarpSE 
+xst -intstyle ise -ifn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.syr" 
+ngdbuild -intstyle ise -dd _ngo -uc C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd  
+cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd 
+XSLTProcess WarpSE_build.xml 
+tsim -intstyle ise WarpSE WarpSE.nga 
+taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm 
+hprep6 -s IEEE1149 -n WarpSE -i WarpSE 
--- a/cpld/XC95144XL/WarpSE.gise
+++ b/cpld/XC95144XL/WarpSE.gise
@ -70,7 +70,7 @@
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1728707316" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728707308">
+    <transform xil_pn:end_ts="1728707657" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728707650">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@ -90,7 +90,7 @@
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1728707321" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728707316">
+    <transform xil_pn:end_ts="1728707663" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728707657">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="WarpSE.bld"/>
@ -99,7 +99,7 @@
      <outfile xil_pn:name="_ngo"/>
      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    </transform>
-    <transform xil_pn:end_ts="1728707341" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728707321">
+    <transform xil_pn:end_ts="1728707682" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728707663">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@ -119,12 +119,12 @@
      <outfile xil_pn:name="WarpSE_html"/>
      <outfile xil_pn:name="WarpSE_pad.csv"/>
    </transform>
-    <transform xil_pn:end_ts="1728707354" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728707352">
+    <transform xil_pn:end_ts="1728707694" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728707692">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="WarpSE.jed"/>
    </transform>
-    <transform xil_pn:end_ts="1728707354" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728707354">
+    <transform xil_pn:end_ts="1728707694" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728707694">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_impactbatch.log"/>
@ -140,7 +140,7 @@
      <outfile xil_pn:name="_impactbatch.log"/>
      <outfile xil_pn:name="ise_impact.cmd"/>
    </transform>
-    <transform xil_pn:end_ts="1728707344" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728707341">
+    <transform xil_pn:end_ts="1728707684" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728707682">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
--- a/cpld/XC95144XL/WarpSE.jed
+++ b/cpld/XC95144XL/WarpSE.jed
@ -1,5 +1,5 @@
 Programmer Jedec Bit Map
-Date Extracted: Sat Oct 12 00:29:13 2024
+Date Extracted: Sat Oct 12 00:34:53 2024

 QF93312*
 QP100*
@ -330,7 +330,7 @@ L0013632 000000 000000 000000 000000 000001 000000 000000 000000*
 L0013680 000000 000000 000000 000000 000001 000000 000000 000000*
 L0013728 000000 000000 000000 000000 000001 000000 000000 000000*
 L0013776 000000 000000 000000 000000 000001 000000 000000 000000*
-L0013824 00001000 00000000 00000000 00000000 00011010 00000001 01001011 00000011*
+L0013824 00000000 00000000 00000000 00000000 00011010 00000001 01001011 00000011*
 L0013888 00000000 00000000 00000000 00000000 00011000 00000011 00011000 00000001*
 L0013952 00000000 00000000 00000000 00000000 00001000 00000001 00000000 00000001*
 L0014016 00000000 00000000 00000000 00000000 00000001 00000001 00010001 00000011*
@ -345,7 +345,7 @@ L0014496 000000 000000 000000 000001 000000 000000 000000 000000*
 L0014544 000000 000000 000000 000000 000000 000000 001000 000000*
 L0014592 000000 000000 000000 000000 000000 000000 001100 000000*
 L0014640 000000 000000 000000 000000 000000 000000 000000 000000*
-L0014688 00000000 00000000 11111000 01000000 00000000 00000000 00010000 00000000*
+L0014688 00001000 00000000 11111000 01000000 00000000 00000000 00010000 00000000*
 L0014752 00000000 00000000 00000000 01000000 00000000 00000000 00000011 01000010*
 L0014816 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01001010*
 L0014880 00000000 00000000 00000000 00000000 00000000 00000000 10000100 00001000*
@ -423,11 +423,11 @@ L0018960 000000 000000 000000 000000 000000 000000 000000 000000*
 L0019008 00000011 00000000 00000000 00000001 00000000 00000001 00000010 00000000*
 L0019072 00000001 00000000 00000010 00000011 00000010 00000000 00000000 00000000*
 L0019136 00000001 00000000 00000000 00000001 00000000 00000010 00000011 00000000*
-L0019200 00000001 00000000 00000000 00000001 00000000 00000010 00000000 00000010*
+L0019200 00000000 00000000 00000000 00000001 00000000 00000010 00000000 00000010*
 L0019264 00000001 00000000 00000000 00000010 00000010 00000001 00000000 00000010*
 L0019328 00000001 00000000 00000001 00000011 00000010 00000010 00000000 00000010*
 L0019392 00000000 00000000 00000001 00000010 00000000 00000001 00000001 00000000*
-L0019456 00000000 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
+L0019456 00000001 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
 L0019520 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000*
 L0019584 000000 000000 000000 000000 000000 000000 000000 000000*
 L0019632 000000 001000 000000 000000 000000 100000 000000 000100*
@ -455,7 +455,7 @@ L0020800 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00000010
 L0020864 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0020928 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0020992 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000001*
-L0021056 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0021056 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0021120 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
 L0021184 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
 L0021248 00000000 00000000 00000010 00000000 00000000 00000001 00000000 00000000*
@ -470,7 +470,7 @@ L0021664 00000000 00000000 00000000 00000000 00000000 00001000 00000011 00000010
 L0021728 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000010*
 L0021792 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000000*
 L0021856 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000*
-L0021920 00000100 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
+L0021920 00000000 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
 L0021984 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0022048 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
 L0022112 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
@ -1446,7 +1446,7 @@ L0077888 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000
 L0077952 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000*
 L0078016 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078080 00000000 00000000 10000000 00000000 00000000 00000000 00000000 00000000*
-L0078144 00000000 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
+L0078144 00000100 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
 L0078208 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078272 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078336 000000 000000 000000 000000 000000 000000 000000 000000*
@ -1461,7 +1461,7 @@ L0078752 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 L0078816 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078880 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078944 00000000 00000000 00001000 00000000 00000000 00000000 00000000 00010000*
-L0079008 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
+L0079008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
 L0079072 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
 L0079136 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
 L0079200 000000 000000 000000 000000 000001 000000 000000 000000*
@ -1651,7 +1651,7 @@ L0089712 000000 000000 000000 000000 000000 000000 000000 000000*
 L0089760 000000 000000 000000 000000 000000 000000 000000 000000*
 L0089808 000000 000000 000000 000000 000000 000000 000000 000000*
 L0089856 00000000 00000000 00000000 10100000 00000000 00000000 00000000 00000000*
-L0089920 00001000 00000000 00000100 00000100 00000000 00000000 00010000 00000000*
+L0089920 00000000 00000000 00000100 00000100 00000000 00000000 00010000 00000000*
 L0089984 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00000000*
 L0090048 00000000 00000000 00000000 00100100 00000000 00000000 00010000 00000000*
 L0090112 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00000000*
@ -1666,7 +1666,7 @@ L0090576 000000 000000 000000 000000 000000 000000 001000 000100*
 L0090624 000000 000000 000000 000010 000000 000000 001000 000000*
 L0090672 000000 000000 000000 000000 000000 000000 001000 000000*
 L0090720 00000000 00000100 10000000 00000000 00000000 00000000 10001100 00000000*
-L0090784 00000000 00000000 00000000 00000000 00000000 00000000 10100100 00000000*
+L0090784 00001000 00000000 00000000 00000000 00000000 00000000 10100100 00000000*
 L0090848 00000000 00000000 00000100 00000000 00000000 00000000 00001000 00000000*
 L0090912 00000000 00000000 01111000 00000000 00000000 00000000 00000000 00000000*
 L0090976 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
--- a/cpld/XC95144XL/WarpSE.mfd
+++ b/cpld/XC95144XL/WarpSE.mfd
@ -575,8 +575,8 @@ INPUTS | 4 | nPOR  | SlowClockGate  | set/SetWRr  | A_FSB<1>
 INPUTMC | 3 | 0 | 17 | 0 | 16 | 6 | 3
 INPUTP | 1 | 149
 EQ | 3 | 
-   SlowClockGate.D = nPOR & SlowClockGate & !set/SetWRr
-	# nPOR & A_FSB<1> & set/SetWRr;
+   !SlowClockGate.D = nPOR & !SlowClockGate & !set/SetWRr
+	# nPOR & !A_FSB<1> & set/SetWRr;
   SlowClockGate.CLK = FCLK;	// GCK
 GLOBALS | 1 | 2 | FCLK

@ -623,8 +623,8 @@ INPUTS | 4 | nPOR  | SlowSCSI  | set/SetWRr  | A_FSB<3>
 INPUTMC | 3 | 0 | 17 | 0 | 12 | 6 | 3
 INPUTP | 1 | 155
 EQ | 3 | 
-   !SlowSCSI.D = nPOR & !SlowSCSI & !set/SetWRr
-	# nPOR & !A_FSB<3> & set/SetWRr;
+   SlowSCSI.D = nPOR & SlowSCSI & !set/SetWRr
+	# nPOR & A_FSB<3> & set/SetWRr;
   SlowSCSI.CLK = FCLK;	// GCK
 GLOBALS | 1 | 2 | FCLK

--- a/cpld/XC95144XL/WarpSE.nga
+++ b/cpld/XC95144XL/WarpSE.nga
--- a/cpld/XC95144XL/WarpSE.ngc
+++ b/cpld/XC95144XL/WarpSE.ngc
--- a/cpld/XC95144XL/WarpSE.ngd
+++ b/cpld/XC95144XL/WarpSE.ngd
--- a/cpld/XC95144XL/WarpSE.ngr
+++ b/cpld/XC95144XL/WarpSE.ngr
--- a/cpld/XC95144XL/WarpSE.pad
+++ b/cpld/XC95144XL/WarpSE.pad
@ -1,7 +1,7 @@
 Release 8.1i - Fit P.20131013
 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved

-10-12-2024  0:28AM
+10-12-2024  0:34AM

 NOTE: This file is designed to be imported into a spreadsheet program
 such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
--- a/cpld/XC95144XL/WarpSE.rpt
+++ b/cpld/XC95144XL/WarpSE.rpt
@ -1,7 +1,7 @@
 
 cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
-Design Name: WarpSE                              Date: 10-12-2024,  0:28AM
+Design Name: WarpSE                              Date: 10-12-2024,  0:34AM
 Device Used: XC95144XL-10-TQ100
 Fitting Status: Successful

@ -982,8 +982,8 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
 RnW_IOB_OE <= NOT nAoutOE;

 FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
-SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(1) AND set/SetWRr));
+SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));

 FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
 SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)
@ -998,8 +998,8 @@ SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
 	OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));

 FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
-SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
-	OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
+SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
+	OR (nPOR AND A_FSB(3) AND set/SetWRr));

 FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
 SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
--- a/cpld/XC95144XL/WarpSE.syr
+++ b/cpld/XC95144XL/WarpSE.syr
@ -4,7 +4,7 @@ Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.


 Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.08 secs
+Total CPU time to Xst completion: 0.09 secs
 
 --> Parameter xsthdpdir set to xst

@ -474,11 +474,11 @@ Cell Usage :


 Total REAL time to Xst completion: 5.00 secs
-Total CPU time to Xst completion: 4.98 secs
+Total CPU time to Xst completion: 4.95 secs
 
 --> 

-Total memory usage is 262752 kilobytes
+Total memory usage is 263456 kilobytes

 Number of errors   :    0 (   0 filtered)
 Number of warnings :    3 (   0 filtered)
--- a/cpld/XC95144XL/WarpSE.vm6
+++ b/cpld/XC95144XL/WarpSE.vm6
@ -2391,11 +2391,11 @@ NODE | IONPReady.Q | 11632 | ? | 0 | 0 | IONPReady | NULL | NULL | IONPReady.REG

 INPUT_INSTANCE | 0 | 0 | NULL | A_FSB_1_IBUF | WarpSE_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | A_FSB<1> | 11450 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | A_FSB<1> | 11444 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | A_FSB_1_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_1_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX

-MACROCELL_INSTANCE | PrldLow+OptxMapped | SlowClockGate | WarpSE_COPY_0_COPY_0 | 2155873280 | 5 | 1
+MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | SlowClockGate | WarpSE_COPY_0_COPY_0 | 2155873536 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | nPOR | 11226 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | nPOR.Q | nPOR | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
@ -2403,7 +2403,7 @@ NODE | SlowClockGate | 11256 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowClo
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_1_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_1_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | FCLK_IBUF/FCLK | 11220 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | FCLK_IBUF | 3 | 5 | II_FCLK
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
@ -2417,14 +2417,14 @@ NODE | SlowClockGate | 11256 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowClo
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_1_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_1_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | SlowClockGate.D1 | 11634 | ? | 0 | 4096 | SlowClockGate | NULL | NULL | SlowClockGate.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
 SIGNAL | NODE | SlowClockGate.D2 | 11635 | ? | 0 | 4096 | SlowClockGate | NULL | NULL | SlowClockGate.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 3 | IV_TRUE | nPOR | IV_TRUE | SlowClockGate | IV_FALSE | set/SetWRr
-SPPTERM | 3 | IV_TRUE | nPOR | IV_TRUE | A_FSB_1_IBUF | IV_TRUE | set/SetWRr
+SPPTERM | 3 | IV_TRUE | nPOR | IV_FALSE | SlowClockGate | IV_FALSE | set/SetWRr
+SPPTERM | 3 | IV_TRUE | nPOR | IV_FALSE | A_FSB_1_IBUF | IV_TRUE | set/SetWRr

 SRFF_INSTANCE | SlowClockGate.REG | SlowClockGate | 0 | 2 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
@ -2436,9 +2436,9 @@ NODE | SlowClockGate.Q | 11636 | ? | 0 | 0 | SlowClockGate | NULL | NULL | SlowC

 INPUT_INSTANCE | 0 | 0 | NULL | A_FSB_7_IBUF | WarpSE_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | A_FSB<7> | 11451 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | A_FSB<7> | 11450 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | A_FSB_7_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_7_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX

 MACROCELL_INSTANCE | PrldLow+OptxMapped | SlowIACK | WarpSE_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
@ -2448,7 +2448,7 @@ NODE | SlowIACK | 11257 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowIACK.Q |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_7_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_7_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | FCLK_IBUF/FCLK | 11220 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | FCLK_IBUF | 3 | 5 | II_FCLK
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
@ -2462,7 +2462,7 @@ NODE | SlowIACK | 11257 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowIACK.Q |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_7_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_7_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | SlowIACK.D1 | 11638 | ? | 0 | 4096 | SlowIACK | NULL | NULL | SlowIACK.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
@ -2481,9 +2481,9 @@ NODE | SlowIACK.Q | 11640 | ? | 0 | 0 | SlowIACK | NULL | NULL | SlowIACK.REG |

 INPUT_INSTANCE | 0 | 0 | NULL | A_FSB_5_IBUF | WarpSE_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | A_FSB<5> | 11444 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | A_FSB<5> | 11445 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | A_FSB_5_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_5_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX

 MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | SlowIWM | WarpSE_COPY_0_COPY_0 | 2155873536 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
@ -2493,7 +2493,7 @@ NODE | SlowIWM | 11258 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowIWM.Q | S
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_5_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_5_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | FCLK_IBUF/FCLK | 11220 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | FCLK_IBUF | 3 | 5 | II_FCLK
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
@ -2507,7 +2507,7 @@ NODE | SlowIWM | 11258 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowIWM.Q | S
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_5_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_5_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | SlowIWM.D1 | 11642 | ? | 0 | 4096 | SlowIWM | NULL | NULL | SlowIWM.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
@ -2526,9 +2526,9 @@ NODE | SlowIWM.Q | 11644 | ? | 0 | 0 | SlowIWM | NULL | NULL | SlowIWM.REG | 0 |

 INPUT_INSTANCE | 0 | 0 | NULL | A_FSB_4_IBUF | WarpSE_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | A_FSB<4> | 11445 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | A_FSB<4> | 11446 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | A_FSB_4_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_4_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX

 MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | SlowSCC | WarpSE_COPY_0_COPY_0 | 2155873536 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
@ -2538,7 +2538,7 @@ NODE | SlowSCC | 11259 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowSCC.Q | S
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_4_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_4_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | FCLK_IBUF/FCLK | 11220 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | FCLK_IBUF | 3 | 5 | II_FCLK
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
@ -2552,7 +2552,7 @@ NODE | SlowSCC | 11259 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowSCC.Q | S
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_4_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_4_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | SlowSCC.D1 | 11646 | ? | 0 | 4096 | SlowSCC | NULL | NULL | SlowSCC.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
@ -2571,11 +2571,11 @@ NODE | SlowSCC.Q | 11648 | ? | 0 | 0 | SlowSCC | NULL | NULL | SlowSCC.REG | 0 |

 INPUT_INSTANCE | 0 | 0 | NULL | A_FSB_3_IBUF | WarpSE_COPY_0_COPY_0 | 16 | 1 | 1
 INPUT_NODE_TYPE | 0 | 5 | II_IN
-NODE | A_FSB<3> | 11446 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
+NODE | A_FSB<3> | 11451 | PI | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
 OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
-NODE | A_FSB_3_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_3_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX

-MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | SlowSCSI | WarpSE_COPY_0_COPY_0 | 2155873536 | 5 | 1
+MACROCELL_INSTANCE | PrldLow+OptxMapped | SlowSCSI | WarpSE_COPY_0_COPY_0 | 2155873280 | 5 | 1
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | nPOR | 11226 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | nPOR.Q | nPOR | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
@ -2583,7 +2583,7 @@ NODE | SlowSCSI | 11260 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowSCSI.Q |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_3_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_3_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | FCLK_IBUF/FCLK | 11220 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | FCLK_IBUF | 3 | 5 | II_FCLK
 OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
@ -2597,14 +2597,14 @@ NODE | SlowSCSI | 11260 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | SlowSCSI.Q |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | set/SetWRr | 11348 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | set/SetWRr.Q | set/SetWRr | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_3_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_3_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | SlowSCSI.D1 | 11650 | ? | 0 | 4096 | SlowSCSI | NULL | NULL | SlowSCSI.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
 OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
 SIGNAL | NODE | SlowSCSI.D2 | 11651 | ? | 0 | 4096 | SlowSCSI | NULL | NULL | SlowSCSI.SI | 2 | 9 | MC_SI_D2
-SPPTERM | 3 | IV_TRUE | nPOR | IV_FALSE | SlowSCSI | IV_FALSE | set/SetWRr
-SPPTERM | 3 | IV_TRUE | nPOR | IV_FALSE | A_FSB_3_IBUF | IV_TRUE | set/SetWRr
+SPPTERM | 3 | IV_TRUE | nPOR | IV_TRUE | SlowSCSI | IV_FALSE | set/SetWRr
+SPPTERM | 3 | IV_TRUE | nPOR | IV_TRUE | A_FSB_3_IBUF | IV_TRUE | set/SetWRr

 SRFF_INSTANCE | SlowSCSI.REG | SlowSCSI | 0 | 2 | 1
 INPUT_NODE_TYPE | 0 | 8 | SRFF_D
@ -5899,7 +5899,7 @@ MACROCELL_INSTANCE | OptxMapped | RA_0_OBUF | WarpSE_COPY_0_COPY_0 | 2155872256
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_1_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_1_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | A_FSB_9_IBUF | 11328 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_9_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
@ -5909,7 +5909,7 @@ SIGNAL_INSTANCE | RA_0_OBUF.SI | RA_0_OBUF | 0 | 3 | 2
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_1_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_1_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_1_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | A_FSB_9_IBUF | 11328 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_9_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
@ -5932,7 +5932,7 @@ NODE | A_FSB_17_IBUF | 11194 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_7_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_7_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | A_FSB_21_IBUF | 11190 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_21_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
@ -5962,7 +5962,7 @@ NODE | A_FSB_17_IBUF | 11194 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_7_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_7_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | A_FSB_21_IBUF | 11190 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_21_IBUF | 0 | 5 | II_IMUX
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
@ -6076,7 +6076,7 @@ NODE | A_FSB_16_IBUF | 11195 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_7_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_7_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
 NODE | RA_2_OBUF | 11352 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | RA_2_OBUF.Q | RA_2_OBUF | 0 | 0 | MC_Q

@ -6086,7 +6086,7 @@ NODE | A_FSB_16_IBUF | 11195 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_7_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_7_IBUF | 11345 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_7_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | RA_2_OBUF.D1 | 11947 | ? | 0 | 4096 | RA_2_OBUF | NULL | NULL | RA_2_OBUF.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
@ -6107,7 +6107,7 @@ NODE | A_FSB_11_IBUF | 11218 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_3_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_3_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
 NODE | RA_4_OBUF | 11353 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | RA_4_OBUF.Q | RA_4_OBUF | 0 | 0 | MC_Q

@ -6117,7 +6117,7 @@ NODE | A_FSB_11_IBUF | 11218 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_3_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_3_IBUF | 11346 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_3_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | RA_4_OBUF.D1 | 11951 | ? | 0 | 4096 | RA_4_OBUF | NULL | NULL | RA_4_OBUF.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
@ -6138,7 +6138,7 @@ NODE | A_FSB_12_IBUF | 11217 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_4_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_4_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
 NODE | RA_5_OBUF | 11354 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | RA_5_OBUF.Q | RA_5_OBUF | 0 | 0 | MC_Q

@ -6148,7 +6148,7 @@ NODE | A_FSB_12_IBUF | 11217 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_4_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_4_IBUF | 11333 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_4_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | RA_5_OBUF.D1 | 11955 | ? | 0 | 4096 | RA_5_OBUF | NULL | NULL | RA_5_OBUF.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
@ -6169,7 +6169,7 @@ NODE | A_FSB_13_IBUF | 11197 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_5_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_5_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 0 | 0 | MC_Q
 NODE | RA_6_OBUF | 11355 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | RA_6_OBUF.Q | RA_6_OBUF | 0 | 0 | MC_Q

@ -6179,7 +6179,7 @@ NODE | A_FSB_13_IBUF | 11197 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL |
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
 NODE | ram/RASEL | 11280 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | ram/RASEL.Q | ram/RASEL | 1 | 0 | MC_UIM
 INPUT_NODE_TYPE | 1 | 100 | NOTYPE
-NODE | A_FSB_5_IBUF | 11331 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
+NODE | A_FSB_5_IBUF | 11332 | ? | 0 | 0 | WarpSE_COPY_0_COPY_0 | NULL | NULL | A_FSB_5_IBUF | 0 | 5 | II_IMUX
 OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
 SIGNAL | NODE | RA_6_OBUF.D1 | 11959 | ? | 0 | 4096 | RA_6_OBUF | NULL | NULL | RA_6_OBUF.SI | 1 | 9 | MC_SI_D1
 SPPTERM | 0 | IV_ZERO
--- a/cpld/XC95144XL/WarpSE.xml
+++ b/cpld/XC95144XL/WarpSE.xml
--- a/cpld/XC95144XL/WarpSE_SVF.ipf
+++ b/cpld/XC95144XL/WarpSE_SVF.ipf
--- a/cpld/XC95144XL/WarpSE_html/fit/ascii.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/ascii.htm
@ -3,7 +3,7 @@
 
 cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
-Design Name: WarpSE                              Date: 10-12-2024,  0:28AM
+Design Name: WarpSE                              Date: 10-12-2024,  0:34AM
 Device Used: XC95144XL-10-TQ100
 Fitting Status: Successful

@ -984,8 +984,8 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
 RnW_IOB_OE <= NOT nAoutOE;

 FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
-SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(1) AND set/SetWRr));
+SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));

 FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
 SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)
@ -1000,8 +1000,8 @@ SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
 	OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));

 FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
-SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
-	OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
+SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
+	OR (nPOR AND A_FSB(3) AND set/SetWRr));

 FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
 SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
--- a/cpld/XC95144XL/WarpSE_html/fit/defeqns.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/defeqns.htm
@ -218,8 +218,8 @@ FTCPE_RnW_IOB: FTCPE port map (RnW_IOB_I,RnW_IOB_T,NOT C16M,'0','0');
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RnW_IOB_OE <= NOT nAoutOE;
 </td></tr><tr><td>
 FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND A_FSB(1) AND set/SetWRr));
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)
@ -234,8 +234,8 @@ FDCPE_SlowSCC: FDCPE port map (SlowSCC,SlowSCC_D,FCLK,'0','0');
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND A_FSB(3) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
--- a/cpld/XC95144XL/WarpSE_html/fit/eqns.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/eqns.htm
@ -4,7 +4,7 @@
      var design = "WarpSE";
      var device = "XC95144XL";
      signals = new Array("ALE0M","ALE0S","ASrf","BACTr","GA22_SPECSIG","GA23_SPECSIG","IOACT","IODONE","IOL0","IONPReady","IOREQ","IORW","IOU0","MCKE","QoSEN","RA0_SPECSIG","RA10_SPECSIG","RA11_SPECSIG","RA1_SPECSIG","RA2_SPECSIG","RA3_SPECSIG","RA4_SPECSIG","RA5_SPECSIG","RA6_SPECSIG","RA7_SPECSIG","RA8_SPECSIG","RA9_SPECSIG","RAMReady","RefReq","RefUrg","RnW_IOB","SlowClockGate","SlowIACK","SlowIWM","SlowSCC","SlowSCSI","SlowSnd","SlowTimeout0_SPECSIG","SlowTimeout1_SPECSIG","SlowTimeout2_SPECSIG","SlowTimeout3_SPECSIG","SlowVIA","cntC8Mr0_SPECSIG","cntC8Mr1_SPECSIG","cntC8Mr2_SPECSIG","cntC8Mr3_SPECSIG","cntEr0_SPECSIG","cntEr1_SPECSIG","cntIS0_SPECSIG","cntIS1_SPECSIG","cntLTimer0_SPECSIG","cntLTimer10_SPECSIG","cntLTimer11_SPECSIG","cntLTimer1_SPECSIG","cntLTimer2_SPECSIG","cntLTimer3_SPECSIG","cntLTimer4_SPECSIG","cntLTimer5_SPECSIG","cntLTimer6_SPECSIG","cntLTimer7_SPECSIG","cntLTimer8_SPECSIG","cntLTimer9_SPECSIG","cntLTimerTick_SPECSIG","cntQS0_SPECSIG","cntQS1_SPECSIG","cntQS2_SPECSIG","cntQS3_SPECSIG","cntQoSCSr_SPECSIG","cntTimer0_SPECSIG","cntTimer1_SPECSIG","cntTimer2_SPECSIG","cntTimer3_SPECSIG","cntTimerTick_SPECSIG","csOverlay_SPECSIG","iobmC8Mr_SPECSIG","iobmDoutOE_SPECSIG","iobmES0_SPECSIG","iobmES1_SPECSIG","iobmES2_SPECSIG","iobmES3_SPECSIG","iobmEr_SPECSIG","iobmIOREQr_SPECSIG","iobmIOS_FSM_FFd1_SPECSIG","iobmIOS_FSM_FFd2_SPECSIG","iobmIOS_FSM_FFd3_SPECSIG","iobmIOS_FSM_FFd4_SPECSIG","iobmIOS_FSM_FFd5_SPECSIG","iobmIOS_FSM_FFd6_SPECSIG","iobmIOS_FSM_FFd7_SPECSIG","iobmVPAr_SPECSIG","iobsClear1_SPECSIG","iobsIOACTr_SPECSIG","iobsIODONEr0_SPECSIG","iobsIODONEr1_SPECSIG","iobsIODONErf_SPECSIG","iobsIOL1_SPECSIG","iobsIORW1_SPECSIG","iobsIOU1_SPECSIG","iobsLoad1_SPECSIG","iobsSent_SPECSIG","iobsTS_FSM_FFd1_SPECSIG","iobsTS_FSM_FFd2_SPECSIG","nADoutLE0","nADoutLE1","nAS_IOB","nAoutOE","nBERR_FSB","nBR_IOB","nBR_IOBout","nCAS","nDTACK_FSB","nDinLE","nDinOE","nDoutOE","nLDS_IOB","nOE","nPOR","nRAMLWE","nRAMUWE","nRAS","nRES","nRESout","nROMOE","nROMWE","nUDS_IOB","nVMA_IOB","nVPA_FSB","ramCASEndEN_SPECSIG","ramRASEL_SPECSIG","ramRASEN_SPECSIG","ramRASrf_SPECSIG","ramRS0_SPECSIG","ramRS1_SPECSIG","ramRS2_SPECSIG","ramRefCAS_SPECSIG","ramRefDone_SPECSIG","setSetWRr_SPECSIG");
-      sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","ON","ON","ON","ON","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
+      sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","OFF","ON","ON","OFF","ON","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
      sigTypes = new Array("D","D","D","D","","","D","D","D","D","D","D","D","D","D","","","","","","","","","","","","","D","D","D","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","T","T","T","T","T","T","T","T","T","T","T","T","D","D","D","T","D","D","T","T","T","T","D","T","D","D","T","D","T","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","D","T","D","D","","D","D","D","T","","D","D","D","D","","","D","D","T","","","","","D","","","D","T","D","D","D","D","D","D","T","T","D","D","D");

      
@ -276,9 +276,9 @@
          
            pterms["FB1_12_2"]=new Array("nPOR","/A_FSB2_SPECSIG","setSetWRr_SPECSIG");
          
-            pterms["FB1_13_1"]=new Array("nPOR","/SlowSCSI","/setSetWRr_SPECSIG");
+            pterms["FB1_13_1"]=new Array("nPOR","SlowSCSI","/setSetWRr_SPECSIG");
          
-            pterms["FB1_13_2"]=new Array("nPOR","/A_FSB3_SPECSIG","setSetWRr_SPECSIG");
+            pterms["FB1_13_2"]=new Array("nPOR","A_FSB3_SPECSIG","setSetWRr_SPECSIG");
          
            pterms["FB1_14_1"]=new Array("nPOR","/SlowSCC","/setSetWRr_SPECSIG");
          
@ -292,9 +292,9 @@
          
            pterms["FB1_16_2"]=new Array("nPOR","A_FSB7_SPECSIG","setSetWRr_SPECSIG");
          
-            pterms["FB1_17_1"]=new Array("nPOR","SlowClockGate","/setSetWRr_SPECSIG");
+            pterms["FB1_17_1"]=new Array("nPOR","/SlowClockGate","/setSetWRr_SPECSIG");
          
-            pterms["FB1_17_2"]=new Array("nPOR","A_FSB1_SPECSIG","setSetWRr_SPECSIG");
+            pterms["FB1_17_2"]=new Array("nPOR","/A_FSB1_SPECSIG","setSetWRr_SPECSIG");
          
            pterms["FB1_18_1"]=new Array("/nPOR","/cntC8Mr1_SPECSIG","cntC8Mr0_SPECSIG");
          
--- a/cpld/XC95144XL/WarpSE_html/fit/summary.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/summary.htm
@ -30,7 +30,7 @@
 <tr>
 <td width="40%"> <b>Date</b>
 </td>
-<td width="60%"> 10-12-2024,  0:28AM</td>
+<td width="60%"> 10-12-2024,  0:34AM</td>
 </tr>
 </table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
 <table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
--- a/cpld/XC95144XL/WarpSE_html/tim/timing_report.htm
+++ b/cpld/XC95144XL/WarpSE_html/tim/timing_report.htm
@ -27,7 +27,7 @@
  <TD WIDTH="65%" CLASS="cpldta_text_normal"><A HREF="Javascript:popWin('http://www.xilinx.com/literature/index.htm','800','800','test');">XC95144XL</A>, -10 (3.0)</TD>
 </TR>
 <TR>
-  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD>  <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 00:29:02 2024
+  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD>  <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 00:34:43 2024
 </TD>
 </TR>
 <TR>
@ -3882,7 +3882,7 @@ function AUTO_TS_F2P_BACTr_Q_to_nDinOE() {
 <SPAN CLASS="cpldta_text_normal">809</SPAN>
 <BR><SPAN CLASS="cpldta_text_normal_bold"><B>Number of Timing errors:</B></SPAN> 
 <SPAN CLASS="cpldta_text_normal">809</SPAN>
-<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 00:29:02 2024
+<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 00:34:43 2024
 </SPAN>
 <HR>
 </HTML>
--- a/cpld/XC95144XL/WarpSE_ngdbuild.xrpt
+++ b/cpld/XC95144XL/WarpSE_ngdbuild.xrpt
@ -5,7 +5,7 @@
    The structure and the elements are likely to change over the next few releases.
    This means code written to parse this file will need to be revisited each subsequent release.-->

-  <application stringID="NgdBuild" timeStamp="Sat Oct 12 00:28:40 2024">
+  <application stringID="NgdBuild" timeStamp="Sat Oct 12 00:34:21 2024">
    <section stringID="User_Env">
      <table stringID="User_EnvVar">
        <column stringID="variable"/>
--- a/cpld/XC95144XL/WarpSE_pad.csv
+++ b/cpld/XC95144XL/WarpSE_pad.csv
@ -1,7 +1,7 @@
 Release 8.1i - Fit P.20131013
 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved

-10-12-2024  0:28AM
+10-12-2024  0:34AM

 NOTE: This file is designed to be imported into a spreadsheet program
 such as Microsoft Excel for viewing, printing and sorting. The comma ','
--- a/cpld/XC95144XL/WarpSE_summary.html
+++ b/cpld/XC95144XL/WarpSE_summary.html
@ -2,7 +2,7 @@
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 00:29:14)</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 00:34:54)</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
 <TD>WarpSE.xise</TD>
@ -65,9 +65,9 @@ System Settings</A>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 00:28:35 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 00:28:40 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 00:28:55 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 00:34:16 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 00:34:21 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 00:34:36 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
 <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 </TABLE>
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -77,5 +77,5 @@ System Settings</A>
 </TABLE>


-<br><center><b>Date Generated:</b> 10/12/2024 - 00:29:14</center>
+<br><center><b>Date Generated:</b> 10/12/2024 - 00:34:54</center>
 </BODY></HTML>
--- a/cpld/XC95144XL/WarpSE_xst.xrpt
+++ b/cpld/XC95144XL/WarpSE_xst.xrpt
@ -5,7 +5,7 @@
    The structure and the elements are likely to change over the next few releases.
    This means code written to parse this file will need to be revisited each subsequent release.-->

-  <application stringID="Xst" timeStamp="Sat Oct 12 00:28:30 2024">
+  <application stringID="Xst" timeStamp="Sat Oct 12 00:34:11 2024">
    <section stringID="User_Env">
      <table stringID="User_EnvVar">
        <column stringID="variable"/>
--- a/cpld/XC95144XL/_ngo/netlist.lst
+++ b/cpld/XC95144XL/_ngo/netlist.lst
@ -1,2 +1,2 @@
-C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728707315
+C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728707656
 OK
--- a/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs
+++ b/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs
@ -8,8 +8,29 @@
 <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->

 <messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/CNT.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/CS.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/FSB.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/IOBM.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/IOBS.v&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/RAM.v&quot; into library work</arg>
+</msg>
+
 <msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/SET.v&quot; into library work</arg>
 </msg>

+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE.v&quot; into library work</arg>
+</msg>
+
 </messages>

--- a/cpld/XC95144XL/iseconfig/WarpSE.xreport
+++ b/cpld/XC95144XL/iseconfig/WarpSE.xreport
@ -1,7 +1,7 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
 <header>
-  <DateModified>2024-10-12T00:28:10</DateModified>
+  <DateModified>2024-10-12T00:34:00</DateModified>
  <ModuleName>WarpSE</ModuleName>
  <SummaryTimeStamp>2024-10-09T06:57:43</SummaryTimeStamp>
  <SavedFilePath>C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
--- a/cpld/XC95144XL/usage_statistics_webtalk.html
+++ b/cpld/XC95144XL/usage_statistics_webtalk.html
@ -17,7 +17,7 @@
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
-<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">a162ca09ecd44e88bfd7624cefa5a602</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
+<TD><xtag-property name="RandomID">b3a7c111c3094ca7bbfba225dd37199f</xtag-property>.<xtag-property name="ProjectID">318d6704338848bcaa06ac32b5dc469b</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
 <TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
 <TD><xtag-property name="TargetPackage"></xtag-property></TD>
 </TR>
@ -29,7 +29,7 @@
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
-<TD><xtag-property name="Date Generated">2024-10-12T00:29:46</xtag-property></TD>
+<TD><xtag-property name="Date Generated">2024-10-12T00:39:12</xtag-property></TD>
 <TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
 <TD><xtag-property name="ToolFlow">IMPACT</xtag-property></TD>
 </TR>
--- a/cpld/XC95144XL/webtalk.log
+++ b/cpld/XC95144XL/webtalk.log
@ -3,7 +3,7 @@ Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

 Project Information
 --------------------
-ProjectID=a162ca09ecd44e88bfd7624cefa5a602
+ProjectID=318d6704338848bcaa06ac32b5dc469b
 ProjectIteration=1

 WebTalk Summary
--- a/cpld/XC95144XL/webtalk_impact.xml
+++ b/cpld/XC95144XL/webtalk_impact.xml
@ -3,9 +3,9 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="impact" timeStamp="Sat Oct 12 00:29:45 2024">
+<application name="impact" timeStamp="Sat Oct 12 00:39:12 2024">
 <section name="Project Information" visible="false">
-<property name="ProjectID" value="a162ca09ecd44e88bfd7624cefa5a602"/>
+<property name="ProjectID" value="318d6704338848bcaa06ac32b5dc469b"/>
 <property name="ProjectIteration" value="1"/>
 </section>
 <section name="iMPACT Project Info" visible="true">
--- a/cpld/XC95144XL/webtalk_pn.xml
+++ b/cpld/XC95144XL/webtalk_pn.xml
@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pn" timeStamp="Sat Oct 12 00:28:29 2024">
+<application name="pn" timeStamp="Sat Oct 12 00:34:10 2024">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="B70E14F6F6B943E9BF9FD5113EA04D70" type="project"/>
 <property name="ProjectIteration" value="0" type="project"/>
--- a/cpld/XC95144XL/xst/work/hdllib.ref
+++ b/cpld/XC95144XL/xst/work/hdllib.ref
@ -1,8 +1,8 @@
-MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728707310
-MO CS NULL ../CS.v vlg22/_c_s.bin 1728707310
-MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728707310
-MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728707310
-MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728707310
-MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728707310
-MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728707310
-MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728707310
+MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728707651
+MO CS NULL ../CS.v vlg22/_c_s.bin 1728707651
+MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728707651
+MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728707651
+MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728707651
+MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728707651
+MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728707651
+MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728707651
--- a/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin
+++ b/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin
--- a/cpld/XC95144XL/xst/work/vlg22/_c_s.bin
+++ b/cpld/XC95144XL/xst/work/vlg22/_c_s.bin
--- a/cpld/XC95144XL/xst/work/vlg37/_f_s_b.bin
+++ b/cpld/XC95144XL/xst/work/vlg37/_f_s_b.bin
--- a/cpld/XC95144XL/xst/work/vlg48/_s_e_t.bin
+++ b/cpld/XC95144XL/xst/work/vlg48/_s_e_t.bin
--- a/cpld/XC95144XL/xst/work/vlg52/_warp_s_e.bin
+++ b/cpld/XC95144XL/xst/work/vlg52/_warp_s_e.bin
--- a/cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin
+++ b/cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin
--- a/cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin
+++ b/cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin
--- a/cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin
+++ b/cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin