diff --git a/cpld/CFG_A.v b/cpld/CFG_A.v
index 3bac613..75d4c56 100644
--- a/cpld/CFG_A.v
+++ b/cpld/CFG_A.v
@@ -5,6 +5,12 @@ module CFG(
 	inout GA21,
 	inout GA20,
 	output SlowdownIOWriteGate,
+	input [11:10] RA,
+	input [19:18] BA,
+	input RowA10,
+	output RA11_BA19,
+	output RA10,
+	inout nBG_BA18,
 	input DBG0_ROMWS,
 	input DBG1_RAMWS,
 	input DBG4_IOWS,
@@ -13,16 +19,20 @@ module CFG(
 	output IOWS);
 	
 	assign GA23 = 1'bZ;
-	wire GA23Gate = 
+	wire GA22Gate = 
 		(A[23:20]==4'h6) ||
 		(A[23:20]==4'h7 &&  A[19:16]!=4'hF) ||
 		(A[23:20]==4'h5 && !A[19]);
-	assign GA22 = ) ? 1'b0 : A[23];
+	assign GA22 = GA22Gate ? 1'b0 : A[23];
 	assign GA21 = 1'bZ;
 	assign GA20 = 1'bZ;
 
 	assign SlowdownIOWriteGate = 1;
 
+	output RA11_BA19 = BA[19];
+	output RA10 = RowA10;
+	assign nBG_BA18 = BA[18];
+
 	assign ROMWS = DBG0_ROMWS;
 	assign RAMWS = DBG1_RAMWS;
 	assign IOWS = DBG4_IOWS;
diff --git a/cpld/CFG_Prototype.v b/cpld/CFG_Prototype.v
index 4341267..971538c 100644
--- a/cpld/CFG_Prototype.v
+++ b/cpld/CFG_Prototype.v
@@ -5,6 +5,12 @@ module CFG(
 	inout GA21,
 	inout GA20,
 	output SlowdownIOWriteGate,
+	input [11:10] RA,
+	input [19:18] BA,
+	input RowA10,
+	output RA11_BA19,
+	output RA10,
+	inout nBG_BA18,
 	input DBG0_ROMWS,
 	input DBG1_RAMWS,
 	input DBG4_IOWS,
@@ -17,8 +23,16 @@ module CFG(
 	assign GA21 = 1'bZ;
 	assign GA20 = 1'bZ;
 
+
+
+
+
 	assign SlowdownIOWriteGate = 0;
-	
+
+	output RA11_BA19 = RA[11];
+	output RA10 = RA[10];
+	assign nBG_BA18 = 1'bZ;
+
 	assign ROMWS = 0;
 	assign RAMWS = 0;
 	assign IOWS = 0;
diff --git a/cpld/RAM.v b/cpld/RAM.v
index 7d7b557..5afa46f 100644
--- a/cpld/RAM.v
+++ b/cpld/RAM.v
@@ -6,6 +6,8 @@ module RAM(
 	input BACT, input BACTr,
 	/* Select and ready signals */
 	input RAMCS, input RAMCS0X, input ROMCS, input ROMCS4X,
+	/* ROM size inputs */
+	input [1:0] ROMSize, input [1:0] ROMBank,
 	/* RAM/ROM wait state inputs */
 	input RAMWS, input ROMWS,
 	/* RAM/ROM ready output */
@@ -13,8 +15,10 @@ module RAM(
 	/* Refresh Counter Interface */
 	input RefReqIn, input RefUrgIn,
 	/* DRAM interface */
-	output [11:0] RA, output nRAS, output reg nCAS,
+	output nRAS, output reg nCAS,
 	output nLWE, output nUWE, output nOE,
+	/* DRAM address and ROM bank address */
+	output [11:0] RA, output RowA10, output [19:18] BA,
 	/* NOR flash interface */
 	output nROMOE, output nROMWE);
 
@@ -43,7 +47,7 @@ module RAM(
 	assign nUWE = !(!nUDS && RASEL && !nWE);
 	
 	/* RAM /OE control */
-	assign nOE = 0;
+	assign nOE = !nWE;
 	/*reg nOEr; assign nOE = nOEr;
 	always @(posedge CLK, posedge nAS) begin
 		if (nAS) nOEr <= 1;
@@ -63,11 +67,12 @@ module RAM(
 
 	/* RAM address mux (and ROM address on RA8) */
 	// RA11 doesn't do anything so both should be identical.
-	assign RA[11] = !RASEL ? A[19] : A[20]; // ROM address 19
+	assign RA[11] =   !RASEL ? A[19] : A[20]; // ROM address 19
 	assign RA[03] = !RASEL ? A[19] : A[20];
 	// RA10 has only row so different rows but same column.
 	assign RA[10] = !RASEL ? A[17] : A[07];
 	assign RA[02] = !RASEL ? A[16] : A[07];
+	assign RowA10 = A[17];
 	// Remainder of RA bus is unpaired
 	assign RA[09] = !RASEL ? A[15] : A[08];
 	assign RA[08] = !RASEL ? A[18] : A[21]; // ROM address 18
@@ -78,6 +83,8 @@ module RAM(
 	assign RA[01] = !RASEL ? A[10] : A[02];
 	assign RA[00] = !RASEL ? A[09] : A[01];
 
+	assign BA[19:18] = 2'b11;
+
 	wire RS0toRef = // Refresh during first clock of non-RAM access
 					(RefReq &&  BACT && !BACTr && !RAMCS0X) ||
 					// Urgent refresh while bus inactive
@@ -89,14 +96,14 @@ module RAM(
 	always @(posedge CLK) begin
 		case (RS[2:0])
 			0: begin // Idle/ready
-				if (RAMReady) begin // Continue accessing RAM
+				if (RAMReady) begin // After wait state
 					RS <= 1; // Continue accessing RAM
 					RAMReady <= 1;
 					RASEL <= 1;
 					RefCAS <= 0;
 					RASEN <= 1;
 				end else if (RS0toRAM) begin // Wait state
-					RS <= 0;
+					RS <= RAMWS ? 0 : 1;
 					RAMReady <= 1;
 					RASEL <= 0;
 					RefCAS <= 0;