New RAM controller
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Zane Kaminski
parent
d4e0008854
commit
22c3dd55ac
111
cpld/RAM.v
111
cpld/RAM.v
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@ -1,6 +1,7 @@
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module RAM(
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/* MC68HC000 interface */
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input CLK, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS,
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input CLK, input [21:1] A, input nWE,
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input nAS, input nLDS, input nUDS, input nDTACK,
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/* AS cycle detection */
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input BACT,
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/* Select and ready signals */
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@ -10,7 +11,11 @@ module RAM(
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
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/* BACT and /DTACK registration */
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reg BACTr; always @(posedge CLK) BACTr <= BACT;
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reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
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/* RAM control state */
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reg [3:0] RS = 0;
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reg RASEN = 0;
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@ -30,13 +35,15 @@ module RAM(
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/* RAM control signals */
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
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assign nOE = !(!nAS && nWE); // Shared with ROM
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assign nLWE = !(!nLDS && !nWE && RASEL);
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assign nUWE = !(!nUDS && !nWE && RASEL);
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/* ROM control signals */
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assign nROMCS = !ROMCS;
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assign nROMWE = !((!nAS && !nWE));
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assign nROMWE = !(!nAS && !nWE);
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/* Shared /OE control */
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always @(posedge CLK) nOE <= !(BACT && !nWE && !(BACTr && DTACKr));
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/* RAM address mux (and ROM address on RA8) */
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// RA11 doesn't do anything so both should be identical.
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@ -55,66 +62,59 @@ module RAM(
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[00] = !RASEL ? A[09] : A[01];
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reg BACTr; always @(posedge CLK) BACTr <= BACT;
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always @(posedge CLK) begin
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case (RS[3:0])
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0: begin
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if (( BACT && !BACTr && !RAMCS0X && RefReq) ||
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(!BACT && RefUrg) ||
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( BACT && RefUrg && !RAMCS0X) ||
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(!RASEN)) begin
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0: begin // Idle/ready
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if ((RefReq && BACT && !BACTr && !RAMCS0X) ||
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(RefUrg && !RASEN) ||
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(RefUrg && BACT && !RAMCS0X) ||
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(RefUrg && !BACT)) begin // Go to refresh
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RS <= 8;
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RASEL <= 0;
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CAS <= 1;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end else if (BACT && RAMCS && RASEN) begin
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end else if (BACT && RAMCS && RASEN) begin // Access RAM
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RS <= 1;
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RASEL <= 1;
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CAS <= 1;
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RASrr <= 1;
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RASEN <= 1;
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RAMReady <= 1;
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end else begin
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end else begin // Stay in idle/ready
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RS <= 0;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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end 1: begin
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end 1: begin // RAM access
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RS <= 2;
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RASEL <= 1;
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CAS <= 1;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end 2: begin
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RS <= 3;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end 3: begin
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if (BACT) begin
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end 2: begin // finish RAM access
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if (DTACKr) begin // Cycle ending
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RS <= 3;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end else if (RefUrg) begin
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RS <= 8;
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RASEL <= 0;
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CAS <= 1;
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end else begin
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RS <= 2;
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RASEL <= 1;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end
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end 3: begin //AS cycle complete
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if (RefUrg) begin // Refresh RAS
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RS <= 4;
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RASEL <= 0;
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RASrr <= 1;
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RASEN <= 0;
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RAMReady <= 0;
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end else begin
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end else begin // Cycle ended so go abck to idle/ready
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RS <= 0;
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RASEL <= 0;
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CAS <= 0;
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@ -122,52 +122,55 @@ module RAM(
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RASEN <= 1;
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RAMReady <= 1;
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end
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end 8: begin
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RS <= 9;
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end 8: begin // Refresh CAS
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end 9: begin // Refresh RAS I
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RS <= 5;
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RASEL <= 0;
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CAS <= 1;
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RASrr <= 1;
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RASEN <= 0;
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RAMReady <= 0;
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end 9: begin
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RS <= 10;
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end 10: begin // Refresh RAS II
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RS <= 6;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 1;
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RASEN <= 0;
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RAMReady <= 0;
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end 10: begin
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RS <= 11;
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end 11: begin // Refresh precharge I
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RS <= 6;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end 11: begin
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end 12: begin // Refresh precharge II
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RS <= 15;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end 15: begin
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end 15: begin // Reenable RAM and go to idle/ready
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RS <= 0;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end default: begin
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RS <= 0;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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endcase
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end
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always @(negedge CLK) RASrf <= RS==1;
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always @(negedge CLK) nCAS <= !CAS;
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always @(negedge CLK) begin
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RASrf <= RS==1;
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case (RS[2:0])
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0: nCAS <= 1;
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1: nCAS <= 0;
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2: nCAS <= DTACKr;
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3: nCAS <= !RefUrg;
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4: nCAS <= !RefUrg;
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5: nCAS <= 1;
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6: nCAS <= 1;
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7: nCAS <= 1;
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endcase
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end
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endmodule
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@ -71,7 +71,8 @@ module WarpSE(
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wire RAMReady;
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RAM ram(
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/* MC68HC000 interface */
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FCLK, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
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FCLK, A_FSB[21:1], nWE_FSB,
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nAS_FSB, nLDS_FSB, nUDS_FSB, nDTACK_FSB,
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/* AS cycle detection */
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BACT,
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/* Select and ready signals */
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