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New RAM controller

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This commit is contained in:
Zane Kaminski 2023-04-10 19:28:13 -04:00
parent d4e0008854
commit 22c3dd55ac
2 changed files with 59 additions and 55 deletions
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111
cpld/RAM.v
View File

@ -1,6 +1,7 @@
module RAM(
/* MC68HC000 interface */
input CLK, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS,
input CLK, input [21:1] A, input nWE,
input nAS, input nLDS, input nUDS, input nDTACK,
/* AS cycle detection */
input BACT,
/* Select and ready signals */
@ -10,7 +11,11 @@ module RAM(
/* DRAM and NOR flash interface */
output [11:0] RA, output nRAS, output reg nCAS,
output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
/* BACT and /DTACK registration */
reg BACTr; always @(posedge CLK) BACTr <= BACT;
reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
/* RAM control state */
reg [3:0] RS = 0;
reg RASEN = 0;
@ -30,13 +35,15 @@ module RAM(
/* RAM control signals */
assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
assign nOE = !(!nAS && nWE); // Shared with ROM
assign nLWE = !(!nLDS && !nWE && RASEL);
assign nUWE = !(!nUDS && !nWE && RASEL);
/* ROM control signals */
assign nROMCS = !ROMCS;
assign nROMWE = !((!nAS && !nWE));
assign nROMWE = !(!nAS && !nWE);
/* Shared /OE control */
always @(posedge CLK) nOE <= !(BACT && !nWE && !(BACTr && DTACKr));
/* RAM address mux (and ROM address on RA8) */
// RA11 doesn't do anything so both should be identical.
@ -55,66 +62,59 @@ module RAM(
assign RA[01] = !RASEL ? A[10] : A[02];
assign RA[00] = !RASEL ? A[09] : A[01];
reg BACTr; always @(posedge CLK) BACTr <= BACT;
always @(posedge CLK) begin
case (RS[3:0])
0: begin
if (( BACT && !BACTr && !RAMCS0X && RefReq) ||
(!BACT && RefUrg) ||
( BACT && RefUrg && !RAMCS0X) ||
(!RASEN)) begin
0: begin // Idle/ready
if ((RefReq && BACT && !BACTr && !RAMCS0X) ||
(RefUrg && !RASEN) ||
(RefUrg && BACT && !RAMCS0X) ||
(RefUrg && !BACT)) begin // Go to refresh
RS <= 8;
RASEL <= 0;
CAS <= 1;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 0;
end else if (BACT && RAMCS && RASEN) begin
end else if (BACT && RAMCS && RASEN) begin // Access RAM
RS <= 1;
RASEL <= 1;
CAS <= 1;
RASrr <= 1;
RASEN <= 1;
RAMReady <= 1;
end else begin
end else begin // Stay in idle/ready
RS <= 0;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 1;
RAMReady <= 1;
end
end 1: begin
end 1: begin // RAM access
RS <= 2;
RASEL <= 1;
CAS <= 1;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 1;
end 2: begin
RS <= 3;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 1;
end 3: begin
if (BACT) begin
end 2: begin // finish RAM access
if (DTACKr) begin // Cycle ending
RS <= 3;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 1;
end else if (RefUrg) begin
RS <= 8;
RASEL <= 0;
CAS <= 1;
end else begin
RS <= 2;
RASEL <= 1;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 1;
end
end 3: begin //AS cycle complete
if (RefUrg) begin // Refresh RAS
RS <= 4;
RASEL <= 0;
RASrr <= 1;
RASEN <= 0;
RAMReady <= 0;
end else begin
end else begin // Cycle ended so go abck to idle/ready
RS <= 0;
RASEL <= 0;
CAS <= 0;
@ -122,52 +122,55 @@ module RAM(
RASEN <= 1;
RAMReady <= 1;
end
end 8: begin
RS <= 9;
end 8: begin // Refresh CAS
end 9: begin // Refresh RAS I
RS <= 5;
RASEL <= 0;
CAS <= 1;
RASrr <= 1;
RASEN <= 0;
RAMReady <= 0;
end 9: begin
RS <= 10;
end 10: begin // Refresh RAS II
RS <= 6;
RASEL <= 0;
CAS <= 0;
RASrr <= 1;
RASEN <= 0;
RAMReady <= 0;
end 10: begin
RS <= 11;
end 11: begin // Refresh precharge I
RS <= 6;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 0;
end 11: begin
end 12: begin // Refresh precharge II
RS <= 15;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 0;
RAMReady <= 0;
end 15: begin
end 15: begin // Reenable RAM and go to idle/ready
RS <= 0;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 1;
RAMReady <= 1;
end default: begin
RS <= 0;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
RASEN <= 1;
RAMReady <= 1;
end
endcase
end
always @(negedge CLK) RASrf <= RS==1;
always @(negedge CLK) nCAS <= !CAS;
always @(negedge CLK) begin
RASrf <= RS==1;
case (RS[2:0])
0: nCAS <= 1;
1: nCAS <= 0;
2: nCAS <= DTACKr;
3: nCAS <= !RefUrg;
4: nCAS <= !RefUrg;
5: nCAS <= 1;
6: nCAS <= 1;
7: nCAS <= 1;
endcase
end
endmodule

3
cpld/WarpSE.v
View File

@ -71,7 +71,8 @@ module WarpSE(
wire RAMReady;
RAM ram(
/* MC68HC000 interface */
FCLK, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
FCLK, A_FSB[21:1], nWE_FSB,
nAS_FSB, nLDS_FSB, nUDS_FSB, nDTACK_FSB,
/* AS cycle detection */
BACT,
/* Select and ready signals */