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Warp-SE
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This commit is contained in:
Zane Kaminski 2023-04-09 05:11:26 -04:00
parent 625f7fd014
commit 23e3681063
30 changed files with 1267 additions and 1373 deletions
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2
cpld/XC95144XL/WarpSE.bld
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@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 155428 kilobytes
Total memory usage is 154596 kilobytes
Writing NGD file "WarpSE.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec

7
cpld/XC95144XL/WarpSE.cmd_log
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@ -653,3 +653,10 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm

21
cpld/XC95144XL/WarpSE.gise
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@ -61,17 +61,16 @@
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1680947820" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1680947820">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1680947820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1680947820">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1681028056" xil_pn:in_ck="-4320870779658513146" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681028048">
<transform xil_pn:end_ts="1681030881" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681030873">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="WarpSE.lso"/>
<outfile xil_pn:name="WarpSE.ngc"/>
<outfile xil_pn:name="WarpSE.ngr"/>
@ -88,21 +87,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1681028061" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681028056">
<transform xil_pn:end_ts="1681030886" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681030881">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="WarpSE.bld"/>
<outfile xil_pn:name="WarpSE.ngd"/>
<outfile xil_pn:name="WarpSE_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1681028081" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681028061">
<transform xil_pn:end_ts="1681030912" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681030886">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="WarpSE.gyd"/>
<outfile xil_pn:name="WarpSE.mfd"/>
<outfile xil_pn:name="WarpSE.nga"/>
@ -117,18 +114,14 @@
<outfile xil_pn:name="WarpSE_html"/>
<outfile xil_pn:name="WarpSE_pad.csv"/>
</transform>
<transform xil_pn:end_ts="1681028083" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681028081">
<transform xil_pn:end_ts="1681030914" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681030912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="WarpSE.jed"/>
</transform>
<transform xil_pn:end_ts="1680947378" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1680947375">
<status xil_pn:value="AbortedRun"/>
<transform xil_pn:end_ts="1681030918" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1681030915">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>

2
cpld/XC95144XL/WarpSE.jed
View File

@ -1,5 +1,5 @@
Programmer Jedec Bit Map
Date Extracted: Sun Apr 09 04:14:42 2023
Date Extracted: Sun Apr 09 05:01:53 2023
QF93312*
QP100*

2
cpld/XC95144XL/WarpSE.nga
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2
cpld/XC95144XL/WarpSE.ngc
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File diff suppressed because one or more lines are too long

2
cpld/XC95144XL/WarpSE.ngd
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File diff suppressed because one or more lines are too long

2
cpld/XC95144XL/WarpSE.ngr
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File diff suppressed because one or more lines are too long

2
cpld/XC95144XL/WarpSE.pad
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@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
4- 9-2023 4:14AM
4- 9-2023 5:01AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'

2
cpld/XC95144XL/WarpSE.rpt
View File

@ -1,7 +1,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: WarpSE Date: 4- 9-2023, 4:14AM
Design Name: WarpSE Date: 4- 9-2023, 5:01AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful

6
cpld/XC95144XL/WarpSE.syr
View File

@ -272,8 +272,8 @@ Synthesizing Unit <CNT>.
Found 1-bit register for signal <nRESout>.
Found 1-bit register for signal <AoutOE>.
Found 1-bit register for signal <QoSReady>.
Found 2-bit adder for signal <$add0000> created at line 65.
Found 12-bit adder for signal <$add0001> created at line 66.
Found 2-bit adder for signal <$add0000> created at line 66.
Found 12-bit adder for signal <$add0001> created at line 67.
Found 2-bit register for signal <Er>.
Found 12-bit register for signal <LTimer>.
Found 1-bit register for signal <LTimerTC>.
@ -515,7 +515,7 @@ Total CPU time to Xst completion: 5.09 secs
-->
Total memory usage is 266948 kilobytes
Total memory usage is 267012 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)

692
cpld/XC95144XL/WarpSE.tspec
View File

@ -54,8 +54,8 @@ AUTO_TS_P2P:FROM:A_FSB<11>:TO:RA<4>:1
AUTO_TS_P2P:FROM:FCLK:TO:RA<4>:1
AUTO_TS_P2P:FROM:A_FSB<3>:TO:RA<4>:1
AUTO_TS_F2P:FROM:ram/RASEL.Q:TO:RA<4>:1
AUTO_TS_P2P:FROM:FCLK:TO:RA<5>:1
AUTO_TS_P2P:FROM:A_FSB<12>:TO:RA<5>:1
AUTO_TS_P2P:FROM:FCLK:TO:RA<5>:1
AUTO_TS_P2P:FROM:A_FSB<4>:TO:RA<5>:1
AUTO_TS_F2P:FROM:ram/RASEL.Q:TO:RA<5>:1
AUTO_TS_P2P:FROM:A_FSB<13>:TO:RA<6>:1
@ -133,114 +133,80 @@ AUTO_TS_P2F:FROM:FCLK:TO:RefUrg.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:RefUrg.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:RefUrg.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:RefUrg.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<5>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<5>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<5>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<5>.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<6>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<6>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<6>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<6>.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<7>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<7>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<7>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<7>.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<8>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<8>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<8>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<8>.CE:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<12>.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<0>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<0>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<0>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<0>.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<4>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<4>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<4>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<4>.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<9>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<9>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<9>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<9>.CE:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:cnt/LTimer<0>.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:cnt/LTimer<0>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<0>.Q:TO:cnt/Timer<0>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<0>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<0>.D:1
@ -250,115 +216,153 @@ AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<0>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<0>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/Timer<0>.CE:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd7.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/BACTr.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RAMEN.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/Once.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd4.Q:TO:ram/RAMEN.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RAMEN.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/RAMEN.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:ram/RAMEN.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/Sent.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:iobs/Sent.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimer<10>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<10>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<10>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<10>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<10>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<10>.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<11>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<11>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<11>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<11>.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<1>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<1>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<1>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<1>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<1>.CE:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<2>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<2>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<2>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<2>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<2>.CE:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<3>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<3>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<3>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<3>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<3>.CE:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<4>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<4>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<5>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<5>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<6>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<6>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<7>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<7>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<8>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<8>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimer<9>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<9>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<0>.Q:TO:cnt/Timer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<1>.Q:TO:cnt/Timer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<1>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/Timer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<0>.Q:TO:cnt/Timer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<1>.Q:TO:cnt/Timer<1>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/Timer<1>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<1>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<1>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/Timer<1>.CE:1
AUTO_TS_F2F:FROM:cnt/Timer<0>.Q:TO:cnt/Timer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<1>.Q:TO:cnt/Timer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<2>.Q:TO:cnt/Timer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<1>.Q:TO:cnt/Timer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<2>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/Timer<2>.D:1
@ -366,33 +370,23 @@ AUTO_TS_P2F:FROM:FCLK:TO:cnt/Timer<2>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<2>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<2>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/Timer<2>.CE:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd7.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RAMEN.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/Once.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd4.Q:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/RAMEN.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RAMEN.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/RAMEN.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:ram/RefDone.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/RefDone.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RefDone.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RefDone.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RefDone.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RefDone.D:1
AUTO_TS_F2F:FROM:QoSReady.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<0>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<1>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<2>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<3>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<12>.Q:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:FCLK:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/Timer<0>.Q:TO:RefReq.D:1
AUTO_TS_F2F:FROM:cnt/Timer<1>.Q:TO:RefReq.D:1
AUTO_TS_F2F:FROM:cnt/Timer<2>.Q:TO:RefReq.D:1
@ -401,33 +395,31 @@ AUTO_TS_P2F:FROM:FCLK:TO:RefReq.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:RefReq.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:RefReq.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:RefReq.CE:1
AUTO_TS_F2F:FROM:cnt/LTimer<12>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:cnt/LTimer<12>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<12>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<12>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<12>.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<12>.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<12>.CE:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimer<11>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimer<11>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<0>.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<1>.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<2>.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<3>.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Timer<3>.Q:TO:cnt/Timer<3>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/Timer<3>.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Timer<3>.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/Timer<3>.CE:1
@ -439,35 +431,31 @@ AUTO_TS_F2F:FROM:cs/ODCSr.Q:TO:cs/nOverlay.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:cs/nOverlay.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cs/nOverlay.D:1
AUTO_TS_P2F:FROM:nRES:TO:cs/nOverlay.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:iobs/IORW1.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:iobs/IORW1.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:IONPReady.Q:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:iobs/IORW1.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:iobs/IORW1.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:IONPReady.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:IONPReady.D:1
AUTO_TS_F2F:FROM:IONPReady.Q:TO:IONPReady.D:1
AUTO_TS_F2F:FROM:iobs/IODONEr.Q:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:FCLK:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IONPReady.D:1
@ -477,56 +465,30 @@ AUTO_TS_P2F:FROM:A_FSB<18>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:FCLK:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:IONPReady.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IONPReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<12>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/LTimerTC.CE:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/LTimerTC.CE:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/LTimerTC.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimerTC.CE:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IONPReady.D:1
AUTO_TS_F2F:FROM:iobs/Load1.Q:TO:iobs/IOL1.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/IOL1.CE:1
AUTO_TS_F2F:FROM:iobs/Load1.Q:TO:iobs/IOU1.CE:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/IOU1.CE:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/Once.D:1
AUTO_TS_F2F:FROM:ram/Once.Q:TO:ram/Once.D:1
AUTO_TS_F2F:FROM:ram/RAMEN.Q:TO:ram/Once.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/Once.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:ram/Once.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/Once.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/Once.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/Once.D:1
AUTO_TS_F2F:FROM:ram/Once.Q:TO:ram/Once.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:ram/Once.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:ram/Once.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/Once.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/Once.D:1
AUTO_TS_F2F:FROM:nBERR_FSB_OBUF.Q:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:nBERR_FSB_OBUF.Q:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:IOBERR.Q:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:FCLK:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:C8M:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:QoSReady.Q:TO:nVPA_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:FCLK:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:nBERR_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:IONPReady.Q:TO:nVPA_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:QoSReady.Q:TO:nVPA_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:nVPA_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:nVPA_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:nVPA_FSB_OBUF.D:1
@ -556,52 +518,45 @@ AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:iobs/TS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:iobs/TS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:iobs/IOACTr.Q:TO:iobs/TS_FSM_FFd1.D:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/TS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:iobs/IOACTr.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:iobs/TS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:ram/BACTr.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd4.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:ram/RAMEN.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:ram/RAMEN.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/RS_FSM_FFd8.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:cnt/LTimerTC.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:cnt/nIPL2r.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:cnt/LTimerTC.Q:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/IS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/IS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:cnt/Er<1>.Q:TO:cnt/IS_FSM_FFd2.D:1
@ -619,36 +574,30 @@ AUTO_TS_P2F:FROM:A_FSB<22>:TO:ram/RS_FSM_FFd7.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/RS_FSM_FFd7.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RS_FSM_FFd7.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:iobs/Load1.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/Load1.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:iobs/Load1.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:iobs/Load1.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:iobs/Load1.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:FCLK:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:iobs/Load1.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:iobs/Load1.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:cnt/WS<0>.D:1
AUTO_TS_F2F:FROM:cnt/WS<0>.Q:TO:cnt/WS<0>.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:cnt/WS<0>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/WS<0>.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:IOL0.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IOL0.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:IOL0.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IOL0.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:IOL0.D:1
AUTO_TS_F2F:FROM:IOL0.Q:TO:IOL0.D:1
AUTO_TS_F2F:FROM:iobs/IOL1.Q:TO:IOL0.D:1
@ -657,50 +606,38 @@ AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:IOL0.D:1
AUTO_TS_P2F:FROM:FCLK:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IOL0.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IOL0.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:IOL0.D:1
AUTO_TS_P2F:FROM:nLDS_FSB:TO:IOL0.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:IOU0.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:iobs/IOU1.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:IOU0.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:IOU0.D:1
AUTO_TS_P2F:FROM:FCLK:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:IOU0.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IOU0.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:IOU0.D:1
AUTO_TS_P2F:FROM:nUDS_FSB:TO:IOU0.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:cnt/WS<1>.D:1
AUTO_TS_F2F:FROM:cnt/WS<0>.Q:TO:cnt/WS<1>.D:1
@ -722,21 +659,16 @@ AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RS_FSM_FFd4.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RS_FSM_FFd4.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd7.Q:TO:ram/RS_FSM_FFd5.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RS_FSM_FFd5.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:ram/BACTr.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd5.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:ram/RAMEN.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/RS_FSM_FFd6.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:iobs/IORW1.Q:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:IORDREQ.D:1
@ -744,41 +676,71 @@ AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:iobs/IOACTr.Q:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:IORDREQ.Q:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:FCLK:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:IORDREQ.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:IORDREQ.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/Sent.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/IORW1.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd1.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/IOACTr.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:IOWRREQ.Q:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/IOACTr.Q:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:iobs/IORW1.Q:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:FCLK:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:IOWRREQ.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:IOWRREQ.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<0>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<1>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<2>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/WS<3>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:QoSReady.Q:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:FCLK:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<10>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<11>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<8>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<9>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<15>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<12>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:QoSReady.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:QoSReady.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:RAMReady.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd4.Q:TO:RAMReady.D:1
AUTO_TS_F2F:FROM:RAMReady.Q:TO:RAMReady.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:RAMReady.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:RAMReady.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:RAMReady.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:RAMReady.D:1
AUTO_TS_P2F:FROM:FCLK:TO:RAMReady.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:RAMReady.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:cnt/WS<3>.D:1
AUTO_TS_F2F:FROM:cnt/WS<3>.Q:TO:cnt/WS<3>.D:1
AUTO_TS_F2F:FROM:cnt/WS<0>.Q:TO:cnt/WS<3>.D:1
@ -793,8 +755,25 @@ AUTO_TS_F2F:FROM:ram/RS_FSM_FFd3.Q:TO:ram/RS_FSM_FFd2.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RS_FSM_FFd2.D:1
AUTO_TS_F2F:FROM:iobs/TS_FSM_FFd2.Q:TO:ALE0S.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ALE0S.D:1
AUTO_TS_F2F:FROM:iobs/Clear1.Q:TO:IOPWReady.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:IOPWReady.D:1
AUTO_TS_F2F:FROM:iobs/Load1.Q:TO:IOPWReady.D:1
AUTO_TS_P2F:FROM:FCLK:TO:IOPWReady.D:1
AUTO_TS_F2F:FROM:cnt/Er<0>.Q:TO:cnt/Er<1>.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/Er<1>.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<0>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<1>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<2>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<10>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<3>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<4>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<5>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<6>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<7>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<8>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<9>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:cnt/LTimer<11>.Q:TO:cnt/LTimerTC.D:1
AUTO_TS_P2F:FROM:FCLK:TO:cnt/LTimerTC.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:cs/ODCSr.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:cs/ODCSr.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:cs/ODCSr.D:1
@ -805,23 +784,19 @@ AUTO_TS_P2F:FROM:FCLK:TO:cs/ODCSr.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd1.Q:TO:nRESout.D:1
AUTO_TS_F2F:FROM:cnt/IS_FSM_FFd2.Q:TO:nRESout.D:1
AUTO_TS_P2F:FROM:FCLK:TO:nRESout.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/BACTr.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/BACTr.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/BACTr.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd7.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd6.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RefDone.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd5.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd8.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:RefReq.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/BACTr.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RAMEN.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:cs/nOverlay.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:RefUrg.Q:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd5.Q:TO:ram/CAS.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/CAS.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:ram/CAS.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:ram/CAS.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:ram/CAS.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:ram/CAS.D:1
AUTO_TS_F2F:FROM:ram/RS_FSM_FFd7.Q:TO:ram/RASrf.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RASrf.D:1
@ -839,19 +814,24 @@ AUTO_TS_F2F:FROM:ram/RS_FSM_FFd2.Q:TO:ram/RS_FSM_FFd1.D:1
AUTO_TS_P2F:FROM:FCLK:TO:ram/RS_FSM_FFd1.D:1
AUTO_TS_F2F:FROM:ram/CAS.Q:TO:nCAS_OBUF.D:1
AUTO_TS_P2F:FROM:FCLK:TO:nCAS_OBUF.D:1
AUTO_TS_F2F:FROM:QoSReady.Q:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:IONPReady.Q:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:RAMReady.Q:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:IOPWReady.Q:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:QoSReady.Q:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:fsb/ASrf.Q:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<22>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:FCLK:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<23>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<21>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<20>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<19>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<18>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<17>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<16>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<13>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:nWE_FSB:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:A_FSB<14>:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:nAS_FSB:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_P2F:FROM:FCLK:TO:nDTACK_FSB_OBUF.D:1
AUTO_TS_F2F:FROM:iobs/Load1.Q:TO:nADoutLE1_OBUF.D:1
AUTO_TS_F2F:FROM:nADoutLE1_OBUF.Q:TO:nADoutLE1_OBUF.D:1
AUTO_TS_F2F:FROM:iobs/Clear1.Q:TO:nADoutLE1_OBUF.D:1

173
cpld/XC95144XL/WarpSE.xise
View File

@ -43,142 +43,64 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../WarpSE.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../WarpSE-XC95144XL.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-10" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-10" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc95144xl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|WarpSE" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../WarpSE.v" xil_pn:valueState="non-default"/>
@ -190,15 +112,8 @@
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
@ -210,25 +125,14 @@
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@ -236,16 +140,11 @@
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@ -253,75 +152,35 @@
<property xil_pn:name="Output File Name" xil_pn:value="WarpSE" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="TQ100" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="WarpSE_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="WarpSE_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="WarpSE_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="WarpSE_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
@ -330,33 +189,18 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -366,35 +210,22 @@
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->

2
cpld/XC95144XL/WarpSE.xml
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2
cpld/XC95144XL/WarpSE_html/fit/ascii.htm
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@ -3,7 +3,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: WarpSE Date: 4- 9-2023, 4:14AM
Design Name: WarpSE Date: 4- 9-2023, 5:01AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful

2
cpld/XC95144XL/WarpSE_html/fit/summary.htm
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@ -30,7 +30,7 @@
<tr>
<td width="40%"> <b>Date</b>
</td>
<td width="60%">  4- 9-2023, 4:14AM</td>
<td width="60%">  4- 9-2023, 5:01AM</td>
</tr>
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">

1642
cpld/XC95144XL/WarpSE_html/tim/timing_report.htm
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2
cpld/XC95144XL/WarpSE_ngdbuild.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sun Apr 09 04:14:20 2023">
<application stringID="NgdBuild" timeStamp="Sun Apr 09 05:01:25 2023">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>

2
cpld/XC95144XL/WarpSE_pad.csv
View File

@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
4- 9-2023 4:14AM
4- 9-2023 5:01AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','

1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 4- 9-2023 4:14AM 4- 9-2023 5:01AM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.

10
cpld/XC95144XL/WarpSE_summary.html
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@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (04/09/2023 - 04:14:44)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (04/09/2023 - 05:01:58)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpSE.xise</TD>
@ -65,9 +65,9 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Apr 9 04:14:15 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sun Apr 9 04:14:20 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sun Apr 9 04:14:35 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>6 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Apr 9 05:01:20 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sun Apr 9 05:01:25 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sun Apr 9 05:01:45 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>6 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -77,5 +77,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 04/09/2023 - 04:17:32</center>
<br><center><b>Date Generated:</b> 04/09/2023 - 05:01:58</center>
</BODY></HTML>

2
cpld/XC95144XL/WarpSE_xst.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sun Apr 09 04:14:10 2023">
<application stringID="Xst" timeStamp="Sun Apr 09 05:01:15 2023">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>

2
cpld/XC95144XL/_ngo/netlist.lst
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@ -1,2 +1,2 @@
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681028055
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681030880
OK

18
cpld/XC95144XL/_xmsgs/pn_parser.xmsgs
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@ -8,6 +8,24 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/CNT.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/CS.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/FSB.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBM.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBS.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/RAM.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE.v&quot; into library work</arg>
</msg>

18
cpld/XC95144XL/iseconfig/WarpSE.projectmgr
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@ -1,4 +1,4 @@
<?xml version="1.0" encoding="utf-8"?>
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
@ -9,13 +9,13 @@
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>cnt - CNT (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/CNT.v)</SelectedItem>
<SelectedItem>WarpSE (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000d2000000020000000000000000000000000200000064ffffffff000000810000000300000002000000d20000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>cnt - CNT (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/CNT.v)</CurrentItem>
<CurrentItem>WarpSE (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
@ -40,7 +40,7 @@
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>CNT.v</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
@ -64,13 +64,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Generate Timing</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Generate Timing</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>

4
cpld/XC95144XL/iseconfig/WarpSE.xreport
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@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2023-04-09T03:54:50</DateModified>
<DateModified>2023-04-09T04:28:14</DateModified>
<ModuleName>WarpSE</ModuleName>
<SummaryTimeStamp>2023-04-09T02:22:59</SummaryTimeStamp>
<SavedFilePath>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL</ImplementationReportsDirectory>
<ImplementationReportsDirectory>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
<DateInitialized>2023-04-07T01:51:28</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>

5
cpld/XC95144XL/webtalk_pn.xml
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@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sun Apr 09 04:14:09 2023">
<application name="pn" timeStamp="Sun Apr 09 05:01:14 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="7132971001B64D51887D7F260ADC77C3" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
@ -26,6 +26,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_intWbtProjectID" value="7132971001B64D51887D7F260ADC77C3" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="XC9500XL CPLDs" type="design"/>
<property name="PROP_DevDevice" value="xc95144xl" type="design"/>
@ -35,7 +36,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_DevSpeed" value="-10" type="design"/>
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
<property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VERILOG" value="8" type="source"/>
<property name="FILE_VERILOG" value="7" type="source"/>
</section>
</application>
</document>

14
cpld/XC95144XL/xst/work/hdllib.ref
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@ -1,7 +1,7 @@
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681028050
MO CS NULL ../CS.v vlg22/_c_s.bin 1681028050
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681028050
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681028050
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681028050
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681028050
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681028050
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681030875
MO CS NULL ../CS.v vlg22/_c_s.bin 1681030875
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681030875
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681030875
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681030875
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681030875
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681030875

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cpld/XC95144XL/xst/work/vlg22/_c_s.bin
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cpld/XC95144XL/xst/work/vlg52/_warp_s_e.bin
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cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin
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