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Zane Kaminski 2023-04-17 02:23:47 -04:00
parent a3b441fde9
commit 335232eae2
1 changed files with 1 additions and 7 deletions
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8
cpld/RAM.v
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@ -120,12 +120,6 @@ module RAM(
RAMReady <= 1;
end
end 4: begin // Refresh RAS II
RS <= 5;
RASEL <= 0;
RASrr <= 1;
RASEN <= 0;
RAMReady <= 0;
end 5: begin // Refresh precharge I
RS <= 6;
RASEL <= 0;
RASrr <= 0;
@ -147,7 +141,7 @@ module RAM(
endcase
end
always @(negedge CLK) begin
RASrf <= RS==1;
RASrf <= RS==1 || RS==4;
case (RS[2:0])
0: nCAS <= !RS0toRef;
1: nCAS <= 0;