From 357eccab161e0b1699ef9c2deee2d5759e6282ac Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Tue, 5 Apr 2022 18:00:27 -0400 Subject: [PATCH] working on SDRAM --- CPUBuf.kicad_sch | 1110 ++++++ Control.kicad_sch | 16 + PDSBuf.kicad_sch | 3747 +++++++++++++++++++ RAM.kicad_sch | 1359 +++++++ RAMROM.kicad_sch | 2074 ++-------- WarpSE.kicad_prl | 2 +- WarpSE.kicad_pro | 12 +- WarpSE.kicad_sch | 1449 ++++--- cpld/CLK.v | 13 + cpld/CNT.v | 7 - cpld/CS.v | 24 +- cpld/FSB.v | 19 +- cpld/RAM.v | 379 +- cpld/WarpSE.v | 39 +- cpld/XC95144XL/WarpSE.cmd_log | 6 + cpld/XC95144XL/WarpSE.gise | 39 +- cpld/XC95144XL/WarpSE.ngc | 2 +- cpld/XC95144XL/WarpSE.ngr | 2 +- cpld/XC95144XL/WarpSE.prj | 1 + cpld/XC95144XL/WarpSE.syr | 152 +- cpld/XC95144XL/WarpSE.xise | 6 +- cpld/XC95144XL/WarpSE_summary.html | 6 +- cpld/XC95144XL/WarpSE_xst.xrpt | 42 +- cpld/XC95144XL/_xmsgs/pn_parser.xmsgs | 18 - cpld/XC95144XL/_xmsgs/xst.xmsgs | 28 +- cpld/XC95144XL/iseconfig/WarpSE.projectmgr | 7 +- cpld/XC95144XL/iseconfig/WarpSE.xreport | 2 +- cpld/XC95144XL/webtalk_pn.xml | 4 +- cpld/XC95144XL/xst/work/hdllib.ref | 15 +- cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin | Bin 20942 -> 24652 bytes cpld/XC95144XL/xst/work/vlg22/_c_s.bin | Bin 13511 -> 13511 bytes cpld/XC95144XL/xst/work/vlg37/_f_s_b.bin | Bin 7217 -> 7476 bytes cpld/XC95144XL/xst/work/vlg52/_c_l_k.bin | Bin 0 -> 2141 bytes cpld/XC95144XL/xst/work/vlg52/_warp_s_e.bin | Bin 21682 -> 22700 bytes cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin | Bin 4280 -> 2668 bytes cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin | Bin 19519 -> 19519 bytes cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin | Bin 12663 -> 12663 bytes 37 files changed, 7779 insertions(+), 2801 deletions(-) create mode 100644 CPUBuf.kicad_sch create mode 100644 PDSBuf.kicad_sch create mode 100644 RAM.kicad_sch create mode 100644 cpld/CLK.v create mode 100644 cpld/XC95144XL/xst/work/vlg52/_c_l_k.bin diff --git a/CPUBuf.kicad_sch b/CPUBuf.kicad_sch new file mode 100644 index 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0c5dddf1-38df-43d2-b49c-e7b691dab0ab) @@ -1354,6 +1358,10 @@ (effects (font (size 1.27 1.27)) (justify left)) (uuid 0e0f9829-27a5-43b2-a0ae-121d3ce72ef4) ) + (hierarchical_label "Acc~{BERR}" (shape output) (at 91.44 114.3 0) + (effects (font (size 1.27 1.27)) (justify left)) + (uuid 1295be7c-b0d0-4670-a7f8-d8979b0215ad) + ) (hierarchical_label "ROM~{WE}" (shape output) (at 210.82 109.22 180) (effects (font (size 1.27 1.27)) (justify right)) (uuid 15ea3484-2685-47cb-9e01-ec01c6d477b8) @@ -1410,6 +1418,10 @@ (effects (font (size 1.27 1.27)) (justify left)) (uuid 4970ec6e-3725-4619-b57d-dc2c2cb86ed0) ) + (hierarchical_label "Acc~{DTACK}" (shape output) (at 91.44 119.38 0) + (effects (font (size 1.27 1.27)) (justify left)) + (uuid 56cecd5a-008e-41df-af8c-5e4688d2a528) + ) (hierarchical_label "ADoutLE0" (shape output) (at 261.62 78.74 0) (effects (font (size 1.27 1.27)) (justify left)) (uuid 58126faf-01a4-4f91-8e8c-ca9e47b48048) @@ -1418,6 +1430,10 @@ (effects (font (size 1.27 1.27)) (justify right)) (uuid 58390862-1833-41dd-9c4e-98073ea0da33) ) + (hierarchical_label "Acc~{BR}" (shape output) (at 91.44 121.92 0) + (effects (font (size 1.27 1.27)) (justify left)) + (uuid 5db41e98-9c51-489f-a58b-6ef1f756c143) + ) (hierarchical_label "Acc~{VPA}" (shape output) (at 210.82 127 180) (effects (font (size 1.27 1.27)) (justify right)) (uuid 5e755161-24a5-4650-a6e3-9836bf074412) diff --git a/PDSBuf.kicad_sch b/PDSBuf.kicad_sch new file mode 100644 index 0000000..b588bed --- /dev/null +++ b/PDSBuf.kicad_sch @@ -0,0 +1,3747 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 54093c93-5e7e-4c8d-8d94-40c077747c12) + + (paper "A4") + + (lib_symbols + (symbol "Device:C_Small" (pin_numbers hide) (pin_names (offset 0.254) hide) (in_bom yes) (on_board yes) + (property "Reference" "C" (id 0) (at 0.254 1.778 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "C_Small" (id 1) (at 0.254 -2.032 0) + (effects (font (size 1.27 1.27)) (justify left)) + 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"active_layer": 0, + "active_layer": 31, "active_layer_preset": "All Layers", "auto_track_width": true, "hidden_nets": [], diff --git a/WarpSE.kicad_pro b/WarpSE.kicad_pro index 7928a1f..e6e2237 100644 --- a/WarpSE.kicad_pro +++ b/WarpSE.kicad_pro @@ -487,7 +487,7 @@ ], [ "00000000-0000-0000-0000-000060941922", - "Buf" + "PDSBuf" ], [ "00000000-0000-0000-0000-00005f72f108", @@ -495,16 +495,12 @@ ], [ "00000000-0000-0000-0000-00005f723900", - "RAMROM" + "RAM" ], [ "00000000-0000-0000-0000-00005f723173", "Control" ], - [ - "00000000-0000-0000-0000-000061350d21", - "Clk.sch" - ], [ "00000000-0000-0000-0000-000061a87b62", "DIPSW" @@ -512,6 +508,10 @@ [ "00000000-0000-0000-0000-000061aa52c4", "Prog" + ], + [ + "b5e3c22e-d373-459f-a3ce-4b8c26e51ce1", + "CPUBuf" ] ], "text_variables": {} diff --git a/WarpSE.kicad_sch b/WarpSE.kicad_sch index 326c79b..716c1b3 100644 --- a/WarpSE.kicad_sch +++ b/WarpSE.kicad_sch @@ -65,430 +65,361 @@ ) ) - (junction (at 73.66 71.12) (diameter 0) (color 0 0 0 0) - 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(unit 1) (value "74LVC245APW") (footprint "") ) (path "/00000000-0000-0000-0000-000061aa52c4/00000000-0000-0000-0000-0000616f4596" (reference "Y1") (unit 1) (value "12M") (footprint "stdpads:Crystal_HC49-SMD") diff --git a/cpld/CLK.v b/cpld/CLK.v new file mode 100644 index 0000000..3358769 --- /dev/null +++ b/cpld/CLK.v @@ -0,0 +1,13 @@ +module CLK( + input CLK, output reg [2:0] SS, + output reg MCLK, output RCLK); + + always @(posedge CLK) begin + SS[1:0] <= SS[1:0]+1; + end + + always @(posedge CLK) begin + MCLK <= SS[1:0]==2'b01 || SS[1:0]==2'b10; + end + +endmodule diff --git a/cpld/CNT.v b/cpld/CNT.v index d26fff4..b5de4c6 100644 --- a/cpld/CNT.v +++ b/cpld/CNT.v @@ -1,20 +1,13 @@ module CNT( /* FSB clock and AS detection */ input FCLK, input CACT, - /* Refresh request */ - output RefReq, output RefUrgent, input RefAck, /* Timeout signals */ output reg TimeoutA, output reg TimeoutB); /* Refresh counter */ reg [7:0] RefCnt = 0; - reg RefDone = 0; - assign RefReq = ~RefDone; - assign RefUrgent = RefCnt[7] && RefCnt[6] && RefCnt[5] && ~RefDone; always @(posedge FCLK) begin RefCnt <= RefCnt+1; - if (RefCnt==0) RefDone <= 0; - else if (RefAck) RefDone <= 1; end /* Timeout signals */ diff --git a/cpld/CS.v b/cpld/CS.v index 1b2705d..67b4ceb 100644 --- a/cpld/CS.v +++ b/cpld/CS.v @@ -39,7 +39,7 @@ module CS( (A[15:12]==4'hC) || // 4096 bytes video (A[15:12]==4'hD) || // 4096 bytes video (A[15:12]==4'hE) || // 4096 bytes video - (A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound + (A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound assign SndRAMCSWR = VidRAMCSWR64k && ( (A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) || (A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3))); @@ -49,18 +49,18 @@ module CS( (A[23:20]==4'h0 && Overlay); /* Select signals - IOB domain */ - assign IACS = A[23:08]==16'hFFFF; // IACK + assign IACS = A[23:08]==16'hFFFF; // IACK assign IOCS = (A[23:20]==4'h4 && MotherboardROMEN) || // Motherboard ROM - A[23:20]==4'h5 || // SCSI - A[23:20]==4'h8 || // empty - A[23:20]==4'h9 || // SCC read/reset - A[23:20]==4'hA || // empty - A[23:20]==4'hB || // SCC write - A[23:20]==4'hC || // empty - A[23:20]==4'hD || // IWM - A[23:20]==4'hE || // VIA - A[23:20]==4'hF || // IACK - VidRAMCSWR; + A[23:20]==4'h5 || // SCSI + A[23:20]==4'h8 || // empty + A[23:20]==4'h9 || // SCC read/reset + A[23:20]==4'hA || // empty + A[23:20]==4'hB || // SCC write + A[23:20]==4'hC || // empty + A[23:20]==4'hD || // IWM + A[23:20]==4'hE || // VIA + A[23:20]==4'hF || // IACK + VidRAMCSWR; assign SCSICS = A[23:20]==4'h5; // SCSI assign IOPWCS = RAMCS_OverlayOff && ~nWE; diff --git a/cpld/FSB.v b/cpld/FSB.v index f323c45..2cc0ca7 100644 --- a/cpld/FSB.v +++ b/cpld/FSB.v @@ -1,39 +1,38 @@ module FSB( + input CLK, input [1:0] SS, /* MC68HC000 interface */ input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR, /* AS cycle detection */ - output BACT, + output reg BACT, /* Ready inputs */ - input Ready0, input Ready1, input Ready2, input Disable, + input Ready0, input Ready1, input Disable, /* BERR inputs */ input BERR0, input BERR1, /* Interrupt acknowledge select */ input IACS); /* AS cycle detection */ - reg ASrf = 0; - always @(negedge FCLK) begin ASrf <= ~nAS; end - assign BACT = ~nAS || ASrf; + always @(posedge FCLK) begin + if (SS[1:0]==2'h1 && ~nAS) BACT <= 1; + else if (SS[1:0]==2'h3 && nAS) BACT <= 0; + end /* Ready and BERR "remember" */ - reg Ready0r, Ready1r, Ready2r; + reg Ready0r, Ready1r; reg BERR0r, BERR1r; wire Ready = ~Disable && (Ready0 || Ready0r) && - (Ready1 || Ready1r) && - (Ready2 || Ready2r); + (Ready1 || Ready1r); wire BERR = (BERR0 || BERR0r || BERR1 || BERR1r); assign nBERR = ~(~nAS && BERR); always @(posedge FCLK) begin if (~BACT) begin Ready0r <= 0; Ready1r <= 0; - Ready2r <= 0; BERR0r <= 0; BERR1r <= 0; end else begin if (Ready0) Ready0r <= 1; if (Ready1) Ready1r <= 1; - if (Ready2) Ready2r <= 1; if (BERR0) BERR0r <= 1; if (BERR1) BERR1r <= 1; end diff --git a/cpld/RAM.v b/cpld/RAM.v index 04f5629..a240530 100644 --- a/cpld/RAM.v +++ b/cpld/RAM.v @@ -1,150 +1,253 @@ module RAM( + /* Fast clock and 25 MHz substate */ + input CLK, input [1:0] SS, /* MC68HC000 interface */ - input CLK, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS, - /* AS cycle detection */ - input BACT, + input [21:1] A, input nWE, input nAS, input nLDS, input nUDS, + input BACT, /* Select and ready signals */ - input RAMCS, input ROMCS, output Ready, - /* Refresh Counter Interface */ - input RefReq, input RefUrgent, output RefAck, - /* DRAM and NOR flash interface */ - output [11:0] RA, output nRAS, output reg nCAS, - output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE); - + input RAMCS, input ROMCS, + /* SDRAM interface */ + output reg CKE, output reg nCS, + output reg nRAS, output reg nCAS, output reg nRWE, + output reg [1:0] BA, output reg [11:0] RA, + output reg DQMH, output reg DQML); + /* RAM control state */ - reg [2:0] RS = 0; - reg Once = 0; - reg RAMReady = 0; - reg RASEL = 0; // RASEL controls /CAS signal - - /* Refresh state */ - reg RAMDIS1 = 0; - reg RAMDIS2 = 0; - wire RAMDIS = RAMDIS1 || RAMDIS2; - wire RAMEN = ~RAMDIS; - reg RefRAS = 0; - - assign nROMCS = ~ROMCS; - assign nRAS = ~((~nAS && RAMCS && RAMEN && ~RefRAS /* does this add loading to these P-terms? */) || RefRAS); - assign nOE = ~(~nAS && nWE); - assign nLWE = ~(~nAS && ~nWE && ~nLDS && RAMEN); - assign nUWE = ~(~nAS && ~nWE && ~nUDS && RAMEN); - assign nROMWE = ~(~nAS && ~nWE); - - assign RA[11] = A[19]; - assign RA[10] = A[21]; - assign RA[09] = RASEL ? A[20] : A[19]; - assign RA[08] = (RASEL && RAMCS) ? A[09] : A[18]; - assign RA[07] = RASEL ? A[08] : A[17]; - assign RA[06] = RASEL ? A[07] : A[16]; - assign RA[05] = RASEL ? A[06] : A[15]; - assign RA[04] = RASEL ? A[05] : A[14]; - assign RA[03] = RASEL ? A[04] : A[13]; - assign RA[02] = RASEL ? A[03] : A[12]; - assign RA[01] = RASEL ? A[02] : A[11]; - assign RA[00] = RASEL ? A[01] : A[10]; - + reg [1:0] RS = 0; + reg Once1 = 0; + reg Once3 = 0; always @(posedge CLK) begin - if (~BACT) Once <= 0; - else if (RS==0 && BACT && RAMCS) Once <= 1; + if (SS[1:0]==2'h3) case (RS[1:0]) + 2'h0: RS <= 2'h1; + 2'h1: RS <= ~nAS ? (Once3 ? 2'h3 : 2'h2) : 2'h1; + 2'h2: RS <= 2'h3; + 2'h3: RS <= 2'h0; + endcase end always @(posedge CLK) begin - if (~BACT) RAMDIS2 <= 0; - else if ((RS==0 && BACT && RefUrgent && Once && RAMCS) || - (RS==7 && BACT && RefUrgent && Once)) RAMDIS2 <= 1; - end - reg BACTr; - always @(posedge CLK) begin BACTr <= BACT; end - always @(posedge CLK) begin - if (RS==0) begin - if (( BACT && RefReq && ~RAMCS && ~BACTr) || // Non-urgent refresh can start during first clock of non-RAM cycle - (~BACT && RefUrgent) || // Urgent refresh can start during bus idle - ( BACT && RefUrgent && ~RAMCS)) begin // Urgent refresh can start during non-ram cycle - RS <= 2; - RAMReady <= 0; - RASEL <= 1; - RAMDIS1 <= 1; - end else if (BACT && RAMCS && ~Once) begin - // RAM access cycle has priority over urgent refresh if RAM access already begun - RS <= 5; - RAMReady <= 0; - RASEL <= 1; - RAMDIS1 <= 0; - end else if (BACT && RAMCS && RefUrgent) begin - // Urgent refresh can start during prolonged RAM access cycle - // But we must insert one extra precharge state first. - RS <= 1; - RAMReady <= 0; - RASEL <= 0; - RAMDIS1 <= 1; - end else begin - // No RAM access/refresh requests pending - RS <= 0; - RAMReady <= 1; - RASEL <= 0; - RAMDIS1 <= 0; - end - RefRAS <= 0; - end else if (RS==1) begin - RS <= 2; - RAMReady <= 0; - RASEL <= 1; - RAMDIS1 <= 1; - RefRAS <= 0; - end else if (RS==2) begin - RS <= 3; - RAMReady <= 0; - RASEL <= 1; - RAMDIS1 <= 1; - RefRAS <= 1; - end else if (RS==3) begin - RS <= 4; - RAMReady <= 0; - RASEL <= 0; - RAMDIS1 <= 1; - RefRAS <= 1; - end else if (RS==4) begin - RS <= 7; - RAMReady <= 0; - RASEL <= 0; - RAMDIS1 <= 1; - RefRAS <= 0; - end else if (RS==5) begin - RS <= 6; - RAMReady <= 0; - RASEL <= 1; - RAMDIS1 <= 0; - RefRAS <= 0; - end else if (RS==6) begin - RS <= 7; - RAMReady <= 0; - RASEL <= 0; - RAMDIS1 <= 0; - RefRAS <= 0; - end else if (RS==7) begin - if (~BACT && RefUrgent) begin - RS <= 2; - RAMReady <= 0; - RAMDIS1 <= 1; - RASEL <= 1; - end else if (BACT && RefUrgent) begin - RS <= 1; - RAMReady <= 0; - RASEL <= 0; - RAMDIS1 <= 1; - end else begin - RS <= 0; - RAMReady <= 1; - RASEL <= 0; - RAMDIS1 <= 0; - end - RefRAS <= 0; + if (SS[1:0]==2'h1 && RS[1:0]==2'h1 && ~nAS && RAMCS) Once1 <= 1; + else if (SS[1:0]==2'h3) begin + if (nAS) begin + Once1 <= 0; + Once3 <= 0; + end else Once3 <= Once1; end end - always @(negedge CLK) begin nCAS <= ~RASEL; end - assign RefAck = RefRAS; - - assign Ready = ~RAMCS || RAMReady; + /* RAM control and address */ + always @(posedge CLK) begin + case (RS[1:0]) + 2'h0: begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end 2'h1: begin + case (SS[1:0]) + 2'h0: begin + if (RAMCS || ROMCS) begin + // NOP CKE + CKE <= 1'b1; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end else begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end + RA[11:0] <= A[21:10]; + end 2'h1: begin + if (~nAS && ~Once3 && (RAMCS || ROMCS)) begin + // ACT CKD + CKE <= 1'b0; + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end else begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end + RA[11:0] <= A[21:10]; + end 2'h2: begin + if (~nAS && ~Once3 && nWE && (RAMCS || ROMCS)) begin + // NOP CKE + CKE <= 1'b1; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end else begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end + RA[10] <= 1'b1; // auto-precharge + RA[9] <= A[9]; // don't care + RA[8:0] <= A[9:1]; + end 2'h3: begin + if (~nAS && ~Once3 && nWE && (RAMCS || ROMCS)) begin + // RD CKE + CKE <= 1'b1; + nCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end else begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end + RA[10] <= 1'b1; // auto-precharge + RA[9] <= A[19]; // don't care + RA[8:0] <= A[9:1]; + end + endcase + BA[1] <= 1'b0; + BA[0] <= RAMCS; + end 2'h2: begin + case (SS[1:0]) + 2'h0: begin + if (~nWE && RAMCS) begin + // NOP CKE + CKE <= 1'b1; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end else begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end + end 2'h1: begin + if (~nWE && RAMCS) begin + // WR CKE + CKE <= 1'b1; + nCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= 1'b0; + DQML <= nLDS; + DQMH <= nUDS; + end else begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end + end 2'h2: begin + // NOP CKE + CKE <= 1'b1; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end 2'h3: begin + // PC CKD + CKE <= 1'b0; + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b0; + DQML <= 1'b1; + DQMH <= 1'b1; + end + endcase + // BA[1:0] doesn't change + RA[10] <= 1'b1; // auto-precharge / "all" + RA[9] <= A[19]; // don't care + RA[8:0] <= A[9:1]; + end 2'h3: begin + case (SS[1:0]) + 2'h0: begin + // NOP CKE + CKE <= 1'b1; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end 2'h1: begin + // AREF + CKE <= 1'b1; + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end 2'h2: begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end 2'h3: begin + // NOP CKD + CKE <= 1'b0; + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + DQML <= 1'b1; + DQMH <= 1'b1; + end + endcase + end + endcase + end endmodule diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v index 49ffa5e..aa04287 100644 --- a/cpld/WarpSE.v +++ b/cpld/WarpSE.v @@ -7,7 +7,9 @@ module WarpSE( output nDTACK_FSB, output nVPA_FSB, output nBERR_FSB, - input CLK_FSB, + input CLK, + output MCLK, + output RCLK, input CLK2X_IOB, input CLK_IOB, input E_IOB, @@ -22,14 +24,15 @@ module WarpSE( input nBERR_IOB, input nRES, input nIPL2, - output nROMCS, - output nRAMLWE, - output nRAMUWE, - output nROMWE, + output CKE, + output nCS, output nRAS, output nCAS, + output nRWE, + output [1:0] BA, output [11:0] RA, - output nOE, + output DQMH, + output DQML, output nADoutLE0, output nADoutLE1, output nAoutOE, @@ -48,8 +51,9 @@ module WarpSE( /* AS cycle detection */ wire BACT; - /* Refresh request/ack signals */ - wire RefReq, RefUrgent, RefAck; + wire [1:0] SS; + wire CLK_FSB = (~CLK && SS[1:0]==2'b01); + CLK clk(CLK, SS, MCLK, RCLK); wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR; CS cs( @@ -62,19 +66,17 @@ module WarpSE( /* Device select outputs */ IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR); - wire Ready_RAM; RAM ram( + CLK, SS, /* MC68HC000 interface */ - CLK_FSB, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB, + A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB, /* AS cycle detection */ BACT, /* Select and ready signals */ - RAMCS, ROMCS, Ready_RAM, - /* Refresh Counter Interface */ - RefReq, RefUrgent, RefAck, - /* DRAM and NOR flash interface */ - RA[11:0], nRAS, nCAS, - nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE); + RAMCS, ROMCS, + /* SDRAM interface */ + CKE, nCS, nRAS, nCAS, nRWE, + BA, RA, DQMH, DQML); wire Ready_IOBS, BERR_IOBS; wire Park, IOREQ, IOACT, IOBERR; @@ -118,8 +120,6 @@ module WarpSE( CNT cnt( /* FSB clock and AS detection */ CLK_FSB, BACT, - /* Refresh request */ - RefReq, RefUrgent, RefAck, /* Timeout signals */ TimeoutA, TimeoutB); @@ -140,12 +140,13 @@ module WarpSE( end FSB fsb( + CLK, SS, /* MC68HC000 interface */ CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB, /* AS cycle detection */ BACT, /* Ready and IA inputs */ - Ready_RAM, Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA), Disable, + Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA), Disable, /* BERR inputs */ (~SCSICS && TimeoutB), BERR_IOBS, /* Interrupt acknowledge select */ diff --git a/cpld/XC95144XL/WarpSE.cmd_log b/cpld/XC95144XL/WarpSE.cmd_log index 55c92dc..3a535e9 100644 --- a/cpld/XC95144XL/WarpSE.cmd_log +++ b/cpld/XC95144XL/WarpSE.cmd_log @@ -22,3 +22,9 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt verilog -optimize speed -htmlr XSLTProcess WarpSE_build.xml tsim -intstyle ise WarpSE WarpSE.nga taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" diff --git a/cpld/XC95144XL/WarpSE.gise b/cpld/XC95144XL/WarpSE.gise index 99188c7..92425f0 100644 --- a/cpld/XC95144XL/WarpSE.gise +++ b/cpld/XC95144XL/WarpSE.gise @@ -70,15 +70,15 @@ - + - + - + @@ -102,37 +102,30 @@ + + + - - - - - + - + + + + - - - - - - - - - - - - - + - + + + + diff --git a/cpld/XC95144XL/WarpSE.ngc b/cpld/XC95144XL/WarpSE.ngc index 9397fdb..0209d8e 100644 --- a/cpld/XC95144XL/WarpSE.ngc +++ b/cpld/XC95144XL/WarpSE.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/cpld/XC95144XL/WarpSE.ngr b/cpld/XC95144XL/WarpSE.ngr index 5c3b112..4fae4e5 100644 --- a/cpld/XC95144XL/WarpSE.ngr +++ b/cpld/XC95144XL/WarpSE.ngr @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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a/cpld/XC95144XL/WarpSE.prj b/cpld/XC95144XL/WarpSE.prj index dc97722..e26d242 100644 --- a/cpld/XC95144XL/WarpSE.prj +++ b/cpld/XC95144XL/WarpSE.prj @@ -4,4 +4,5 @@ verilog work "../IOBM.v" verilog work "../FSB.v" verilog work "../CS.v" verilog work "../CNT.v" +verilog work "../CLK.v" verilog work "../WarpSE.v" diff --git a/cpld/XC95144XL/WarpSE.syr b/cpld/XC95144XL/WarpSE.syr index 50a806d..156c78a 100644 --- a/cpld/XC95144XL/WarpSE.syr +++ b/cpld/XC95144XL/WarpSE.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.84 secs +Total CPU time to Xst completion: 0.80 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.87 secs +Total CPU time to Xst completion: 0.84 secs --> Reading design: WarpSE.prj @@ -86,8 +86,10 @@ Compiling verilog file "../CS.v" in library work Module compiled Compiling verilog file "../CNT.v" in library work Module compiled -Compiling verilog file "../WarpSE.v" in library work +Compiling verilog file "../CLK.v" in library work Module compiled +Compiling verilog file "../WarpSE.v" in library work +Module compiled Module compiled No errors in compilation Analysis of file <"WarpSE.prj"> succeeded. @@ -98,6 +100,8 @@ Analysis of file <"WarpSE.prj"> succeeded. ========================================================================= Analyzing hierarchy for module in library . +Analyzing hierarchy for module in library . + Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . @@ -117,6 +121,9 @@ Analyzing hierarchy for module in library . Analyzing top module . Module is correct for synthesis. +Analyzing module in library . +Module is correct for synthesis. + Analyzing module in library . Module is correct for synthesis. @@ -141,6 +148,20 @@ Module is correct for synthesis. ========================================================================= Performing bidirectional port resolution... +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. + +Synthesizing Unit . + Related source file is "../CLK.v". +WARNING:Xst:1305 - Output is never assigned. Tied to value 0. +WARNING:Xst:1305 - Output > is never assigned. Tied to value 0. + Found 2-bit register for signal >. + Found 1-bit register for signal . + Found 2-bit adder for signal <$add0000> created at line 6. + Summary: + inferred 3 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + Synthesizing Unit . Related source file is "../CS.v". @@ -153,28 +174,33 @@ Unit synthesized. Synthesizing Unit . Related source file is "../RAM.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found finite state machine for signal . ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 18 | - | Inputs | 6 | - | Outputs | 9 | + | States | 4 | + | Transitions | 6 | + | Inputs | 2 | + | Outputs | 4 | | Clock | CLK (rising_edge) | - | Power Up State | 000 | + | Clock enable | RS$cmp_eq0000 (positive) | + | Power Up State | 00 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). - inferred 6 D-type flip-flop(s). + inferred 21 D-type flip-flop(s). Unit synthesized. @@ -262,7 +288,6 @@ Synthesizing Unit . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit up counter for signal . - Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). @@ -271,13 +296,13 @@ Unit synthesized. Synthesizing Unit . Related source file is "../FSB.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . - Found 1-bit register for signal . + Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . - Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). @@ -308,11 +333,13 @@ Unit synthesized. HDL Synthesis Report Macro Statistics +# Adders/Subtractors : 1 + 2-bit adder : 1 # Counters : 2 5-bit up counter : 1 8-bit up counter : 1 -# Registers : 68 - 1-bit register : 68 +# Registers : 83 + 1-bit register : 83 # Tristates : 4 1-bit tristate buffer : 4 @@ -347,18 +374,14 @@ Optimizing FSM on signal with johnson encoding. 01 | 10 ------------------- Analyzing FSM for best encoding. -Optimizing FSM on signal with compact encoding. +Optimizing FSM on signal with compact encoding. ------------------- State | Encoding ------------------- - 000 | 000 - 010 | 010 - 101 | 001 - 001 | 101 - 011 | 011 - 100 | 111 - 111 | 100 - 110 | 110 + 00 | 10 + 01 | 00 + 11 | 11 + 10 | 01 ------------------- WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone. You should achieve better results by setting this init to 1. @@ -370,11 +393,13 @@ Advanced HDL Synthesis Report Macro Statistics # FSMs : 3 +# Adders/Subtractors : 1 + 2-bit adder : 1 # Counters : 2 5-bit up counter : 1 8-bit up counter : 1 -# Registers : 47 - Flip-Flops : 47 +# Registers : 65 + Flip-Flops : 65 ========================================================================= @@ -394,27 +419,23 @@ Optimizing unit ... implementation constraint: INIT=r : IPL2r1 implementation constraint: INIT=r : Disable implementation constraint: INIT=r : RESDone - implementation constraint: INIT=r : ram/RAMReady - implementation constraint: INIT=r : ram/RASEL - implementation constraint: INIT=r : ram/RAMDIS1 - implementation constraint: INIT=r : ram/RefRAS - implementation constraint: INIT=r : ram/RAMDIS2 - implementation constraint: INIT=r : ram/Once + implementation constraint: INIT=r : ram/Once3 + implementation constraint: INIT=r : ram/Once1 + implementation constraint: INIT=r : iobs/PS_FSM_FFd1 implementation constraint: INIT=r : iobs/IOACTr - implementation constraint: INIT=r : ram/RS_FSM_FFd1 implementation constraint: INIT=r : iobs/Once implementation constraint: INIT=r : cs/nOverlay0 implementation constraint: INIT=r : cs/nOverlay1 - implementation constraint: INIT=r : iobs/PS_FSM_FFd1 + implementation constraint: INIT=r : iobm/IOREQr implementation constraint: INIT=r : iobs/PS_FSM_FFd2 + implementation constraint: INIT=r : iobm/IOS_FSM_FFd2 + implementation constraint: INIT=r : iobm/IOS_FSM_FFd3 implementation constraint: INIT=r : iobm/ETACK implementation constraint: INIT=r : iobm/BGr0 implementation constraint: INIT=r : iobm/BGr1 implementation constraint: INIT=r : iobm/BG - implementation constraint: INIT=r : iobm/IOREQr - implementation constraint: INIT=r : fsb/ASrf + implementation constraint: INIT=s : ram/RS_FSM_FFd1 implementation constraint: INIT=r : ram/RS_FSM_FFd2 - implementation constraint: INIT=r : cnt/RefDone implementation constraint: INIT=r : cnt/RefCnt_0 implementation constraint: INIT=r : cnt/RefCnt_1 implementation constraint: INIT=r : cnt/RefCnt_2 @@ -423,10 +444,7 @@ Optimizing unit ... implementation constraint: INIT=r : cnt/RefCnt_5 implementation constraint: INIT=r : cnt/RefCnt_6 implementation constraint: INIT=r : cnt/RefCnt_7 - implementation constraint: INIT=r : ram/RS_FSM_FFd3 implementation constraint: INIT=r : iobm/IOS_FSM_FFd1 - implementation constraint: INIT=r : iobm/IOS_FSM_FFd2 - implementation constraint: INIT=r : iobm/IOS_FSM_FFd3 ========================================================================= * Partition Report * @@ -455,44 +473,44 @@ Clock Enable : YES wysiwyg : NO Design Statistics -# IOs : 75 +# IOs : 79 Cell Usage : -# BELS : 596 -# AND2 : 165 -# AND3 : 25 -# AND4 : 15 -# AND5 : 3 +# BELS : 631 +# AND2 : 180 +# AND3 : 29 +# AND4 : 13 +# AND5 : 1 # AND6 : 1 # AND7 : 1 # AND8 : 3 # GND : 1 -# INV : 265 -# OR2 : 98 -# OR3 : 5 -# OR4 : 1 +# INV : 266 +# OR2 : 109 +# OR3 : 9 +# OR4 : 3 # VCC : 1 -# XOR2 : 12 -# FlipFlops/Latches : 89 -# FD : 60 -# FDCE : 29 +# XOR2 : 14 +# FlipFlops/Latches : 103 +# FD : 72 +# FDCE : 31 # Tri-States : 1 # BUFE : 1 -# IO Buffers : 74 +# IO Buffers : 78 # IBUF : 39 -# OBUF : 31 +# OBUF : 35 # OBUFE : 4 ========================================================================= -Total REAL time to Xst completion: 39.00 secs -Total CPU time to Xst completion: 38.76 secs +Total REAL time to Xst completion: 23.00 secs +Total CPU time to Xst completion: 22.87 secs --> -Total memory usage is 236884 kilobytes +Total memory usage is 205652 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 5 ( 0 filtered) -Number of infos : 0 ( 0 filtered) +Number of warnings : 10 ( 0 filtered) +Number of infos : 1 ( 0 filtered) diff --git a/cpld/XC95144XL/WarpSE.xise b/cpld/XC95144XL/WarpSE.xise index c18d7f4..727246e 100644 --- a/cpld/XC95144XL/WarpSE.xise +++ b/cpld/XC95144XL/WarpSE.xise @@ -41,11 +41,15 @@ - + + + + + diff --git a/cpld/XC95144XL/WarpSE_summary.html b/cpld/XC95144XL/WarpSE_summary.html index 65742f3..e413d8d 100644 --- a/cpld/XC95144XL/WarpSE_summary.html +++ b/cpld/XC95144XL/WarpSE_summary.html @@ -2,12 +2,12 @@ - + - + @@ -77,5 +77,5 @@ System Settings
WarpSE Project Status (03/28/2022 - 09:47:24)
WarpSE Project Status
Project File: WarpSE.xise Parser Errors: No Errors X 4 Errors
Module Name:
-
Date Generated: 03/28/2022 - 09:47:24
+
Date Generated: 04/02/2022 - 12:52:13
\ No newline at end of file diff --git a/cpld/XC95144XL/WarpSE_xst.xrpt b/cpld/XC95144XL/WarpSE_xst.xrpt index 7a00b13..82559dd 100644 --- a/cpld/XC95144XL/WarpSE_xst.xrpt +++ b/cpld/XC95144XL/WarpSE_xst.xrpt @@ -5,7 +5,7 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
@@ -79,9 +79,10 @@
+ - - + + @@ -89,9 +90,10 @@
+ - - + +
@@ -108,34 +110,34 @@
- +
- - - - + + + + - - + + - + - - - + + + - + - +
- - + +
diff --git a/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs b/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs index d77c5ee..b2da4a2 100644 --- a/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs +++ b/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs @@ -8,24 +8,6 @@ -Analyzing Verilog file "Z:/Warp-SE/cpld/CNT.v" into library work - - -Analyzing Verilog file "Z:/Warp-SE/cpld/CS.v" into library work - - -Analyzing Verilog file "Z:/Warp-SE/cpld/FSB.v" into library work - - -Analyzing Verilog file "Z:/Warp-SE/cpld/IOBM.v" into library work - - -Analyzing Verilog file "Z:/Warp-SE/cpld/IOBS.v" into library work - - -Analyzing Verilog file "Z:/Warp-SE/cpld/RAM.v" into library work - - Analyzing Verilog file "Z:/Warp-SE/cpld/WarpSE.v" into library work diff --git a/cpld/XC95144XL/_xmsgs/xst.xmsgs b/cpld/XC95144XL/_xmsgs/xst.xmsgs index 0a93d02..8afd483 100644 --- a/cpld/XC95144XL/_xmsgs/xst.xmsgs +++ b/cpld/XC95144XL/_xmsgs/xst.xmsgs @@ -5,22 +5,40 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -Input <SW<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +"../WarpSE.v" line 56 Connection to output port 'SS' does not match port size -The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone. +Register <BA<1>> in unit <RAM> has a constant value of 0 during circuit operation. The register is replaced by logic. + + +Output <RCLK> is never assigned. Tied to value 0. + + +Output <SS<2>> is never assigned. Tied to value 0. + + +Input <BACT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SW<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone. You should achieve better results by setting this init to 1. -The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable. +The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable. You should achieve better results by setting this init to 1. -The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE. +The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE. You should achieve better results by setting this init to 1. -The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE. +The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE. You should achieve better results by setting this init to 1. diff --git a/cpld/XC95144XL/iseconfig/WarpSE.projectmgr b/cpld/XC95144XL/iseconfig/WarpSE.projectmgr index 9af9f47..1f272a7 100644 --- a/cpld/XC95144XL/iseconfig/WarpSE.projectmgr +++ b/cpld/XC95144XL/iseconfig/WarpSE.projectmgr @@ -21,17 +21,16 @@ 1 - Implement Design/Synthesize - XST User Constraints - Generate Timing + Synthesize - XST - 7 + 4 0 000000ff0000000000000001000000010000000000000000000000000000000000000000000000012b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012b0000000100000000 false - Generate Timing + Synthesize - XST diff --git a/cpld/XC95144XL/iseconfig/WarpSE.xreport b/cpld/XC95144XL/iseconfig/WarpSE.xreport index 0803afd..cf40ff6 100644 --- a/cpld/XC95144XL/iseconfig/WarpSE.xreport +++ b/cpld/XC95144XL/iseconfig/WarpSE.xreport @@ -1,7 +1,7 @@
- 2022-03-28T09:36:17 + 2022-04-02T12:52:13 WarpSE Unknown Z:/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport diff --git a/cpld/XC95144XL/webtalk_pn.xml b/cpld/XC95144XL/webtalk_pn.xml index 461191f..6cf6a16 100644 --- a/cpld/XC95144XL/webtalk_pn.xml +++ b/cpld/XC95144XL/webtalk_pn.xml @@ -3,7 +3,7 @@ - +
@@ -41,7 +41,7 @@ This means code written to parse this file will need to be revisited each subseq - +
diff --git a/cpld/XC95144XL/xst/work/hdllib.ref b/cpld/XC95144XL/xst/work/hdllib.ref index e95d3b1..a7b0d3e 100644 --- a/cpld/XC95144XL/xst/work/hdllib.ref +++ b/cpld/XC95144XL/xst/work/hdllib.ref @@ -1,8 +1,9 @@ -MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1648475072 -MO CS NULL ../CS.v vlg22/_c_s.bin 1648475072 -MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1648475072 -MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1648475072 -MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1648475072 -MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1648475072 -MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1648475071 +MO CLK NULL ../CLK.v vlg52/_c_l_k.bin 1648923392 +MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1648923392 +MO CS NULL ../CS.v vlg22/_c_s.bin 1648923392 +MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1648923391 +MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1648923391 +MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1648923392 +MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1648923391 +MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1648923391 MO MXSE NULL ../MXSE.v vlg15/_m_x_s_e.bin 1648473402 diff --git a/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin b/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin index 52858a95884117b920c096a1f22fd3bb1e1e3aa6..6c693fe26a1de4e92243cc236462a52219108417 100644 GIT binary patch literal 24652 zcmeHM1+-m7vVGkrfskM!xCM6-+#y8pKp-Jlf)kwJ4uiwsgTvtN?t{Ay?hYZqU;_;H z(b>E1u1npMek9?;T7Ulky;85McUA4~)2CYQ$+KVW`ea*MTNg-zbn4Ng=fK{p_Smh_ zu695@E@V&0bgHLDJ%@yTw6S)~{UY{TW9t3>(e1tP9Ni(TIp+Uv+vkLHL9RF_-cQ8X z=WmG_-8km~?+lRtX?6Ws+2$PZc}hCRKQm+&$cB*BA@n28dI89skR{cQ_z+-2WhYL* zRcaXVB_M96&oU6N>;5GU#|9y;pSZ?k%=PEsGmy*2#5RTPs56e^s>d^yew-u5c^DCD?=gn>EPvE#L%uH8TSd3;`3yY73TuMOhAht55@{ye`2Zyetr&F?waUYf4{$(}6O)Z*Q)gl_9xLZ~Wyx*I{`7enjVjB!bfu z?9;pNny9(SR>Li7HdFi3wGX7j@WB?=19~3FxGfDGxb||WS2L8pXHXkNtt+JCfZ>}C zn;**A-dGUId2C=RjC>Jm3}`gC=~lyyawe!9`mM1lA9!2oeDED0Ro_+ED}Nev7(UR3 zyFBzZ%`Me2EfpO36CAIp+TMf6v&o7FZHD$);^Zs*sbLr5&fTEw1la|`ACr4P_JZsK z`4eP+$bpc9A%{Z#3^@XF6yzAlUm(XrPK2BcDHiov`6G@?AQnVbYX2yP)R+*Ww2n=v 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