From 4788ad7fe03d21d734418757a64ae8aea34d67a7 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Fri, 11 Oct 2024 17:28:08 -0400 Subject: [PATCH] Add settings module power-on reset --- cpld/CNT.v | 3 +- cpld/SET.v | 12 ++++++- cpld/WarpSE.v | 6 ++++ cpld/XC95144XL/WarpSE.syr | 66 ++++++++++++++++++++++++++------------- 4 files changed, 64 insertions(+), 23 deletions(-) diff --git a/cpld/CNT.v b/cpld/CNT.v index 4e9b30c..e8f7b01 100644 --- a/cpld/CNT.v +++ b/cpld/CNT.v @@ -1,6 +1,8 @@ module CNT( /* FSB clock and E clock inputs */ input CLK, input C8M, input E, + /* Power-on reset */ + output reg nPOR, /* Refresh request */ output reg RefReq, output reg RefUrg, /* Reset, button */ @@ -110,7 +112,6 @@ module CNT( always @(posedge CLK) LTimerTick <= TimerTick && LTimerTC; /* C8M duty cycle check and power-on reset */ - reg nPOR = 0; always @(posedge CLK) begin if (C8Mr[3:0]==4'b0000 || C8Mr[3:0]==4'b1111) nPOR <= 0; else if (C8Mr[1:0]==2'b01) nPOR <= 1; diff --git a/cpld/SET.v b/cpld/SET.v index 9a1203b..97d52e5 100644 --- a/cpld/SET.v +++ b/cpld/SET.v @@ -1,5 +1,6 @@ module SET( input CLK, + input nPOR, input BACT, input [11:1] A, input SetCSWR, @@ -15,7 +16,16 @@ module SET( reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR; always @(posedge CLK) begin - if (SetWRr) begin + if (!nPOR) begin + SlowTimeout[3:0] <= 4'hF; + SlowIACK <= 1; + SlowVIA <= 1; + SlowIWM <= 1; + SlowSCC <= 1; + SlowSCSI <= 1; + SlowSnd <= 1; + SlowClockGate <= 1; + end else if (SetWRr) begin SlowTimeout[3:0] <= A[11:8]; SlowIACK <= A[7]; SlowVIA <= A[6]; diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v index 2bccc56..156cc8f 100644 --- a/cpld/WarpSE.v +++ b/cpld/WarpSE.v @@ -55,6 +55,9 @@ module WarpSE( wire nRESin = nRES; wire nRESout; assign nRES = !nRESout ? 1'b0 : 1'bZ; + + /* Power-on reset */ + wire nPOR; /* AS cycle detection */ wire ASrf, BACT, BACTr; @@ -208,6 +211,7 @@ module WarpSE( wire [3:0] SlowTimeout; SET set( .CLK(FCLK), + .nPOR(nPOR), .BACT(BACT), .A(A_FSB[11:1]), .SetCSWR(SetCSWR), @@ -227,6 +231,8 @@ module WarpSE( .CLK(FCLK), .C8M(C8M), .E(E), + /* Power-on reset */ + .nPOR(nPOR), /* Refresh request */ .RefReq(RefReq), .RefUrg(RefUrg), diff --git a/cpld/XC95144XL/WarpSE.syr b/cpld/XC95144XL/WarpSE.syr index a5f4502..242a2e0 100644 --- a/cpld/XC95144XL/WarpSE.syr +++ b/cpld/XC95144XL/WarpSE.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.10 secs +Total CPU time to Xst completion: 0.08 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.10 secs +Total CPU time to Xst completion: 0.08 secs --> Reading design: WarpSE.prj @@ -75,7 +75,9 @@ wysiwyg : NO ========================================================================= * HDL Compilation * ========================================================================= +Compiling verilog file "../SET.v" in library work Compiling verilog file "../RAM.v" in library work +Module compiled Compiling verilog file "../IOBS.v" in library work Module compiled Compiling verilog file "../IOBM.v" in library work @@ -106,6 +108,8 @@ Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . +Analyzing hierarchy for module in library . + Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . @@ -129,6 +133,9 @@ Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. +Analyzing module in library . +Module is correct for synthesis. + Analyzing module in library . Module is correct for synthesis. @@ -239,11 +246,28 @@ WARNING:Xst:646 - Signal is assigned but never used. This unconnected sig Unit synthesized. +Synthesizing Unit . + Related source file is "../SET.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + + Synthesizing Unit . Related source file is "../CNT.v". Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . + Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . @@ -253,15 +277,13 @@ Synthesizing Unit . Found 2-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . - Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit down counter for signal . - Found 1-bit register for signal . Found 4-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 3 Counter(s). - inferred 11 D-type flip-flop(s). + inferred 10 D-type flip-flop(s). Unit synthesized. @@ -302,11 +324,11 @@ Macro Statistics 12-bit up counter : 1 4-bit down counter : 1 4-bit up counter : 2 -# Registers : 62 - 1-bit register : 58 +# Registers : 70 + 1-bit register : 65 2-bit register : 2 3-bit register : 1 - 4-bit register : 1 + 4-bit register : 2 # Tristates : 7 1-bit tristate buffer : 7 @@ -374,6 +396,8 @@ Optimizing unit ... implementation constraint: INIT=r : Sent implementation constraint: INIT=r : TS_FSM_FFd1 +Optimizing unit ... + Optimizing unit ... implementation constraint: INIT=s : IOS_FSM_FFd7 implementation constraint: INIT=r : DoutOE @@ -388,7 +412,6 @@ Optimizing unit ... implementation constraint: INIT=r : Timer_2 implementation constraint: INIT=r : IS_0 implementation constraint: INIT=r : IS_1 - implementation constraint: INIT=r : nPOR implementation constraint: INIT=r : Timer_3 implementation constraint: INIT=r : Timer_0 implementation constraint: INIT=r : Timer_1 @@ -423,22 +446,23 @@ Design Statistics # IOs : 80 Cell Usage : -# BELS : 647 -# AND2 : 194 -# AND3 : 27 -# AND4 : 12 +# BELS : 691 +# AND2 : 209 +# AND3 : 26 +# AND4 : 13 # AND5 : 3 # AND8 : 2 -# GND : 6 -# INV : 262 -# OR2 : 106 -# OR3 : 9 +# GND : 7 +# INV : 278 +# OR2 : 116 +# OR3 : 10 # OR4 : 4 # OR5 : 1 +# OR6 : 1 # XOR2 : 21 -# FlipFlops/Latches : 102 +# FlipFlops/Latches : 113 # FD : 61 -# FDCE : 36 +# FDCE : 47 # FDCP : 1 # FDP : 4 # IO Buffers : 73 @@ -450,11 +474,11 @@ Cell Usage : Total REAL time to Xst completion: 5.00 secs -Total CPU time to Xst completion: 5.10 secs +Total CPU time to Xst completion: 4.96 secs --> -Total memory usage is 262560 kilobytes +Total memory usage is 263392 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 3 ( 0 filtered)