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Improve refresh performance

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This commit is contained in:
Zane Kaminski 2024-10-03 19:13:23 -04:00
parent 1785fc67b8
commit 4983054120
1 changed files with 3 additions and 3 deletions
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6
cpld/CNT.v
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@ -2,7 +2,7 @@ module CNT(
/* FSB clock and E clock inputs */ /* FSB clock and E clock inputs */
input CLK, input C8M, input E, input CLK, input C8M, input E,
/* Refresh request */ /* Refresh request */
output reg RefReq, output RefUrg, output reg RefReq, output reg RefUrg,
/* Reset, button */ /* Reset, button */
output reg nRESout, input nRESin, input nIPL2, output reg nRESout, input nRESin, input nIPL2,
/* Mac PDS bus master control outputs */ /* Mac PDS bus master control outputs */
@ -34,20 +34,20 @@ module CNT(
* | 5 0101 | 1 | 0 | * | 5 0101 | 1 | 0 |
* | 6 0110 | 1 | 0 | * | 6 0110 | 1 | 0 |
* | 7 0111 | 1 | 0 | * | 7 0111 | 1 | 0 |
* | 8 1000 | 1 | 1 | * | 8 1000 | 1 | 0 |
* | 9 1001 | 1 | 1 | * | 9 1001 | 1 | 1 |
* | 10 1010 | 1 | 1 | * | 10 1010 | 1 | 1 |
* back to timer==0 * back to timer==0
*/ */
reg [3:0] Timer = 0; reg [3:0] Timer = 0;
wire TimerTC = Timer==10; wire TimerTC = Timer==10;
assign RefUrg = Timer[3];
reg TimerTick; reg TimerTick;
always @(posedge CLK) begin always @(posedge CLK) begin
if (EFall) begin if (EFall) begin
if (TimerTC) Timer <= 0; if (TimerTC) Timer <= 0;
else Timer <= Timer+1; else Timer <= Timer+1;
RefReq <= Timer!=10; RefReq <= Timer!=10;
RefUrg <= Timer==8 || Timer==9;
end end
end end
always @(posedge CLK) TimerTick <= EFall && TimerTC; always @(posedge CLK) TimerTick <= EFall && TimerTC;