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New RAM /OE control so it doesn't bus fight
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@ -37,10 +37,15 @@ module RAM(
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/* RAM control signals */
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/* RAM control signals */
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrf);
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrf);
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assign nOE = 0;//!( !nAS && RAMCS && BACTr);
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assign nLWE = !(!nLDS && RASEL && !nWE);
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assign nLWE = !(!nLDS && RASEL && !nWE);
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assign nUWE = !(!nUDS && RASEL && !nWE);
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assign nUWE = !(!nUDS && RASEL && !nWE);
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/* RAM /OE control */
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always @(posedge CLK) begin
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if (nAS) nOE <= 1;
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else nOE <= !(BACT && RAMCS0X && nWE);
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end
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/* ROM control signals */
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/* ROM control signals */
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assign nROMOE = !(!nAS && ROMCS && nWE);
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assign nROMOE = !(!nAS && ROMCS && nWE);
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assign nROMWE = !(!nAS && ROMCS4X && !nWE && BACTr);
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assign nROMWE = !(!nAS && ROMCS4X && !nWE && BACTr);
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