mirror of
https://github.com/garrettsworkshop/Warp-SE.git
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Add "new old"
This commit is contained in:
Zane Kaminski
parent
10ebdd43ba
commit
5e958a385b
120
cpld/new old/CNT.v
Normal file
120
cpld/new old/CNT.v
Normal file
@ -0,0 +1,120 @@
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module CNT(
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/* FSB clock and E clock inputs */
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input CLK, input C8M, input E,
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/* Refresh request */
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output reg RefReq, output reg RefUrg,
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/* Reset, button */
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output reg nRESout, input nRESin, input nIPL2,
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output reg nBR_IOB,
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/* QoS control */
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input BACT,
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input BACTr,
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input IOQoSCS,
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input SndQoSCS,
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input IACKCS,
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output reg IOQoSEN,
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output reg MCKE);
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/* E clock synchronization */
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reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E };
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wire EFall = Er[1] && !Er[0];
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/* C8M clock synchronization */
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reg [1:0] C8Mr; always @(posedge CLK) C8Mr[1:0] <= { C8Mr[0], C8M };
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wire C8MFall = C8Mr[1] && !C8Mr[0];
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/* NMI and reset synchronization */
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reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
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reg nRESr; always @(posedge CLK) nRESr <= nRESin;
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/* Startup sequence state */
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reg [1:0] IS = 0;
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/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
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* Refresh timer sequence
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* | Timer | RefReq | RefUrg |
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* |---------|--------|-----------|
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* | 0 0000 | 0 | 0 |
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* | 1 0001 | 1 | 0 |
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* | 2 0010 | 1 | 0 |
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* | 3 0011 | 1 | 0 |
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* | 4 0100 | 1 | 0 |
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* | 5 0101 | 1 | 0 |
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* | 6 0110 | 1 | 0 |
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* | 7 0111 | 1 | 0 |
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* | 8 1000 | 1 | 0 |
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* | 9 1001 | 1 | 1 |
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* | 10 1010 | 1 | 1 |
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* back to timer==0
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*/
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reg [3:0] Timer = 0;
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reg TimerTC;
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always @(posedge CLK) begin
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if (EFall) begin
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if (TimerTC) Timer <= 0;
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else Timer <= Timer+1;
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RefUrg <= Timer==8 || Timer==9;
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RefReq <= Timer!=10;
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TimerTC <= Timer==9;
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end
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end
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/* During init (IS!=3) long timer counts from 0 to 3072.
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* 3073 states == 43.151 ms */
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reg [11:0] LTimer;
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wire LTimerTC = LTimer[11:10]==2'b11;
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always @(posedge CLK) begin
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if (EFall && TimerTC) LTimer <= LTimer+1;
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end
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/* QoS select registers */
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reg IOQoSCSr;
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always @(posedge CLK) IOQoSCSr <= (BACT && (IOQoSCS || SndQoSCS || IACKCS)) || !nRESr;
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/* I/O QoS timer */
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reg [3:0] IOQS;
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always @(posedge CLK) begin
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if (IOQoSCSr) IOQS <= 4'hF;
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else if (IOQS==0) IOQS <= 0;
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else if (EFall && TimerTC) IOQS <= IOQS-1;
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end
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/* I/O QoS enable */
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always @(posedge CLK) if (!BACT) IOQoSEN <= IOQS!=0;
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/* MC68K clock enable */
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always @(posedge CLK) MCKE <= 1;//BACT || BACTr || !IOQoSEN || C8MFall;
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/* */
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reg LookReset;
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always @(posedge CLK) begin
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if (!nRESout) LookReset <= 0;
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else if (EFall) LookReset <= 1;
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end
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/* Startup sequence state control */
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wire ISTC = EFall && TimerTC && LTimerTC;
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always @(posedge CLK) begin
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case (IS[1:0])
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0: begin
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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nBR_IOB <= 0; // Default to request bus
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if (ISTC) IS <= 1;
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end 1: begin
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AoutOE <= 0;
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nRESout <= 0;
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nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
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if (ISTC && nIPL2r) IS <= 2;
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end 2: begin
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AoutOE <= !nBR_IOB;
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nRESout <= 0;
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if (ISTC) IS <= 3;
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end 3: begin
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nRESout <= 1; // Release reset
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if (LookReset && !nRESr) IS <= 0;
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end
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endcase
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end
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endmodule
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70
cpld/new old/CS.v
Normal file
70
cpld/new old/CS.v
Normal file
@ -0,0 +1,70 @@
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module CS(
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/* MC68HC000 interface */
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input [23:08] A, input CLK, input nRES, input nWE,
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/* AS cycle detection */
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input BACT,
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/* QoS enable input */
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input IOQoSEN,
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/* Device select outputs */
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output IOCS, output IORealCS, output IOPWCS, output IACKCS,
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output ROMCS, output ROMCS4X,
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output RAMCS, output RAMCS0X,
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output IOQoSCS, output SndQoSCS);
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/* Overlay control */
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reg Overlay;
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always @(posedge CLK) begin
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if (!BACT && !nRES) Overlay <= 1;
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else if (BACT && ROMCS4X) Overlay <= 0;
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end
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/* I/O select signals */
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assign IACKCS = A[23:20]==4'hF;
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wire VIACS = A[23:20]==4'hE;
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wire IWMCS = A[23:20]==4'hD;
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wire SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
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wire SCSICS = A[23:20]==4'h5;
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/* ROM select signals */
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assign ROMCS4X = A[23:20]==4'h4;
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assign ROMCS = Overlay || ROMCS4X;
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/* RAM select signals */
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assign RAMCS0X = A[23:22]==2'b00;
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assign RAMCS = RAMCS0X && !Overlay;
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wire VidRAMCSWR64k = A[23:16]==8'h3F && !nWE; // 3F0000-3FFFFF
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wire VidRAMCSWR = VidRAMCSWR64k; //&& (
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//A[15:12]==4'h2 || // 1792 bytes RAM, 2304 bytes video
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//A[15:12]==4'h3 || // 4096 bytes video
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//A[15:12]==4'h4 || // 4096 bytes video
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//A[15:12]==4'h5 || // 4096 bytes video
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//A[15:12]==4'h6 || // 4096 bytes video
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//A[15:12]==4'h7 || // 3200 bytes video, 896 bytes RAM
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//A[15:12]==4'hA || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
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//A[15:12]==4'hB || // 4096 bytes video
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//A[15:12]==4'hC || // 4096 bytes video
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//A[15:12]==4'hD || // 4096 bytes video
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//A[15:12]==4'hE || // 4096 bytes video
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//A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
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assign SndQoSCS = VidRAMCSWR64k && (
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((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
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((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
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assign IOQoSCS = IWMCS || VIACS || SCCCS || SCSICS;
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/* Select signals - IOB domain */
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assign IACKCS = A[23:20]==4'hF; // IACK
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assign IORealCS =
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A[23:20]==4'hF || // IACK
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A[23:20]==4'hE || // VIA
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A[23:20]==4'hD || // IWM
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A[23:20]==4'hC || // empty / fast ROM
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A[23:20]==4'hB || // SCC write
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A[23:20]==4'hA || // empty
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A[23:20]==4'h9 || // SCC read/reset
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A[23:20]==4'h8 || // empty (expansion RAM)
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A[23:20]==4'h7 || // empty (expansion RAM)
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A[23:20]==4'h6 || // empty (expansion RAM)
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A[23:20]==4'h5; // SCSI
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assign IOCS = IORealCS || VidRAMCSWR || IOQoSEN;
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assign IOPWCS = VidRAMCSWR64k && !IOQoSEN; // Posted write to video RAM only when QoS disabled
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endmodule
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37
cpld/new old/FSB.v
Normal file
37
cpld/new old/FSB.v
Normal file
@ -0,0 +1,37 @@
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module FSB(
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/* MC68HC000 interface */
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input FCLK, input nAS, output reg nDTACK, output reg nVPA,
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/* MC68HC000 clock enable */
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input MCKEi, output reg MCKE,
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/* AS cycle detection */
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output BACT, output reg BACTr,
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/* Ready inputs */
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input ROMCS,
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input RAMCS, input RAMReady,
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input IOPWCS, input IOPWReady, input IONPReady,
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input IOQoSEN,
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/* Interrupt acknowledge select */
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input IACKCS);
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/* MC68k clock enable */
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always @(negedge FCLK) MCKE <= MCKEi;
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/* AS cycle detection */
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reg ASrf = 0;
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always @(negedge FCLK) begin ASrf <= !nAS; end
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assign BACTu = !nAS || ASrf;
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assign BACT = BACTu && MCKE;
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always @(posedge FCLK) BACTr <= BACT;
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/* DTACK/VPA control */
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wire Ready = (RAMCS && !IOQoSEN && RAMReady && !IOPWCS) ||
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(RAMCS && !IOQoSEN && RAMReady && IOPWCS && IOPWReady) ||
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(ROMCS && !IOQoSEN) ||
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(IONPReady);
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always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACKCS);
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always @(posedge FCLK, posedge nAS) begin
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if (nAS) nVPA <= 1;
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else nVPA <= !(Ready && BACT && IACKCS);
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end
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endmodule
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140
cpld/new old/IOBM.v
Normal file
140
cpld/new old/IOBM.v
Normal file
@ -0,0 +1,140 @@
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module IOBM(
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/* PDS interface */
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input C16M, input C8M, input E,
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output reg nAS, output reg nLDS, output reg nUDS, output reg RnW, output reg nVMA,
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input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
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/* IO bus slave port interface */
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input IOREQ, input IORW, input IOLDS, input IOUDS,
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output reg IOACT, output reg IODONE, output reg IOBERR);
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/* C8M clock registration */
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reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
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/* I/O request input synchronization */
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reg IOREQr; always @(posedge C16M) IOREQr <= IOREQ;
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/* VPA synchronization */
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reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
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/* E clock synchronization */
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reg Er; always @(negedge C8M) begin Er <= E; end
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/* E clock state */
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reg [3:0] ES;
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always @(negedge C8M) begin
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if (!E && Er) ES <= 1;
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else if (ES==0 || ES==9) ES <= 0;
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else ES <= ES+1;
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end
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/* ETACK and VMA generation */
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wire ETACK = (ES==8) && !nVMA;
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always @(posedge C8M) begin
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if ((ES==5) && IOACT && VPAr) nVMA <= 0;
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else if(ES==0) nVMA <= 1;
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end
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/* DTACK and BERR synchronization */
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always @(negedge C8M, posedge nAS) begin
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if (nAS) begin
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IODONE <= 0;
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IOBERR <= 0;
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end else begin
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IODONE <= (!nDTACK || ETACK || !nRES);
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IOBERR <= !nBERR;
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end
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end
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/* I/O bus state */
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reg [2:0] IOS = 0;
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reg IOS0;
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always @(posedge C16M) case (IOS[2:0])
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3'h0: begin
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if (IOREQr && !C8Mr && AoutOE) begin // "IOS1"
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IOS <= 2;
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IOS0 <= 0;
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end else begin // "regular" IOS0
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IOS <= 0;
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IOS0 <= 1;
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end
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IOACT <= IOREQr;
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ALE0 <= IOREQr;
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end 3'h2: begin
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IOS <= 3;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h3: begin
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IOS <= 4;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h4: begin
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IOS <= 5;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end 3'h5: begin
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if (!C8Mr && (IODONE || IOBERR)) begin
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IOS <= 6;
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IOACT <= 0;
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end else begin
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IOS <= 5;
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IOACT <= 1;
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end
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IOS0 <= 0;
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ALE0 <= 1;
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end 3'h6: begin
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IOS <= 7;
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IOS0 <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end 3'h7: begin
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IOS <= 0;
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IOS0 <= 1;
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IOACT <= 0;
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ALE0 <= 0;
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end
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endcase
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/* PDS address and data latch control */
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always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
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reg DoutOE = 0;
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always @(posedge C16M) begin
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DoutOE <= (IOS==0 && IOREQr && !IORW && !C8Mr) ||
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(DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
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end
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assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
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/* AS, DS, RW control */
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always @(negedge C16M) begin
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nAS <= !(
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(IOS==0 && IOREQr && !C8Mr) ||
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(IOS==2) ||
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(IOS==3) ||
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(IOS==4) ||
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(IOS==5));
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RnW <= !(
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(IOS==0 && IOREQr && !IORW && !C8Mr) ||
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(!IORW && IOS==2) ||
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(!IORW && IOS==3) ||
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(!IORW && IOS==4) ||
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(!IORW && IOS==5) ||
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(!IORW && IOS==6));
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nLDS <= !(
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(IOS==0 && IOREQr && IORW && IOLDS && !C8Mr) ||
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(IOS==2 && IOLDS) ||
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(IOS==3 && IOLDS) ||
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(IOS==4 && IOLDS) ||
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(IOS==5 && IOLDS));
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nUDS <= !(
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(IOS==0 && IOREQr && IORW && IOUDS && !C8Mr) ||
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(IOS==2 && IOUDS) ||
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(IOS==3 && IOUDS) ||
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(IOS==4 && IOUDS) ||
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(IOS==5 && IOUDS));
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end
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endmodule
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143
cpld/new old/IOBS.v
Normal file
143
cpld/new old/IOBS.v
Normal file
@ -0,0 +1,143 @@
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module IOBS(
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/* MC68HC000 interface */
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input CLK, input nWE, input nAS, input nLDS, input nUDS,
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/* AS cycle detection */
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input BACT,
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/* Select signals */
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input IOCS, input IORealCS, input IOPWCS,
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/* FSB cycle termination outputs */
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output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
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/* Read data OE control */
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output nDinOE,
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/* IOB master controller interface */
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output reg IOREQ, output reg IORW,
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input IOACT, input IODONEin, input IOBERR,
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/* FIFO primary level control */
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output reg ALE0, output reg IOL0, output reg IOU0,
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/* FIFO secondary level control */
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output reg ALE1);
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/* IOACT input synchronization */
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reg IOACTr = 0; always @(posedge CLK) IOACTr <= IOACT;
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/* IODTACK input synchronization */
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reg IODONEr; always @(posedge CLK) IODONEr <= IODONEin;
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wire IODONE = IODONEr;
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/* Read data OE control */
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assign nDinOE = !(!nAS && IORealCS && nWE);
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/* I/O transfer state
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* TS0 - I/O bridge idle:
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* asserts IOREQ
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* transitions to TS3 when BACT && IOCS && !ALE1 && !Sent
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* TS3 - starting I/O transfer:
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latches LDS and UDS from FSB or FIFO secondary level
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transitions immediately to TS2
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* TS2 - waiting for IOBM to begin:
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transitions to TS1 when IOACT true
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* TS1 - waiting for IOBM to finish:
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* transitions to TS1 when IOACT false */
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reg [1:0] TS = 0;
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reg Sent = 0;
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/* FIFO secondary level control */
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reg Load1; reg Clear1;
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reg IORW1; reg IOL1; reg IOU1;
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always @(posedge CLK) begin // ALE and R/W load control
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// If write currently posting (TS!=0),
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// I/O selected, and FIFO secondary level empty
|
||||
if (BACT && IOPWCS && !ALE1 && !Sent && TS!=0) begin
|
||||
// Latch R/W now but latch address and LDS/UDS next cycle
|
||||
IORW1 <= nWE;
|
||||
Load1 <= 1;
|
||||
end else Load1 <= 0;
|
||||
end
|
||||
always @(posedge CLK) begin // ALE clear control
|
||||
// Make address latch transparent in cycle after TS3
|
||||
// (i.e. first TS2 cycle that's not part of current write)
|
||||
if (TS==1) Clear1 <= 1;
|
||||
else Clear1 <= 0;
|
||||
end
|
||||
always @(posedge CLK) begin // LDS, UDS, ALE control
|
||||
if (Load1) begin // Latch address, LDS, UDS when Load1 true
|
||||
ALE1 <= 1;
|
||||
IOL1 <= !nLDS;
|
||||
IOU1 <= !nUDS;
|
||||
end else if (Clear1) ALE1 <= 0;
|
||||
end
|
||||
|
||||
/* FIFO primary level control */
|
||||
always @(posedge CLK) begin
|
||||
if (TS==0) begin
|
||||
// Start IOREQ if FIFO secondary level occupied or FSB request
|
||||
if (ALE1 || (BACT && IOCS && !ALE1 && !Sent)) begin
|
||||
// Request transfer from IOBM
|
||||
TS <= 1;
|
||||
IOREQ <= 1;
|
||||
end else begin // Otherwise stay in idle
|
||||
TS <= 0;
|
||||
IOREQ <= 0;
|
||||
end
|
||||
// Latch R/W and data strobes from FIFO secondary or FSB
|
||||
if (ALE1) begin
|
||||
IORW <= IORW1;
|
||||
IOL0 <= IOL1;
|
||||
IOU0 <= IOU1;
|
||||
end else begin
|
||||
IORW <= nWE;
|
||||
IOL0 <= !nLDS;
|
||||
IOU0 <= !nUDS;
|
||||
end
|
||||
|
||||
ALE0 <= 0;
|
||||
end else if (TS==1) begin
|
||||
TS <= 2; // Always go to TS2
|
||||
IOREQ <= 1; // Keep IOREQ active
|
||||
ALE0 <= 1; // Latch address (and data)
|
||||
// Latch data strobes again from FIFO or FSB as appropriate
|
||||
if (ALE1) begin
|
||||
IOL0 <= IOL1;
|
||||
IOU0 <= IOU1;
|
||||
end else begin
|
||||
IOL0 <= !nLDS;
|
||||
IOU0 <= !nUDS;
|
||||
end
|
||||
end else if (TS==2) begin
|
||||
// Wait for IOACT (transfer started) then withdraw IOREQ and enter TS1
|
||||
if (IOACTr) begin
|
||||
TS <= 3;
|
||||
IOREQ <= 0;
|
||||
end else begin
|
||||
TS <= 2;
|
||||
IOREQ <= 1;
|
||||
end
|
||||
ALE0 <= 1; // Keep address latched
|
||||
end else if (TS==3) begin
|
||||
// Wait for IOACT low (transfer over) before going back to idle
|
||||
if (!IOACTr) TS <= 0;
|
||||
else TS <= 3;
|
||||
IOREQ <= 0;
|
||||
ALE0 <= 0; // Release addr latch since it's controlled by IOBM now
|
||||
end
|
||||
end
|
||||
|
||||
/* Sent control */
|
||||
always @(posedge CLK) begin
|
||||
if (!BACT) Sent <= 0;
|
||||
else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
|
||||
end
|
||||
|
||||
/* Nonposted and posted ready */
|
||||
assign IOPWReady = !ALE1 || Sent; // Posted write reaedy
|
||||
always @(posedge CLK) begin // Nonposted read/write ready
|
||||
if (!BACT) IONPReady <= 0;
|
||||
else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
|
||||
end
|
||||
|
||||
/* BERR control */
|
||||
always @(posedge CLK) begin
|
||||
if (!BACT) nBERR_FSB <= 1;
|
||||
else if (Sent && IOBERR) nBERR_FSB <= 0;
|
||||
end
|
||||
endmodule
|
||||
162
cpld/new old/RAM.v
Normal file
162
cpld/new old/RAM.v
Normal file
@ -0,0 +1,162 @@
|
||||
module RAM(
|
||||
/* MC68HC000 interface */
|
||||
input CLK, input [21:1] A, input nWE,
|
||||
input nAS, input nLDS, input nUDS, input nDTACK,
|
||||
/* AS cycle detection */
|
||||
input BACT, input BACTr,
|
||||
/* Select and ready signals */
|
||||
input RAMCS, input RAMCS0X, input ROMCS, input ROMCS4X,
|
||||
/* RAM ready output */
|
||||
output reg RAMReady,
|
||||
/* Refresh Counter Interface */
|
||||
input RefReqIn, input RefUrgIn,
|
||||
/* DRAM and NOR flash interface */
|
||||
output [11:0] RA, output nRAS, output reg nCAS,
|
||||
output nLWE, output nUWE, output reg nOE, output nROMOE, output nROMWE);
|
||||
|
||||
/* BACT and /DTACK registration */
|
||||
reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
|
||||
|
||||
/* RAM control state */
|
||||
reg [2:0] RS = 0;
|
||||
reg RASEN = 0;
|
||||
reg RASEL = 0;
|
||||
reg RASrr = 0;
|
||||
reg RASrf = 0;
|
||||
|
||||
/* Refresh command generation */
|
||||
reg RefDone; // Refresh done "remember"
|
||||
always @(posedge CLK) begin
|
||||
if (!RefReqIn && !RefUrgIn) RefDone <= 0;
|
||||
else if (RS[2]) RefDone <= 1;
|
||||
end
|
||||
wire RefReq = RefReqIn && !RefDone;
|
||||
wire RefUrg = RefUrgIn && !RefDone;
|
||||
|
||||
/* RAM control signals */
|
||||
assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
|
||||
assign nLWE = !(!nLDS && !nWE && RASEL);
|
||||
assign nUWE = !(!nUDS && !nWE && RASEL);
|
||||
always @(posedge CLK) nOE <= !(BACT && nWE && !(BACTr && DTACKr));
|
||||
|
||||
/* ROM control signals */
|
||||
assign nROMOE = !(ROMCS && !nAS && nWE);
|
||||
assign nROMWE = !(ROMCS4X && !nAS && !nWE);
|
||||
|
||||
/* RAM address mux (and ROM address on RA8) */
|
||||
// RA11 doesn't do anything so both should be identical.
|
||||
assign RA[11] = !RASEL ? A[19] : A[20]; // ROM address 19
|
||||
assign RA[03] = !RASEL ? A[19] : A[20];
|
||||
// RA10 has only row so different rows but same column.
|
||||
assign RA[10] = !RASEL ? A[17] : A[07];
|
||||
assign RA[02] = !RASEL ? A[16] : A[07];
|
||||
// Remainder of RA bus is unpaired
|
||||
assign RA[09] = !RASEL ? A[15] : A[08];
|
||||
assign RA[08] = !RASEL ? A[18] : A[21]; // ROM address 18
|
||||
assign RA[07] = !RASEL ? A[14] : A[06];
|
||||
assign RA[06] = !RASEL ? A[13] : A[05];
|
||||
assign RA[05] = !RASEL ? A[12] : A[04];
|
||||
assign RA[04] = !RASEL ? A[11] : A[03];
|
||||
assign RA[01] = !RASEL ? A[10] : A[02];
|
||||
assign RA[00] = !RASEL ? A[09] : A[01];
|
||||
|
||||
wire RS0toRef = // Refresh during first clock of non-RAM access
|
||||
(RefReq && BACT && !BACTr && !RAMCS0X) ||
|
||||
// Urgent refresh while bus inactive
|
||||
(RefUrg && !BACT) ||
|
||||
// Urgent refresh during non-RAM access
|
||||
(RefUrg && BACT && !RAMCS0X) ||
|
||||
// Urgent refresh if RAM is disabled
|
||||
(RefUrg && !RASEN);
|
||||
|
||||
always @(posedge CLK) begin
|
||||
case (RS[2:0])
|
||||
0: begin // Idle/ready
|
||||
if (RS0toRef) begin // Refresh RAS I
|
||||
RS <= 4;
|
||||
RASEL <= 0;
|
||||
RASrr <= 1;
|
||||
RASEN <= 0;
|
||||
RAMReady <= 0;
|
||||
end else if (BACT && RAMCS && RASEN) begin // Access RAM
|
||||
RS <= 1;
|
||||
RASEL <= 1;
|
||||
RASrr <= 1;
|
||||
RASEN <= 1;
|
||||
RAMReady <= 1;
|
||||
end else begin // Stay in idle/ready
|
||||
RS <= 0;
|
||||
RASEL <= 0;
|
||||
RASrr <= 0;
|
||||
RASEN <= 1;
|
||||
RAMReady <= 1;
|
||||
end
|
||||
end 1: begin // RAM access
|
||||
RS <= 2;
|
||||
RASEL <= 1;
|
||||
RASrr <= 0;
|
||||
RASEN <= 0;
|
||||
RAMReady <= 1;
|
||||
end 2: begin // finish RAM access
|
||||
if (DTACKr) RS <= 3; // Cycle ending
|
||||
else RS <= 2; // Cycle not ending yet
|
||||
RASEL <= 0;
|
||||
RASrr <= 0;
|
||||
RASEN <= 0;
|
||||
RAMReady <= 1;
|
||||
end 3: begin //AS cycle complete
|
||||
if (RefUrg) begin // Refresh RAS
|
||||
RS <= 4;
|
||||
RASEL <= 0;
|
||||
RASrr <= 1;
|
||||
RASEN <= 0;
|
||||
RAMReady <= 0;
|
||||
end else begin // Cycle ended so go abck to idle/ready
|
||||
RS <= 0;
|
||||
RASEL <= 0;
|
||||
RASrr <= 0;
|
||||
RASEN <= 1;
|
||||
RAMReady <= 1;
|
||||
end
|
||||
end 4: begin // Refresh RAS II
|
||||
RS <= 5;
|
||||
RASEL <= 0;
|
||||
RASrr <= 1;
|
||||
RASEN <= 0;
|
||||
RAMReady <= 0;
|
||||
end 5: begin // Refresh precharge I
|
||||
RS <= 6;
|
||||
RASEL <= 0;
|
||||
RASrr <= 0;
|
||||
RASEN <= 0;
|
||||
RAMReady <= 0;
|
||||
end 6: begin // Refresh precharge II
|
||||
RS <= 7;
|
||||
RASEL <= 0;
|
||||
RASrr <= 0;
|
||||
RASEN <= 0;
|
||||
RAMReady <= 0;
|
||||
end 7: begin // Reenable RAM and go to idle/ready
|
||||
RS <= 0;
|
||||
RASEL <= 0;
|
||||
RASrr <= 0;
|
||||
RASEN <= 1;
|
||||
RAMReady <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
always @(negedge CLK) begin
|
||||
RASrf <= RS==1;
|
||||
case (RS[2:0])
|
||||
0: nCAS <= !RS0toRef;
|
||||
1: nCAS <= 0;
|
||||
2: nCAS <= DTACKr;
|
||||
3: nCAS <= !RefUrg;
|
||||
4: nCAS <= !RefUrg;
|
||||
5: nCAS <= 1;
|
||||
6: nCAS <= 1;
|
||||
7: nCAS <= 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
180
cpld/new old/WarpSE.v
Normal file
180
cpld/new old/WarpSE.v
Normal file
@ -0,0 +1,180 @@
|
||||
module WarpSE(
|
||||
input [23:1] A_FSB,
|
||||
output [23:22] GA,
|
||||
input nAS_FSB,
|
||||
input nLDS_FSB,
|
||||
input nUDS_FSB,
|
||||
input nWE_FSB,
|
||||
output nDTACK_FSB,
|
||||
output nVPA_FSB,
|
||||
output nBERR_FSB,
|
||||
input FCLK,
|
||||
input C16M,
|
||||
input C8M,
|
||||
input E,
|
||||
input nDTACK_IOB,
|
||||
input nVPA_IOB,
|
||||
output nVMA_IOB,
|
||||
output nAS_IOB,
|
||||
output nUDS_IOB,
|
||||
output nLDS_IOB,
|
||||
output RnW_IOB,
|
||||
output nBR_IOB,
|
||||
input nBG_IOB,
|
||||
input nBERR_IOB,
|
||||
inout nRES,
|
||||
input nIPL2,
|
||||
output nROMOE,
|
||||
output nRAMLWE,
|
||||
output nRAMUWE,
|
||||
output nROMWE,
|
||||
output nRAS,
|
||||
output nCAS,
|
||||
output [11:0] RA,
|
||||
output nOE,
|
||||
output nADoutLE0,
|
||||
output nADoutLE1,
|
||||
output nAoutOE,
|
||||
output nDoutOE,
|
||||
output nDinOE,
|
||||
output nDinLE,
|
||||
output MCKE,
|
||||
input [5:0] DBG);
|
||||
|
||||
/* GA gated (translated) address output */
|
||||
assign GA[23:22] = A_FSB[23:22];
|
||||
/*assign GA[23:22] = (
|
||||
// $800000-$8FFFFF to $000000-$0FFFFF (1 MB)
|
||||
(A_FSB[23:20]==4'h8) ||
|
||||
// $700000-$7EFFFF to $300000-$3EFFFF (960 kB)
|
||||
(A_FSB[23:20]==4'h7 && A_FSB[19:16]!=4'hF) ||
|
||||
// $600000-$6FFFFF to $200000-$2FFFFF (1 MB)
|
||||
(A_FSB[23:20]==4'h6)) ? 2'b00 : A_FSB[23:22];*/
|
||||
|
||||
/* Reset input and open-drain output */
|
||||
wire nRESin = nRES;
|
||||
wire nRESout;
|
||||
assign nRES = !nRESout ? 1'b0 : 1'bZ;
|
||||
|
||||
/* AS cycle detection */
|
||||
wire BACT, BACTr;
|
||||
|
||||
/* MC68k clock enable */
|
||||
wire MCKEi;
|
||||
|
||||
/* Refresh request/ack signals */
|
||||
wire RefReq, RefUrg;
|
||||
|
||||
/* QoS enable */
|
||||
wire IOQoSEN;
|
||||
|
||||
/* FSB chip select signals */
|
||||
wire IOCS, IORealCS, IOPWCS, IACKCS;
|
||||
wire ROMCS, ROMCS4X;
|
||||
wire RAMCS, RAMCS0X;
|
||||
wire IOQoSCS, SndQoSCS;
|
||||
CS cs(
|
||||
/* MC68HC000 interface */
|
||||
A_FSB[23:08], FCLK, nRESin, nWE_FSB,
|
||||
/* /AS cycle detection */
|
||||
BACT,
|
||||
/* QoS enable input */
|
||||
IOQoSEN,
|
||||
/* Device select outputs */
|
||||
IOCS, IORealCS, IOPWCS, IACKCS,
|
||||
ROMCS, ROMCS4X,
|
||||
RAMCS, RAMCS0X,
|
||||
IOQoSCS, SndQoSCS);
|
||||
|
||||
wire RAMReady;
|
||||
RAM ram(
|
||||
/* MC68HC000 interface */
|
||||
FCLK, A_FSB[21:1], nWE_FSB,
|
||||
nAS_FSB, nLDS_FSB, nUDS_FSB, nDTACK_FSB,
|
||||
/* AS cycle detection inputs */
|
||||
BACT, BACTr,
|
||||
/* RAM and ROM select inputs */
|
||||
RAMCS, RAMCS0X, ROMCS, ROMCS4X,
|
||||
/* RAM ready output */
|
||||
RAMReady,
|
||||
/* Refresh Counter Interface */
|
||||
RefReq, RefUrg,
|
||||
/* DRAM and NOR flash interface */
|
||||
RA[11:0], nRAS, nCAS,
|
||||
nRAMLWE, nRAMUWE, nOE, nROMOE, nROMWE);
|
||||
|
||||
wire IONPReady, IOPWReady;
|
||||
wire IOREQ, IORW;
|
||||
wire IOL0, IOU0;
|
||||
wire ALE0S, ALE0M, ALE1;
|
||||
assign nADoutLE0 = ~(ALE0S || ALE0M);
|
||||
assign nADoutLE1 = ~ALE1;
|
||||
wire IOACT, IODONE, IOBERR;
|
||||
IOBS iobs(
|
||||
/* MC68HC000 interface */
|
||||
FCLK, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
|
||||
/* AS cycle detection */
|
||||
BACT,
|
||||
/* Select signals */
|
||||
IOCS, IORealCS, IOPWCS,
|
||||
/* FSB cycle termination outputs */
|
||||
IONPReady, IOPWReady, nBERR_FSB,
|
||||
/* Read data OE control */
|
||||
nDinOE,
|
||||
/* IOB Master Controller Interface */
|
||||
IOREQ, IORW,
|
||||
IOACT, IODONE, IOBERR,
|
||||
/* FIFO primary level control */
|
||||
ALE0S, IOL0, IOU0,
|
||||
/* FIFO secondary level control */
|
||||
ALE1);
|
||||
|
||||
wire AoutOE;
|
||||
assign nAoutOE = !AoutOE;
|
||||
wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, RnW_IOBout, nVMA_IOBout;
|
||||
assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
|
||||
assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
|
||||
assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
|
||||
assign RnW_IOB = AoutOE ? RnW_IOBout : 1'bZ;
|
||||
assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
|
||||
IOBM iobm(
|
||||
/* PDS interface */
|
||||
C16M, C8M, E,
|
||||
nAS_IOBout, nLDS_IOBout, nUDS_IOBout, RnW_IOBout, nVMA_IOBout,
|
||||
nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
|
||||
/* PDS address and data latch control */
|
||||
AoutOE, nDoutOE, ALE0M, nDinLE,
|
||||
/* IO bus slave port interface */
|
||||
IOREQ, IORW, IOL0, IOU0,
|
||||
IOACT, IODONE, IOBERR);
|
||||
|
||||
CNT cnt(
|
||||
/* FSB clock and E clock inputs */
|
||||
FCLK, C8M, E,
|
||||
/* Refresh request */
|
||||
RefReq, RefUrg,
|
||||
/* Reset, button */
|
||||
nRESout, nRESin, nIPL2,
|
||||
/* Mac PDS bus master control outputs */
|
||||
AoutOE, nBR_IOB,
|
||||
/* QoS control */
|
||||
BACT, BACTr,
|
||||
IOQoSCS, SndQoSCS, IACKCS,
|
||||
IOQoSEN, MCKEi);
|
||||
|
||||
FSB fsb(
|
||||
/* MC68HC000 interface */
|
||||
FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
|
||||
/* MC68HC000 clock enable */
|
||||
MCKEi, MCKE,
|
||||
/* FSB cycle detection */
|
||||
BACT, BACTr,
|
||||
/* Ready inputs */
|
||||
ROMCS4X,
|
||||
RAMCS0X, RAMReady,
|
||||
IOPWCS, IOPWReady, IONPReady,
|
||||
IOQoSEN,
|
||||
/* Interrupt acknowledge select */
|
||||
IACKCS);
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user