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Improved overlay latching
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parent
50451da0a5
commit
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15
cpld/CS.v
15
cpld/CS.v
@ -7,12 +7,14 @@ module CS(
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output IOCS, output IOPWCS, output IACS, output ROMCS, output RAMCS, output SndRAMCSWR);
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output IOCS, output IOPWCS, output IACS, output ROMCS, output RAMCS, output SndRAMCSWR);
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/* Overlay control */
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/* Overlay control */
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reg nOverlay = 0;
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reg nOverlay = 0; wire Overlay = !nOverlay;
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wire Overlay = ~nOverlay;
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reg ODCSr;
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wire ODCS = (A[23:20]==4'h4); // Disable overlay
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always @(posedge CLK) begin
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always @(posedge CLK, negedge nRES) begin
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ODCSr <= (A[23:20]==4'h4) && BACT;
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if (!BACT) begin
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if (!nRES) nOverlay <= 0;
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if (!nRES) nOverlay <= 0;
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else if (BACT && ODCS) nOverlay <= 1;
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else if (ODCSr) nOverlay <= 1;
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end
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end
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end
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/* Select signals - FSB domain */
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/* Select signals - FSB domain */
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@ -35,8 +37,7 @@ module CS(
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((A[15:12]==4'hF) && ((A[11:8]==4'hD) || (A[11:8]==4'hE) || (A[11:8]==4'hF))) ||
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((A[15:12]==4'hF) && ((A[11:8]==4'hD) || (A[11:8]==4'hE) || (A[11:8]==4'hF))) ||
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((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
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((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
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assign ROMCS = ((A[23:20]==4'h0) && Overlay) ||
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assign ROMCS = ((A[23:20]==4'h0) && Overlay) || (A[23:20]==4'h4);
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(A[23:20]==4'h4);
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/* Select signals - IOB domain */
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/* Select signals - IOB domain */
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assign IACS = (A[23:08]==16'hFFFF); // IACK
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assign IACS = (A[23:08]==16'hFFFF); // IACK
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