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Update RAM.v

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Remove old RAMDIS1 stuff
This commit is contained in:
Zane Kaminski 2023-03-20 03:39:56 -04:00
parent a2fc4dc4de
commit 6685e22a7a
1 changed files with 0 additions and 14 deletions
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14
cpld/RAM.v
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@ -97,31 +97,26 @@ module RAM(
RS <= 2; RS <= 2;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 1; RASEL <= 1;
RAMDIS1 <= 1;
end else if (RefFromRS0Pre) begin end else if (RefFromRS0Pre) begin
// Urgent ref can start during long RAM cycle after access. // Urgent ref can start during long RAM cycle after access.
// Must insert one extra precharge state first by going to RS1. // Must insert one extra precharge state first by going to RS1.
RS <= 1; RS <= 1;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 1;
end else if (BACT && RAMCS && RAMEN) begin end else if (BACT && RAMCS && RAMEN) begin
// RAM access cycle has priority over urgent refresh if RAM access already begun // RAM access cycle has priority over urgent refresh if RAM access already begun
RS <= 5; RS <= 5;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 1; RASEL <= 1;
RAMDIS1 <= 0;
end else if (RAMRefFromRS0Pre) begin end else if (RAMRefFromRS0Pre) begin
RS <= 1; RS <= 1;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 1;
end else begin end else begin
// No RAM access/refresh requests pending // No RAM access/refresh requests pending
RS <= 0; RS <= 0;
RAMReady <= 1; RAMReady <= 1;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 0;
end end
RefRAS <= 0; RefRAS <= 0;
end else if (RS==1) begin end else if (RS==1) begin
@ -129,42 +124,36 @@ module RAM(
RS <= 2; RS <= 2;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 1; RASEL <= 1;
RAMDIS1 <= 1;
RefRAS <= 0; RefRAS <= 0;
end else if (RS==2) begin end else if (RS==2) begin
// Refresh RAS pulse asserted ater RS2. // Refresh RAS pulse asserted ater RS2.
RS <= 3; RS <= 3;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 1; RASEL <= 1;
RAMDIS1 <= 1;
RefRAS <= 1; RefRAS <= 1;
end else if (RS==3) begin end else if (RS==3) begin
// RS3 implements requisite RAS pulse width. // RS3 implements requisite RAS pulse width.
RS <= 4; RS <= 4;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 1;
RefRAS <= 1; RefRAS <= 1;
end else if (RS==4) begin end else if (RS==4) begin
// RS4 implements precharge after RAM refresh. // RS4 implements precharge after RAM refresh.
RS <= 7; RS <= 7;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 1;
RefRAS <= 0; RefRAS <= 0;
end else if (RS==5) begin end else if (RS==5) begin
// RS5 is first state of R/W operation // RS5 is first state of R/W operation
RS <= 6; RS <= 6;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 1; RASEL <= 1;
RAMDIS1 <= 0;
RefRAS <= 0; RefRAS <= 0;
end else if (RS==6) begin end else if (RS==6) begin
// RS6 is second state of R/W operation // RS6 is second state of R/W operation
RS <= 7; RS <= 7;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 0;
RefRAS <= 0; RefRAS <= 0;
end else if (RS==7) begin end else if (RS==7) begin
// RS7 is final state of R/W or refresh operation. // RS7 is final state of R/W or refresh operation.
@ -173,7 +162,6 @@ module RAM(
// we know /RAS has been in precharge so we can go to RS2. // we know /RAS has been in precharge so we can go to RS2.
RS <= 2; RS <= 2;
RAMReady <= 0; RAMReady <= 0;
RAMDIS1 <= 1;
RASEL <= 1; RASEL <= 1;
end else if (BACT && RefUrgent) begin end else if (BACT && RefUrgent) begin
// But if /AS cycle hasn't terminated and we need to refresh, // But if /AS cycle hasn't terminated and we need to refresh,
@ -181,13 +169,11 @@ module RAM(
RS <= 1; RS <= 1;
RAMReady <= 0; RAMReady <= 0;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 1;
end else begin end else begin
// Otherwise if no urgent refresh request, go to RS0. // Otherwise if no urgent refresh request, go to RS0.
RS <= 0; RS <= 0;
RAMReady <= 1; RAMReady <= 1;
RASEL <= 0; RASEL <= 0;
RAMDIS1 <= 0;
end end
RefRAS <= 0; RefRAS <= 0;
end end