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Better but RAM still not right... soldering error in prototype?

This commit is contained in:
Zane Kaminski 2023-04-01 08:25:24 -04:00
parent f00f100ca7
commit 6fdd69366e
34 changed files with 3001 additions and 3006 deletions
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6
cpld/CS.v
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@ -18,7 +18,7 @@ module CS(
end
/* Select signals - FSB domain */
assign RAMCS = 0;//(A[23:22]==2'b00) && !Overlay; // 000000-3FFFFF when overlay disabled
assign RAMCS = (A[23:22]==2'b00) && !Overlay; // 000000-3FFFFF when overlay disabled
wire VidRAMCSWR64k = RAMCS && !nWE && (A[21:20]==2'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF / 7F0000-7FFFFF
wire VidRAMCSWR = VidRAMCSWR64k && (
(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
@ -53,7 +53,7 @@ module CS(
(A[23:20]==4'hD) || // IWM
(A[23:20]==4'hE) || // VIA
(A[23:20]==4'hF) || // IACK
VidRAMCSWR || (A[23:22]==2'b00);
assign IOPWCS = (A[23:22]==2'b00)&& !nWE;
VidRAMCSWR;// || (A[23:22]==2'b00);
assign IOPWCS = (A[23:22]==2'b00) && IOCS && !nWE;
endmodule

2
cpld/XC95144XL/WarpSE.bld
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@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 151012 kilobytes
Total memory usage is 150692 kilobytes
Writing NGD file "WarpSE.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec

6
cpld/XC95144XL/WarpSE.cmd_log
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@ -297,3 +297,9 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt
XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga
hprep6 -s IEEE1149 -n WarpSE -i WarpSE

14
cpld/XC95144XL/WarpSE.jed
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@ -1,5 +1,5 @@
Programmer Jedec Bit Map
Date Extracted: Sat Apr 01 07:57:38 2023
Date Extracted: Sat Apr 01 08:21:57 2023
QF93312*
QP100*
@ -353,7 +353,7 @@ L0014944 00000000 00000000 00010001 00000000 00000001 00000000 00000000 00000010
L0015008 00000000 00000000 00000011 00000000 00000011 00000000 00000000 00000000*
L0015072 00000000 00000000 00100000 00000000 00000001 00000000 00000000 00000000*
L0015136 00000000 00000000 00100011 00000000 00000010 00000000 00000000 00100011*
L0015200 00000000 00000000 00100001 00000000 00000011 00000000 00000100 10000000*
L0015200 00000000 00000000 00100001 00000000 00000011 00000000 00000100 00000000*
L0015264 000000 000000 001000 000000 000000 000000 000000 100000*
L0015312 000000 000000 001000 000000 000000 000000 000000 000000*
L0015360 000000 000000 001000 000000 000000 000000 000000 000000*
@ -1301,8 +1301,8 @@ L0069568 00000000 00000000 00000000 00000000 00000000 00100000 00000000 11000000
L0069632 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000*
L0069696 000000 000000 000000 000000 000000 000000 000000 110000*
L0069744 000000 000000 000000 000000 000000 000000 000000 001000*
L0069792 000000 000000 000000 000000 000000 100000 000000 101000*
L0069840 000000 000000 000000 000000 000000 000000 000000 101000*
L0069792 000000 000000 000000 000000 000000 100000 000000 001000*
L0069840 000000 000000 000000 000000 000000 000000 000000 001000*
L0069888 000000 000000 000000 000000 000000 000000 000000 100001*
L0069936 000000 000000 000000 000000 000000 000000 000000 100000*
L0069984 00000000 00000000 00000000 00001000 00000000 00000000 00000000 01000000*
@ -1628,7 +1628,7 @@ L0088384 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
L0088448 00000000 00000000 00110000 00000000 00000000 00000000 00000000 00000000*
L0088512 00000000 00000000 00000000 00000000 00000000 10010000 00000000 00000000*
L0088576 00000000 00000000 00000000 00000000 00000000 00100000 00000000 00100000*
L0088640 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000*
L0088640 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
L0088704 000000 000000 000000 000000 000000 000000 000000 100000*
L0088752 000000 000000 000001 000000 000000 000000 000000 000000*
L0088800 000000 000000 000000 000000 000000 001100 000000 000000*
@ -1710,5 +1710,5 @@ L0093120 000000 000000 100000 000001 100000 000000 000000 000001*
L0093168 000000 000000 100000 000001 100000 000000 000000 000001*
L0093216 000000 000000 000000 000000 100000 000000 000000 001001*
L0093264 000000 000000 000000 000000 100000 000000 000000 001001*
C1BD6*
2A54
C1BCC*
2A5C

18
cpld/XC95144XL/WarpSE.mfd
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@ -941,12 +941,10 @@ INPUTS | 12 | A_FSB<23> | A_FSB<22> | cs/nOverlay | nAS_FSB | ram/RS_FSM_FFd
INPUTMC | 9 | 6 | 2 | 7 | 9 | 7 | 2 | 2 | 4 | 0 | 0 | 0 | 2 | 2 | 17 | 7 | 6 | 7 | 1
INPUTP | 3 | 36 | 30 | 54
IMPORTS | 1 | 7 | 1
EQ | 17 |
EQ | 15 |
ram/RAMEN.D = !ram/RS_FSM_FFd2 & ram/RS_FSM_FFd1 & ram/RAMEN
# !ram/RS_FSM_FFd1 & !ram/RefUrg & ram/RAMEN &
ram/BACTr
# !ram/RS_FSM_FFd1 & !ram/RefUrg & ram/RAMEN &
!ram/RefReq
# !ram/RefUrg & ram/RAMEN & ram/BACTr
# !ram/RefUrg & ram/RAMEN & !ram/RefReq
# !A_FSB<23> & !A_FSB<22> & cs/nOverlay & !nAS_FSB &
!ram/RS_FSM_FFd1 & ram/RAMEN
# !A_FSB<23> & !A_FSB<22> & cs/nOverlay &
@ -954,8 +952,8 @@ EQ | 17 |
;Imported pterms FB8_2
# ram/RS_FSM_FFd2 & !ram/RS_FSM_FFd3 & ram/RAMEN
# !ram/RS_FSM_FFd1 & ram/RS_FSM_FFd3 & ram/RAMEN
# nAS_FSB & ram/RS_FSM_FFd2 & ram/RS_FSM_FFd1 &
ram/RS_FSM_FFd3 & !ram/RefUrg & !fsb/ASrf
# ram/RS_FSM_FFd2 & ram/RS_FSM_FFd1 &
ram/RS_FSM_FFd3 & !ram/RefUrg
# nAS_FSB & !ram/RS_FSM_FFd2 & !ram/RS_FSM_FFd1 &
!ram/RS_FSM_FFd3 & !ram/RefUrg & !fsb/ASrf;
ram/RAMEN.CLK = FCLK; // GCK
@ -1750,7 +1748,7 @@ EQ | 2 |
MACROCELL | 7 | 1 | A_FSB_19_IBUF$BUF0
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 7 | 2
INPUTS | 8 | A_FSB<19> | ram/RS_FSM_FFd2 | ram/RS_FSM_FFd3 | ram/RAMEN | ram/RS_FSM_FFd1 | nAS_FSB | ram/RefUrg | fsb/ASrf
INPUTS | 8 | A_FSB<19> | ram/RS_FSM_FFd2 | ram/RS_FSM_FFd3 | ram/RAMEN | ram/RS_FSM_FFd1 | ram/RefUrg | nAS_FSB | fsb/ASrf
INPUTMC | 6 | 7 | 6 | 7 | 8 | 7 | 2 | 7 | 9 | 0 | 0 | 2 | 4
INPUTP | 2 | 26 | 54
EXPORTS | 1 | 7 | 2
@ -1758,8 +1756,8 @@ EQ | 7 |
RA<11> = A_FSB<19>;
A_FSB_19_IBUF$BUF0.EXP = ram/RS_FSM_FFd2 & !ram/RS_FSM_FFd3 & ram/RAMEN
# !ram/RS_FSM_FFd1 & ram/RS_FSM_FFd3 & ram/RAMEN
# nAS_FSB & ram/RS_FSM_FFd2 & ram/RS_FSM_FFd1 &
ram/RS_FSM_FFd3 & !ram/RefUrg & !fsb/ASrf
# ram/RS_FSM_FFd2 & ram/RS_FSM_FFd1 &
ram/RS_FSM_FFd3 & !ram/RefUrg
# nAS_FSB & !ram/RS_FSM_FFd2 & !ram/RS_FSM_FFd1 &
!ram/RS_FSM_FFd3 & !ram/RefUrg & !fsb/ASrf

2
cpld/XC95144XL/WarpSE.nga
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2
cpld/XC95144XL/WarpSE.ngc
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2
cpld/XC95144XL/WarpSE.ngd
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2
cpld/XC95144XL/WarpSE.ngr
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2
cpld/XC95144XL/WarpSE.pad
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@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
4- 1-2023 7:57AM
4- 1-2023 8:21AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'

12
cpld/XC95144XL/WarpSE.rpt
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@ -1,7 +1,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: WarpSE Date: 4- 1-2023, 7:57AM
Design Name: WarpSE Date: 4- 1-2023, 8:21AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
@ -1436,15 +1436,13 @@ ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
FDCPE_ram/RAMEN: FDCPE port map (ram/RAMEN,ram/RAMEN_D,FCLK,'0','0');
ram/RAMEN_D <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN)
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND ram/RAMEN)
OR (nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND NOT ram/RefUrg)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RAMEN)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
ram/BACTr)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
NOT ram/RefReq)
OR (NOT ram/RefUrg AND ram/RAMEN AND ram/BACTr)
OR (NOT ram/RefUrg AND ram/RAMEN AND NOT ram/RefReq)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND ram/RAMEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND

18
cpld/XC95144XL/WarpSE.syr
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@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
Total CPU time to Xst completion: 0.09 secs
--> Reading design: WarpSE.prj
@ -468,17 +468,17 @@ Design Statistics
# IOs : 75
Cell Usage :
# BELS : 580
# AND2 : 173
# BELS : 578
# AND2 : 172
# AND3 : 27
# AND4 : 8
# AND5 : 3
# AND6 : 2
# AND5 : 2
# AND6 : 3
# AND8 : 3
# GND : 7
# INV : 234
# OR2 : 97
# OR3 : 6
# OR2 : 95
# OR3 : 7
# VCC : 1
# XOR2 : 19
# FlipFlops/Latches : 90
@ -493,7 +493,7 @@ Cell Usage :
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.16 secs
Total CPU time to Xst completion: 5.01 secs
-->

5830
cpld/XC95144XL/WarpSE.vm6
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File diff suppressed because it is too large Load Diff

2
cpld/XC95144XL/WarpSE.xml
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12
cpld/XC95144XL/WarpSE_html/fit/ascii.htm
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@ -3,7 +3,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: WarpSE Date: 4- 1-2023, 7:57AM
Design Name: WarpSE Date: 4- 1-2023, 8:21AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
@ -1438,15 +1438,13 @@ ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
FDCPE_ram/RAMEN: FDCPE port map (ram/RAMEN,ram/RAMEN_D,FCLK,'0','0');
ram/RAMEN_D <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN)
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND ram/RAMEN)
OR (nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND NOT ram/RefUrg)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RAMEN)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
ram/BACTr)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
NOT ram/RefReq)
OR (NOT ram/RefUrg AND ram/RAMEN AND ram/BACTr)
OR (NOT ram/RefUrg AND ram/RAMEN AND NOT ram/RefReq)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND ram/RAMEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND

10
cpld/XC95144XL/WarpSE_html/fit/defeqns.htm
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@ -733,15 +733,13 @@ FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,FCLK,'0','0');
FDCPE_ram/RAMEN: FDCPE port map (ram/RAMEN,ram/RAMEN_D,FCLK,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ram/RAMEN_D <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND ram/RAMEN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ram/RS_FSM_FFd3 AND NOT ram/RefUrg)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RAMEN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ram/BACTr)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT ram/RefReq)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT ram/RefUrg AND ram/RAMEN AND ram/BACTr)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT ram/RefUrg AND ram/RAMEN AND NOT ram/RefReq)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NOT ram/RS_FSM_FFd1 AND ram/RAMEN)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND

6
cpld/XC95144XL/WarpSE_html/fit/eqns.htm
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@ -854,15 +854,15 @@
pterms["FB8_2_3"]=new Array("/ramRS_FSM_FFd1_SPECSIG","ramRS_FSM_FFd3_SPECSIG","ramRAMEN_SPECSIG");
pterms["FB8_2_4"]=new Array("nAS_FSB","ramRS_FSM_FFd2_SPECSIG","ramRS_FSM_FFd1_SPECSIG","ramRS_FSM_FFd3_SPECSIG","/ramRefUrg_SPECSIG","/fsbASrf_SPECSIG");
pterms["FB8_2_4"]=new Array("ramRS_FSM_FFd2_SPECSIG","ramRS_FSM_FFd1_SPECSIG","ramRS_FSM_FFd3_SPECSIG","/ramRefUrg_SPECSIG");
pterms["FB8_2_5"]=new Array("nAS_FSB","/ramRS_FSM_FFd2_SPECSIG","/ramRS_FSM_FFd1_SPECSIG","/ramRS_FSM_FFd3_SPECSIG","/ramRefUrg_SPECSIG","/fsbASrf_SPECSIG");
pterms["FB8_3_1"]=new Array("/ramRS_FSM_FFd2_SPECSIG","ramRS_FSM_FFd1_SPECSIG","ramRAMEN_SPECSIG");
pterms["FB8_3_2"]=new Array("/ramRS_FSM_FFd1_SPECSIG","/ramRefUrg_SPECSIG","ramRAMEN_SPECSIG","ramBACTr_SPECSIG");
pterms["FB8_3_2"]=new Array("/ramRefUrg_SPECSIG","ramRAMEN_SPECSIG","ramBACTr_SPECSIG");
pterms["FB8_3_3"]=new Array("/ramRS_FSM_FFd1_SPECSIG","/ramRefUrg_SPECSIG","ramRAMEN_SPECSIG","/ramRefReq_SPECSIG");
pterms["FB8_3_3"]=new Array("/ramRefUrg_SPECSIG","ramRAMEN_SPECSIG","/ramRefReq_SPECSIG");
pterms["FB8_3_4"]=new Array("/A_FSB23_SPECSIG","/A_FSB22_SPECSIG","csnOverlay_SPECSIG","/nAS_FSB","/ramRS_FSM_FFd1_SPECSIG","ramRAMEN_SPECSIG");

2
cpld/XC95144XL/WarpSE_html/fit/summary.htm
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@ -30,7 +30,7 @@
<tr>
<td width="40%"> <b>Date</b>
</td>
<td width="60%">  4- 1-2023, 7:57AM</td>
<td width="60%">  4- 1-2023, 8:21AM</td>
</tr>
</table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
<table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">

18
cpld/XC95144XL/WarpSE_ngdbuild.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sat Apr 01 07:57:13 2023">
<application stringID="NgdBuild" timeStamp="Sat Apr 01 08:21:33 2023">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -66,32 +66,32 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="173"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="172"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="54"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="36"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="234"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="97"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="95"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="19"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="173"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="172"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="61"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="234"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="97"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="95"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="19"/>
</section>

2
cpld/XC95144XL/WarpSE_pad.csv
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@ -1,7 +1,7 @@
Release 8.1i - Fit P.20131013
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
4- 1-2023 7:57AM
4- 1-2023 8:21AM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','

1 Release 8.1i - Fit P.20131013
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 4- 1-2023 7:57AM 4- 1-2023 8:21AM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.

10
cpld/XC95144XL/WarpSE_summary.html
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@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (04/01/2023 - 07:57:39)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (04/01/2023 - 08:21:58)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpSE.xise</TD>
@ -65,9 +65,9 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Apr 1 07:57:07 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Apr 1 07:57:13 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Apr 1 07:57:30 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>5 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Apr 1 08:21:27 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Apr 1 08:21:33 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Apr 1 08:21:50 2023</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>5 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -77,5 +77,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 04/01/2023 - 08:20:15</center>
<br><center><b>Date Generated:</b> 04/01/2023 - 08:21:58</center>
</BODY></HTML>

8
cpld/XC95144XL/WarpSE_xst.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Apr 01 07:57:02 2023">
<application stringID="Xst" timeStamp="Sat Apr 01 08:21:22 2023">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -112,13 +112,13 @@
<item stringID="XST_IOS" value="75"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="580">
<item dataType="int" stringID="XST_AND2" value="173"/>
<item dataType="int" stringID="XST_BELS" value="578">
<item dataType="int" stringID="XST_AND2" value="172"/>
<item dataType="int" stringID="XST_AND3" value="27"/>
<item dataType="int" stringID="XST_AND4" value="8"/>
<item dataType="int" stringID="XST_GND" value="7"/>
<item dataType="int" stringID="XST_INV" value="234"/>
<item dataType="int" stringID="XST_OR2" value="97"/>
<item dataType="int" stringID="XST_OR2" value="95"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XOR2" value="19"/>
</item>

2
cpld/XC95144XL/_ngo/netlist.lst
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@ -1,2 +1,2 @@
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1680350227
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1680351687
OK

3
cpld/XC95144XL/_xmsgs/pn_parser.xmsgs
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@ -11,8 +11,5 @@
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/CS.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/RAM.v&quot; into library work</arg>
</msg>
</messages>

2
cpld/XC95144XL/webtalk_pn.xml
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@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Apr 01 07:57:01 2023">
<application name="pn" timeStamp="Sat Apr 01 08:21:22 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="17F4E7DEC0A14EDB82C58FCA99308E56" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>

BIN
cpld/XC95144XL/xlnx_auto_0_xdb/cst.xbcd
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14
cpld/XC95144XL/xst/work/hdllib.ref
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@ -1,7 +1,7 @@
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1680350223
MO CS NULL ../CS.v vlg22/_c_s.bin 1680350223
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1680350223
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1680350223
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1680350223
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1680350223
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1680350223
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1680351683
MO CS NULL ../CS.v vlg22/_c_s.bin 1680351683
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1680351683
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1680351683
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1680351683
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1680351683
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1680351683

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cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin
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cpld/XC95144XL/xst/work/vlg22/_c_s.bin
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cpld/XC95144XL/xst/work/vlg37/_f_s_b.bin
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cpld/XC95144XL/xst/work/vlg52/_warp_s_e.bin
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cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin
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cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin
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cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin
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