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Fix RAM.v to compile
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@ -12,7 +12,7 @@ module RAM(
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input RefReqIn, input RefUrgIn,
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input RefReqIn, input RefUrgIn,
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/* DRAM and NOR flash interface */
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output reg nOE, output nROMOE, output nROMWE);
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output nLWE, output nUWE, output nOE, output nROMOE, output nROMWE);
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/* RAM control state */
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/* RAM control state */
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reg [2:0] RS;
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reg [2:0] RS;
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