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Update index.html
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Zane Kaminski
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af4c5c2da1
commit
7b6f6f676f
@ -643,7 +643,7 @@ delay completion of the /AS cycle via their respective Ready signals.
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{name: 'RW', wave: 'x..1...|......x...', phase:0.25, period: 1},
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{name: 'AS', wave: '1...x0.......|............x1....x..', phase:-0.25, period: 0.5},
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{name: 'BACT', wave: '0...x.1......|................0.x.1', phase:-0.25, period: 0.5},
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{name: '/DTACK', wave: '21.|0...1', phase:-0.3, period: 2},
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{name: '/DTACK', wave: '21.|.0..1', phase:-0.3, period: 2},
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{name: 'D (RD)', wave: 'z.x....|.2....z...', phase:0.00},
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{name: 'Ready1', wave: 'x0.|1....', phase:-0.2, period: 2},
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]}
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@ -666,8 +666,8 @@ The IOB slave port holds Ready1 low until the I/O bus transaction is completed.
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{name: 'ALEEN0', wave: '1..0|.1|...', phase:-0.3, period: 2},
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{name: 'IORW0', wave: '2.2.|..|...', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: '2..2|..|...', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'Ready1 (RD)', wave: '0...|..|.10', phase:-0.3, period: 2},
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{name: 'Ready1 (WR)', wave: '1...|..|...', phase:-0.3, period: 2},
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{name: 'IORDReady', wave: '0...|..|.1.', phase:-0.3, period: 2},
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{name: 'IOWRReady', wave: '1...|..|...', phase:-0.3, period: 2},
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]}
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</script><br/><p>
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This diagram shows the behavior of the I/O bus slave port controller under a single read/write request.
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@ -699,7 +699,7 @@ Once IOACT is received high then the IOB slave controller removes IOREQ and ADLE
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In PS1, the IO bus controller waits for IOACT low, indicating that the cycle has completed, and then returns to PS0.
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Additionally, once IOACT is low, if IORW0 indicates a read was performed, IORDRDY is brought high for one cycle.
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</p><p>
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The actual Ready1 output signal is a combination of IORDRDY and IOWRRDY selects the corect one depending on the
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The actual Ready1 output signal is a combination of IORDRDY and IOWRRDY which selects the corect one depending on the
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address range accessed.
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</p>
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@ -709,12 +709,13 @@ address range accessed.
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{signal: [
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{name: 'MCLK', wave: 'p..|..|....|..|..', period: 2},
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{name: 'IOSTART', wave: '10.|..|.10.|..|..', period: 2, phase:-0.3},
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{name: 'PS', wave: '222|22|2222|22|22', period: 2, data:[0,2,2,2,1,1,0,2,2,2,1,1,0], phase:-0.3},
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{name: 'PS', wave: '222|22|2222|22|22', period: 2, data:[0,3,2,2,1,1,0,3,2,2,1,1,0], phase:-0.3},
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{name: 'IOACT', wave: '0..|1.|0...|1.|0.', phase:-0.3, period: 2},
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{name: 'IOREQ', wave: '01.|.0|..1.|.0|..', phase:-0.3, period: 2},
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{name: 'ALE0', wave: '1.0|.1|...0|.1|..', phase:-0.3, period: 2},
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{name: 'IORW0', wave: '20.|..|..0.|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: '2.2|..|...2|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IOWRReady', wave: '1..|..|....|..|..', phase:-0.3, period: 2},
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]}
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</script><br/><p>
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This diagram shows two posted writes.
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@ -726,72 +727,82 @@ In this case, the posted writes are spaced out such that the FIFO is never fully
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{signal: [
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{name: 'MCLK', wave: 'p..|..|.....|..|..', period: 2},
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{name: 'IOSTART', wave: '10.|..|10...|..|..', period: 2, phase:-0.3},
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{name: 'IORDY', wave: '101|..|.0..1|..|..', phase:-0.3, period: 2},
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{name: 'PS', wave: '222|22|22222|22|22', period: 2, data:[0,2,2,2,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
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{name: 'PS', wave: '222|22|22222|22|22', period: 2, data:[0,3,2,2,1,1,0,3,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOACT', wave: '0..|1.|0....|1.|0.', phase:-0.3, period: 2},
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{name: 'IOREQ', wave: '01.|.0|.1...|.0|..', phase:-0.3, period: 2},
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{name: 'ALE1', wave: '1..|..|.0..1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: 'x..|..|.0...|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: 'x..|..|..2..|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE1', wave: '1..|..|..0.1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: '2..|..|.0...|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: '2..|..|..2..|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE0', wave: '1.0|.1|...0.|.1|..', phase:-0.3, period: 2},
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{name: 'IORW0', wave: '20.|..|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: '2.2|..|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IOWRReady', wave: '1..|..|.0..1|..|..', phase:-0.3, period: 2},
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]}
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</script>
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</script><br/><p>
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Here we have the case where two posted writes occur close enough in time that the FIFO is fully utilized.
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</p>
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<h3>24. I/O Bus Slave Port - Two Writes, FIFO filled (1)</h3>
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<script type="WaveDrom">
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{signal: [
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{name: 'MCLK', wave: 'p..|....|.....|..|..', period: 2},
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{name: 'AS&IO', wave: '01.|.01.|.....|..|..', period: 2, phase:-0.3},
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{name: 'IORDY', wave: '101|..0.|....1|..|..', phase:-0.3, period: 2},
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{name: 'PS', wave: '222|2222|22222|22|22', period: 2, data:[0,2,2,2,1,1,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOSTART', wave: '10.|.10.|.....|..|..', period: 2, phase:-0.3},
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{name: 'PS', wave: '222|2222|22222|22|22', period: 2, data:[0,3,2,2,1,1,1,1,0,3,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOACT', wave: '0..|1...|0....|1.|0.', phase:-0.3, period: 2},
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{name: 'IOREQ', wave: '01.|.01.|.....|.0|..', phase:-0.3, period: 2},
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{name: 'ALE1', wave: '1..|..0.|....1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: 'x..|..0.|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: 'x..|...2|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE1', wave: '1..|...0|....1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: '2..|..0.|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: '2..|...2|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE0', wave: '1.0|.1..|...0.|.1|..', phase:-0.3, period: 2},
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{name: 'IORW0', wave: 'x0.|....|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: 'x.2|....|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IORW0', wave: '20.|....|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: '2.2|....|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IOWRReady', wave: '1..|..0.|....1|..|..', phase:-0.3, period: 2},
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]}
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</script>
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</script><br/><p>
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Similar to the previous case but the writes are even closer in time.
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</p>
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<h3>25. I/O Bus Slave Port - Two Writes, FIFO filled (2)</h3>
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<script type="WaveDrom">
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{signal: [
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{name: 'MCLK', wave: 'p..|....|.....|..|..', period: 2},
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{name: 'AS&IO', wave: '01.|01..|.....|..|..', period: 2, phase:-0.3},
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{name: 'IORDY', wave: '101|.0..|....1|..|..', phase:-0.3, period: 2},
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{name: 'PS', wave: '222|2222|22222|22|22', period: 2, data:[0,2,2,2,1,1,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOSTART', wave: '10.|10..|.....|..|..', period: 2, phase:-0.3},
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{name: 'PS', wave: '222|2222|22222|22|22', period: 2, data:[0,3,2,2,1,1,1,1,0,3,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOACT', wave: '0..|1...|0....|1.|0.', phase:-0.3, period: 2},
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{name: 'IOREQ', wave: '01.|....|.....|.0|..', phase:-0.3, period: 2},
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{name: 'ALE1', wave: '1..|.0..|....1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: 'x..|.0..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: 'x..|..2.|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE1', wave: '1..|..0.|....1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: '2..|.0..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: '2..|..2.|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE0', wave: '1.0|.1..|...0.|.1|..', phase:-0.3, period: 2},
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{name: 'IORW0', wave: 'x0.|....|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: 'x.2|....|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IORW0', wave: '20.|....|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: '2.2|....|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IOWRReady', wave: '1..|.0..|....1|..|..', phase:-0.3, period: 2},
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]}
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</script>
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</script><p>
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Similar to the previous case (again) but here the second write has come in before
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the IOBS has received indication from the IOBM that the previous write has begun.
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</p>
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<h3>26. I/O Bus Slave Port - Two Writes, FIFO filled (3)</h3>
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<script type="WaveDrom">
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{signal: [
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{name: 'MCLK', wave: 'p....|..|.....|..|..', period: 2},
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{name: 'AS&IO', wave: '0101.|0.|.....|..|..', period: 2, phase:-0.3},
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{name: 'IORDY', wave: '1.10.|..|....1|..|..', phase:-0.3, period: 2},
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{name: 'PS', wave: '22222|22|22222|22|22', period: 2, data:[0,2,2,2,2,2,1,1,0,2,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOSTART', wave: '1010.|..|.....|..|..', period: 2, phase:-0.3},
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{name: 'PS', wave: '22222|22|22222|22|22', period: 2, data:[0,3,2,2,2,2,1,1,0,3,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOACT', wave: '0....|1.|0....|1.|0.', phase:-0.3, period: 2},
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{name: 'IOREQ', wave: '01...|..|.....|.0|..', phase:-0.3, period: 2},
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{name: 'ALE1', wave: '1..0.|..|....1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: 'x..0.|..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: 'x...2|..|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE1', wave: '1...0|..|....1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: '2..0.|..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: '2...2|..|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE0', wave: '1.0..|.1|...0.|.1|..', phase:-0.3, period: 2},
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{name: 'IORW0', wave: 'x0...|..|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: 'x.2..|..|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IORW0', wave: '20...|..|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: '2.2..|..|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IOWRReady', wave: '1...0|..|....1|..|..', phase:-0.3, period: 2},
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]}
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</script>
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</script><p>
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Similar to the previous case (again). This is the closest write timing allowed, even faster than MC68k can do.
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</p>
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</body>
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