From 8631b521045da7144d8d53c460aed76db8fe00ae Mon Sep 17 00:00:00 2001
From: Zane Kaminski
Date: Mon, 6 Nov 2023 19:49:37 -0500
Subject: [PATCH] final version?
---
Clk.kicad_sch | 5 +-
ClkBuf.kicad_sch | 124 +-
Documentation/index.html | 363 +-
Power.kicad_sch | 432 +-
Prog.kicad_sch | 965 +-
WarpSE.kicad_pcb | 138131 ++++++++++++++++++++++++++++++++++--
WarpSE.kicad_pro | 53 +-
fp-lib-table | 3 +-
8 files changed, 133359 insertions(+), 6717 deletions(-)
diff --git a/Clk.kicad_sch b/Clk.kicad_sch
index 07cdb85..a60c833 100644
--- a/Clk.kicad_sch
+++ b/Clk.kicad_sch
@@ -760,7 +760,7 @@
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(effects (font (size 1.27 1.27)) (justify right))
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(effects (font (size 1.27 1.27)) (justify right))
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(property "Footprint" "stdpads:R_0603" (at 180.34 83.82 0)
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(pin "1" (uuid 5bbb8993-4e6a-4e14-a5ee-022b9c51492e))
(pin "2" (uuid e5a1d3af-4f0b-4d33-8d30-bf829f96aed1))
(instances
diff --git a/ClkBuf.kicad_sch b/ClkBuf.kicad_sch
index 7ca21df..94efc78 100644
--- a/ClkBuf.kicad_sch
+++ b/ClkBuf.kicad_sch
@@ -231,32 +231,32 @@
)
)
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(uuid 131caff9-fc69-41eb-81d9-de7b3376f4e3)
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(uuid 20d398fe-73aa-43d3-8ca2-985ab624712c)
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(uuid 162509bc-62f6-43aa-9778-dcb0500e3a76)
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(effects (font (size 1.27 1.27)) (justify left))
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(pin "1" (uuid 35235e5c-be54-4016-b691-b1c31abd106c))
@@ -410,19 +410,19 @@
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(uuid 57ccc073-6454-4be7-b99e-2e52a3079b38)
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(effects (font (size 1.27 1.27)) hide)
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- (property "Footprint" "stdpads:C_0603" (at 133.35 138.43 0)
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(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 640c16e5-872a-44be-bd5c-44a0677fc6de))
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(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 94d51cc1-7d13-4b87-b5e5-37484853de53))
@@ -555,22 +555,22 @@
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(uuid 80948367-5a1c-4ed0-a3b4-d5c216f5fabd)
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(effects (font (size 1.27 1.27)) (justify left))
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(effects (font (size 1.27 1.27)) (justify left))
)
- (property "Footprint" "stdpads:C_0603" (at 123.19 138.43 0)
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(effects (font (size 1.27 1.27)) hide)
)
- (property "Datasheet" "~" (at 123.19 138.43 0)
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(effects (font (size 1.27 1.27)) hide)
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- (property "LCSC Part" "C23630" (at 123.19 138.43 0)
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(pin "1" (uuid 2c5ccc0d-1783-4464-b314-c36abdd87d91))
@@ -587,19 +587,19 @@
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(uuid 84038a3a-ec03-4561-af51-4c2bf6577707)
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(effects (font (size 1.27 1.27)))
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(effects (font (size 1.27 1.27)) (justify top) hide)
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(pin "1" (uuid e4abcf12-5a81-4dc4-be2f-e287cdbf6fd0))
@@ -698,19 +698,19 @@
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(uuid 9ae89df8-7591-49aa-9807-698d82c3cde2)
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(effects (font (size 1.27 1.27)) hide)
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(uuid af63e236-063d-4e9a-91c6-e1aaeb08194d)
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(effects (font (size 1.27 1.27)) (justify bottom))
)
- (property "Footprint" "stdpads:R_0603" (at 146.05 121.92 0)
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(effects (font (size 1.27 1.27)) hide)
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diff --git a/Documentation/index.html b/Documentation/index.html
index 27e4d3a..32e4f55 100644
--- a/Documentation/index.html
+++ b/Documentation/index.html
@@ -182,30 +182,23 @@ The Ready signals are always high during ROM access so all ROM accesses complete
5. Back-to-Back RAM Access
+{name: 'CAS', wave: '1..0.1.0.1', phase: 0.80, period: 2},
+]}
This diagram introduces the DRAM access timing.
At 25 MHz for a 4-clock read cycle, there are only 2.5 clock cycles (100 ns) between
@@ -221,149 +214,112 @@ which outputs row addresses to the DRAM array when RASEL is low and column addre
The /CAS signal is a function of RASEL. RASEL changes after FCLK rises. If RASEL is high at the next falling edge, /CAS is asserted.
Otherwise if RASEL is low, /CAS is deasserted at the next falling edge.
+"RS" is the RAM state. The RS state changes after the rising edge of the clock
+and can take on values 0-7.
+In RS0, the RAM is considered to be idle.
+At the rising edge of the clock in RS0 a RAM cycle begins if, if /AS is asserted,
+a RAM address is present, and a RAM cycle has not already occurred for this /AS cycle.
+In this case, we know that /RAS has been active for at least 10 nanoseconds, so RASEL is brogught high.
+This switches the RA bus from row to column addresses and RS0 transitions to RS5.
+At the falling edge in the middle of RS5, /CAS is brought low. RS5 always transitions to RS6.
+At the end of RS6, RASEL is brought low again, switching the RA multiplexers back to row addresses
+in preparation for the next DRAM access cycle. RS6 always transitions to RS7.
+RS7 is the state in which a RAM access or refresh is concluded. At the falling edge in the middle of RS7, /CAS is brought high.
+RS7 transitions to RS2 if a refresh request is pending, otherwise RS7 transitions to RS0.
+The states RS1 and RS2-RS4 will be discussed in association with the subsequent refresh cycle diagrams.
+The RS and RAMCS signals are used to generate the Ready0 ready signal input to the FSB.
+Ready0 is high if and only if RS==0 and RAMCS is active.
+
+Also notice how, during write cycles,
+it is undefined whether the cycle is conducted as an "early write" or an "OE-controlled write" cycle.
+/OE is held high at all times during write cycles,
+but /LWE and /UWE are asynchronous functions of MC68k's /LDS and /UDS signals.
+It is undefined during a write cycle whether /LWE and /UWE will go low before or after /CAS falls.
+Since /OE is held high during write cycles, the order of the /WE signals and /CAS is of no consequence.
6. Long-running RAM Access
-This diagram shows the timing for a long-running RAM access, in which the RAM read or write completes sooner than MC68k removes /AS.
+This diagram shows the timing for a long-running RAM access,
+in which the RAM read or write completes sooner than MC68k removes /AS.
+There are cases in which a DRAM access completes in time for termination of a 4-clock bus cycle,
+but the bus cycle is lengthened because not all of the Ready signals to the FSB controller have gone high.
+If RS0 is returned to after a DRAM access but /AS remains asserted,
+then the DRAM must not enter RS5-7 and thus not initiate any additional /CAS cycles.
+Notice how /CAS goes high in the middle of RS7 but /RAS stays low until the end of the /AS cycle.
+Using EDO DRAM allows the data bus output to be maintained while /RAS is low.
+However, if FPM DRAM is used or if a refresh cycle occurs before /AS rises,
+then maintenance of read data on the data bus falls to the bus capacitance and the bus hold resistors.
+Therefore it is best not to prolong DRAM read cycles, even when using EDO DRAM, so that there is no possibility of
+an intervening DRAM refresh cycle causing the data outputs to tristate.
+Fortunately, although DRAM write cycles shadowed to main sound and video memory need to be extended
+when the posted write FIFO is full, there is no need to extend DRAM read cycles.
+Therefore we do not attempt to extend the /CAS pulse to fix this problem until /AS rises since the /CAS pulse
+could be interrupted by a refresh cycle anyway.
+To fix this problem, we could extend the /CAS pulse until /AS is high and have the
+DRAM controller conform to the DRAM "hidden refresh" protocol but it is not necessary.
7. Refresh During Idle
This diagram shows the timing of a refresh occurring after the bus and DRAM are and have been idle for at least one clock cycle.
-
+
+RAM states RS2, RS3, RS4, and RS7 are used for refresh.
+RS2-RS4 implement the main refresh behavior.
+When a refresh request is pending at the rising edge ending RS0 or RS7 while /RAS is inactive,
+RASEN is brought low and RS2 is entered.
+With RASEN low, /AS activity does not cause a /RAS pulse and the DRAM controller uses the registered /RRAS signal
+to initiate refresh cycles.
+At the falling edge in the middle of RS2, /CAS is activated. Then at the rising edge concluding RS2, /RAS is activated
+and RS2 transitions to RS3.
+In RS3, /RAS and /CAS remain active, and RS3 transitions to RS4.
+RS3 and RS4 serve to implement the requisite /RAS pulse width for a refresh.
+At the falling edge in the middle of RS4, /CAS is deactivated. Then at the rising edge concluding RS4, /RAS is deactivated
+and RS4 transitions to RS7.
+RREQ is cleared after the first rising edge on which RefRAS is active.
+In RS7, /RAS and /CAS remain inactive. RS7 serves to implement the requisite RAS precharge time between DRAM cycles.
+RASEN is brought high again after the rising edge concluding RS7 and RS7 transitions to RS0 and the DRAM is considered idle again.
+
+Also notice how a RASEN can only be disabled if /RAS is high or if a DRAM cycle is complete, otherwise
+there may be a tRAS timing violation. This constrains the timing of a refresh.
-8A. Refresh Immediately Following DRAM Access - Idle afterwards
+8. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately
-
-
-8B. Refresh Immediately Following DRAM Access - RAM access immediately afterwards
-
-
-
-9. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately
-
-
-
-10. Refresh Immediately Following DRAM Access - Bus Transaction Terminated Immediately
-
This diagram shows the timing of a refresh occurring immediately after a RAM access cycle.
@@ -379,6 +335,113 @@ The purpose of this diagram is mainly to demonstrate that adequate /RAS and /CAS
after the previous DRAM access is terminated before /RAS is pulsed for refresh.
+
+9. Refresh Immediately Following DRAM Access - Bus Transaction Terminated While Refresh In-Progress
+
+This diagram shows the case where a refresh request occurs during a long-running DRAM access
+and the /AS cycle terminates before the refresh ends.
+
+It is possible for a DRAM access cycle to be extended for a long time, during which the DRAM may be deprived of refresh.
+Therefore we must provide for the case where a DRAM access completes and a refresh begins but before /AS ever goes high.
+In this case, the rising edge of RASEN causes /RAS to go inactive, as opposed to the rising edge of /AS.
+Therefore, the /RAS precharge pulse width in this case is much shorter than
+a refresh occurring during idle or immediately following a DRAM access.
+At 25 MHz, the /RAS precharge width is only 40ns. This is the minimum tRP for 60ns DRAM and is the tightest timing parameter in the Warp-SE.
+We could purpose RS1 to add additional precharge time if necessary.
+
+
+
+10. Refresh Immediately Following DRAM Access - Bus Transaction Terminated After Refresh Completes
+
+This diagram shows the case where a refresh request occurs during a long-running DRAM access
+and the /AS cycle does not terminate before the refresh ends.
+
+This case is similar to the previous but there is a key difference.
+/AS does not rise until after the refresh cycle completes.
+Therefore if RASEN were brought high upon exit from RS7 into RS0, there may be an improperly-short /RAS pulse
+terminated by the rising edge of the /AS.
+Consequently RASEN enablement is held off the first rising edge during which BACT is low.
+
+
+11. Refresh in the "Middle" of DRAM Access
+
+This diagram shows the case where a refresh request occurs in the "middle" of a long-running DRAM access.
+The remainder of the timing is given by diagrams 9 or 10.
+
+
+12. Concurrent DRAM Access and Refresh Requests
+
+This diagram shows the timing of a refresh starting concurrently with the beginning of a RAM access cycle.
+
+Here we see the timing of refresh being entered concurrently with the start of a RAM access.
+In this case, there is a little bit of a race condition.
+RASEN and /AS both fall following the rising edge of FCLK. /AS causes /RAS activation asynchronously,
+but RASEN gates this from occurring.
+Therefore the internal RASEN feedback in the CPLD must occur sooner than /AS transitions,
+otherwise an erroneous /RAS pulse will be generated.
+Fortunately the CPLDs intended to be used (ispMACH4000, XC9500XL) are some 10 years newer than MC68HC000,
+so their speed advantage mitigates the problem.
+The negation of Ready0 causes /DTACK generation and termination of the bus cycle
+to be delayed until completion of the refresh.
+
+
+
+Before showing the timing for the I/O bus slave port on the FSB,
+it's instructive to understand the timing of the I/O bus master controller.
+
+
+
13. I/O Bus E State, VMA, "ETACK"