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https://github.com/garrettsworkshop/Warp-SE.git
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PDS bridge refactor
This commit is contained in:
Zane Kaminski
parent
d557f9e502
commit
8767a92544
66
cpld/IOBM.v
66
cpld/IOBM.v
@ -1,21 +1,19 @@
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module IOBM(
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/* PDS interface */
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input C16M, input C8M, input E,
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output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
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output reg nAS, output reg RnW, output reg nLDS, output reg nUDS, output reg nVMA,
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input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
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/* IO bus slave port interface */
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input IORDREQ, input IOWRREQ, input IOLDS, input IOUDS,
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input IOREQ, input IORW, input IOLDS, input IOUDS,
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output reg IOACT, output reg IODONE, output reg IOBERR);
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/* C8M clock registration */
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reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
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/* I/O request input synchronization */
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reg IORDREQr; always @(posedge C16M) IORDREQr <= IORDREQ;
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reg IOWRREQr; always @(posedge C16M) IOWRREQr <= IOWRREQ;
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wire IOREQr = IORDREQr || IOWRREQr;
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reg IOREQr; always @(posedge C16M) IOREQr <= IOREQ;
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/* VPA synchronization */
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reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
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@ -39,8 +37,8 @@ module IOBM(
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end
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/* DTACK and BERR synchronization */
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always @(negedge C8M, posedge nASout) begin
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if (nASout) begin
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always @(negedge C8M, posedge nAS) begin
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if (nAS) begin
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IODONE <= 0;
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IOBERR <= 0;
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end else begin
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@ -52,8 +50,8 @@ module IOBM(
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/* I/O bus state */
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reg [2:0] IOS = 0;
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reg IOS0;
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always @(posedge C16M) begin
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if (IOS==0) begin
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always @(posedge C16M) case (IOS[2:0])
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3'h0: begin
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if (IOREQr && !C8Mr && AoutOE) begin // "IOS1"
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IOS <= 2;
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IOS0 <= 0;
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@ -61,24 +59,24 @@ module IOBM(
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IOS <= 0;
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IOS0 <= 1;
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end
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IOACT <= IOREQr && AoutOE;
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ALE0 <= IOREQr && AoutOE;
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end else if (IOS==2) begin
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IOACT <= IOREQr;
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ALE0 <= IOREQr;
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end 3'h2: begin
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IOS <= 3;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==3) begin
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end 3'h3: begin
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IOS <= 4;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==4) begin
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end 3'h4: begin
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IOS <= 5;
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IOS0 <= 0;
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IOACT <= 1;
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ALE0 <= 1;
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end else if (IOS==5) begin
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end 3'h5: begin
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if (!C8Mr && (IODONE || IOBERR)) begin
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IOS <= 6;
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IOACT <= 0;
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@ -88,33 +86,55 @@ module IOBM(
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end
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IOS0 <= 0;
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ALE0 <= 1;
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end else if (IOS==6) begin
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end 3'h6: begin
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IOS <= 7;
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IOS0 <= 0;
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IOACT <= 0;
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ALE0 <= 0;
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end else if (IOS==7) begin
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end 3'h7: begin
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IOS <= 0;
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IOS0 <= 1;
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IOACT <= 0;
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ALE0 <= 0;
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end
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end
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endcase
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/* PDS address and data latch control */
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always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
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reg DoutOE = 0;
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always @(posedge C16M) begin
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DoutOE <= (IOS==0 && IOWRREQr && !C8Mr) ||
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DoutOE <= (IOS==0 && IOREQr && !IORW && !C8Mr) ||
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(DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
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end
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assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
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/* AS, DS control */
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/* AS, DS, RW control */
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always @(negedge C16M) begin
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nASout <= !((IOS==0 && IOREQr && !C8Mr) || IOS==2 || IOS==3 || IOS==4 || IOS==5);
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nLDS <= !(IOLDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nLDS) || IOS==3 || IOS==4 || IOS==5));
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nUDS <= !(IOUDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nUDS) || IOS==3 || IOS==4 || IOS==5));
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nAS <= !(
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(IOS==0 && IOREQr && !C8Mr) ||
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(IOS==2) ||
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(IOS==3) ||
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(IOS==4) ||
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(IOS==5));
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RnW <= !(
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(IOS==0 && IOREQr && !IORW && !C8Mr) ||
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(!IORW && IOS==2) ||
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(!IORW && IOS==3) ||
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(!IORW && IOS==4) ||
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(!IORW && IOS==5) ||
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(!IORW && IOS==6));
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nLDS <= !(
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(IOS==0 && IOREQr && IORW && IOLDS && !C8Mr) ||
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(IOS==2 && IOLDS) ||
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(IOS==3 && IOLDS) ||
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(IOS==4 && IOLDS) ||
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(IOS==5 && IOLDS));
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nUDS <= !(
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(IOS==0 && IOREQr && IORW && IOUDS && !C8Mr) ||
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(IOS==2 && IOUDS) ||
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(IOS==3 && IOUDS) ||
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(IOS==4 && IOUDS) ||
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(IOS==5 && IOUDS));
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end
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endmodule
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49
cpld/IOBS.v
49
cpld/IOBS.v
@ -10,7 +10,7 @@ module IOBS(
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/* Read data OE control */
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output nDinOE,
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/* IOB master controller interface */
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output reg IORDREQ, output reg IOWRREQ,
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output reg IOREQ, output reg IORW,
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input IOACT, input IODONEin, input IOBERR,
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/* FIFO primary level control */
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output reg ALE0, output reg IOL0, output reg IOU0,
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@ -70,30 +70,32 @@ module IOBS(
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/* FIFO primary level control */
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always @(posedge CLK) begin
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if (TS==0) begin
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if (ALE1) begin // If FIFO secondary level occupied
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// Request transfer from IOBM and latch R/W from FIFO
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// Start IOREQ if FIFO secondary level occupied or FSB request
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if (ALE1 || (BACT && IOCS && !ALE1 && !Sent)) begin
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// Request transfer from IOBM
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TS <= 3;
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IORDREQ <= IORW1;
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IOWRREQ <= !IORW1;
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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end else if (BACT && IOCS && !ALE1 && !Sent) begin // FSB request
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// Request transfer from IOBM and latch R/W from FSB
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TS <= 3;
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IORDREQ <= nWE;
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IOWRREQ <= !nWE;
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IOL0 <= !nLDS;
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IOU0 <= !nUDS;
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IOREQ <= 1;
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end else begin // Otherwise stay in idle
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TS <= 0;
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IORDREQ <= 0;
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IOWRREQ <= 0;
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IOREQ <= 0;
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end
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// Latch R/W and data strobes from FIFO secondary or FSB
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if (ALE1) begin // If FIFO secondary level occupied
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IORW <= IORW1;
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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end else begin // FSB request
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IORW <= nWE;
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IOL0 <= !nLDS;
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IOU0 <= !nUDS;
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end
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ALE0 <= 0;
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end else if (TS==3) begin
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TS <= 2; // Always go to TS2. Keep IORDREQ/IOWRREQ active
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TS <= 2; // Always go to TS2
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IOREQ <= 1; // Keep IOREQ active
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ALE0 <= 1; // Latch address (and data)
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// Latch data strobes from FIFO or FSB as appropriate
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// Latch data strobes again from FIFO or FSB as appropriate
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if (ALE1) begin
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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@ -105,16 +107,17 @@ module IOBS(
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// Wait for IOACT then withdraw IOREQ and enter TS1
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if (IOACTr) begin
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TS <= 1;
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IORDREQ <= 0;
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IOWRREQ <= 0;
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end else TS <= 2;
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IOREQ <= 0;
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end else begin
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TS <= 2;
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IOREQ <= 1;
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end
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ALE0 <= 1; // Keep address latched
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end else if (TS==1) begin
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// Wait for IOACT low (transfer over) before going back to idle
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if (!IOACTr) TS <= 0;
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else TS <= 1;
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IORDREQ <= 0;
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IOWRREQ <= 0;
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IOREQ <= 0;
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ALE0 <= 0; // Release addr latch since it's controlled by IOBM now
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end
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end
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@ -126,7 +126,7 @@ module WarpSE(
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.nROMWE(nROMWE));
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wire IONPReady, IOPWReady;
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wire IORDREQ, IOWRREQ;
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wire IOREQ, IORW;
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wire IOL0, IOU0;
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wire ALE0S, ALE0M, ALE1;
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assign nADoutLE0 = ~(ALE0S || ALE0M);
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@ -152,8 +152,8 @@ module WarpSE(
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/* Read data OE control */
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.nDinOE(nDinOE),
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/* IOB Master Controller Interface */
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.IORDREQ(IORDREQ),
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.IOWRREQ(IOWRREQ),
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.IOREQ(IOREQ),
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.IORW(IORW),
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.IOACT(IOACT),
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.IODONEin(IODONE),
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.IOBERR(IOBERR),
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@ -166,8 +166,9 @@ module WarpSE(
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wire AoutOE;
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assign nAoutOE = !AoutOE;
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wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
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wire nAS_IOBout, RnW_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
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assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
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assign RnW_IOB = AoutOE ? RnW_IOBout : 1'bZ;
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assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
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assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
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assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
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@ -176,7 +177,8 @@ module WarpSE(
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.C16M(C16M),
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.C8M(C8M),
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.E(E),
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.nASout(nAS_IOBout),
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.nAS(nAS_IOBout),
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.RnW(RnW_IOBout),
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.nLDS(nLDS_IOBout),
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.nUDS(nUDS_IOBout),
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.nVMA(nVMA_IOBout),
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@ -190,8 +192,8 @@ module WarpSE(
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.ALE0(ALE0M),
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.nDinLE(nDinLE),
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/* IO bus slave port interface */
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.IORDREQ(IORDREQ),
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.IOWRREQ(IOWRREQ),
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.IOREQ(IOREQ),
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.IORW(IORW),
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.IOLDS(IOL0),
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.IOUDS(IOU0),
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.IOACT(IOACT),
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