From 8e273169a099e10d95bcf88bbac7463599e43eb0 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sun, 9 Apr 2023 23:26:32 -0400 Subject: [PATCH] Revert "Put back full RAM refresh conditions" This reverts commit adb25788215384c46a7916dda93912e9f234fa1a. --- cpld/RAM.v | 10 ++++------ cpld/WarpSE.v | 2 +- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/cpld/RAM.v b/cpld/RAM.v index bf9bb51..684468c 100644 --- a/cpld/RAM.v +++ b/cpld/RAM.v @@ -4,7 +4,7 @@ module RAM( /* AS cycle detection */ input BACT, /* Select and ready signals */ - input RAMCS, input RAMCS0X, input ROMCS, output reg RAMReady, + input RAMCS, input ROMCS, output reg RAMReady, /* Refresh Counter Interface */ input RefReqIn, input RefUrgIn, /* DRAM and NOR flash interface */ @@ -16,8 +16,8 @@ module RAM( /* RAM control state */ reg [2:0] RS = 0; - reg Once = 0; reg RAMEN = 0; + reg Once = 0; reg RASEL = 0; reg CAS = 0; reg RASrr = 0; @@ -59,10 +59,8 @@ module RAM( assign RA[01] = !RASEL ? A[10] : A[02]; assign RA[00] = !RASEL ? A[09] : A[01]; - wire RefFromRS0 = ((RefReq && BACT && !BACTr && !RAMCS0X) || - (RefUrg && !BACT) || - (RefUrg && BACT && !RAMCS0X) || - (RefUrg && BACT && !RAMEN && !nWE)); + wire RefFromRS0 = ((RefReq && !BACT) || + (RefUrg && !BACT)); wire RefFromRS2 = RefUrg; wire RAMStart = BACT && RAMCS && RAMEN; always @(posedge CLK) begin diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v index 18d06c0..a680484 100644 --- a/cpld/WarpSE.v +++ b/cpld/WarpSE.v @@ -75,7 +75,7 @@ module WarpSE( /* AS cycle detection */ BACT, /* Select and ready signals */ - RAMCS, RAMCS0X, ROMCS, RAMReady, + RAMCS, ROMCS, RAMReady, /* Refresh Counter Interface */ RefReq, RefUrg, /* DRAM and NOR flash interface */