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This commit is contained in:
Zane Kaminski 2023-04-07 06:38:37 -04:00
parent 254b4ccf22
commit 9a9838a2c2
11 changed files with 78 additions and 901 deletions
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3
cpld/CS.v
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@ -54,6 +54,7 @@ module CS(
(A[23:20]==4'h7) || // empty
(A[23:20]==4'h6) || // empty
(A[23:20]==4'h5) || // SCSI
((A[23:20]==4'h4) && Overlay); // ROM once
((A[23:20]==4'h4) && Overlay) ||
VidRAMCSWR; // ROM once
assign IOPWCS = VidRAMCSWR;
endmodule

5
cpld/RAM.v
View File

@ -147,10 +147,7 @@ module RAM(
/* RAM ready signal */
always @(posedge CLK) begin
if (RS==7) RAMReady <= 1;
if (RS==0 && !RefFromRS0) RAMReady <= 1;
if (BACT && RAMReady) RAMReady <= 1;
else RAMReady <= 0;
RAMReady <= (BACT && RAMReady) || (RS==7) || (RS==0 && !RefFromRS0);
end
endmodule

150
cpld/WarpSE-XC95144XL.ucf
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@ -1,75 +1,75 @@
NET "A_FSB<10>" LOC = "P8" ;
NET "A_FSB<11>" LOC = "P9" ;
NET "A_FSB<12>" LOC = "P10" ;
NET "A_FSB<13>" LOC = "P11" ;
NET "A_FSB<14>" LOC = "P12" ;
NET "A_FSB<15>" LOC = "P13" ;
NET "A_FSB<16>" LOC = "P14" ;
NET "A_FSB<17>" LOC = "P15" ;
NET "A_FSB<18>" LOC = "P16" ;
NET "A_FSB<19>" LOC = "P17" ;
NET "A_FSB<1>" LOC = "P94" ;
NET "A_FSB<20>" LOC = "P18" ;
NET "A_FSB<21>" LOC = "P19" ;
NET "A_FSB<22>" LOC = "P20" ;
NET "A_FSB<23>" LOC = "P24" ;
NET "A_FSB<2>" LOC = "P95" ;
NET "A_FSB<3>" LOC = "P96" ;
NET "A_FSB<4>" LOC = "P97" ;
NET "A_FSB<5>" LOC = "P2" ;
NET "A_FSB<6>" LOC = "P3" ;
NET "A_FSB<7>" LOC = "P4" ;
NET "A_FSB<8>" LOC = "P6" ;
NET "A_FSB<9>" LOC = "P7" ;
NET "C20MEN" LOC = "P59" ;
NET "C25MEN" LOC = "P58" ;
NET "FCLK" LOC = "P27" ;
NET "C16M" LOC = "P22" ;
NET "C8M" LOC = "P23" ;
NET "E" LOC = "P25" ;
NET "nADoutLE0" LOC = "P85" ;
NET "nADoutLE1" LOC = "P82" ;
NET "nAoutOE" LOC = "P87" ;
NET "nAS_FSB" LOC = "P32" ;
NET "nAS_IOB" LOC = "P81" ;
NET "nBERR_FSB" LOC = "P70" ;
NET "nBERR_IOB" LOC = "P76" ;
NET "nBG_IOB" LOC = "P73" ;
NET "nBR_IOB" LOC = "P72" ;
NET "nCAS" LOC = "P36" ;
NET "nDinLE" LOC = "P86" ;
NET "nDinOE" LOC = "P90" ;
NET "nDoutOE" LOC = "P89" ;
NET "nDTACK_FSB" LOC = "P28" ;
NET "nDTACK_IOB" LOC = "P78" ;
NET "nIPL2" LOC = "P92" ;
NET "nLDS_FSB" LOC = "P30" ;
NET "nLDS_IOB" LOC = "P79" ;
NET "nOE" LOC = "P37" ;
NET "nRAMLWE" LOC = "P65" ;
NET "nRAMUWE" LOC = "P66" ;
NET "nRAS" LOC = "P64" ;
NET "nRES" LOC = "P91" ;
NET "nROMCS" LOC = "P35" ;
NET "nROMWE" LOC = "P34" ;
NET "nUDS_FSB" LOC = "P33" ;
NET "nUDS_IOB" LOC = "P80" ;
NET "nVMA_IOB" LOC = "P74" ;
NET "nVPA_FSB" LOC = "P93" ;
NET "nVPA_IOB" LOC = "P77" ;
NET "nWE_FSB" LOC = "P29" ;
NET "RA<0>" LOC = "P53" ;
NET "RA<10>" LOC = "P55" ;
NET "RA<11>" LOC = "P63" ;
NET "RA<1>" LOC = "P50" ;
NET "RA<2>" LOC = "P43" ;
NET "RA<3>" LOC = "P41" ;
NET "RA<4>" LOC = "P40" ;
NET "RA<5>" LOC = "P42" ;
NET "RA<6>" LOC = "P46" ;
NET "RA<7>" LOC = "P52" ;
NET "RA<8>" LOC = "P54" ;
NET "RA<9>" LOC = "P56" ;
NET "SW<1>" LOC = "P61" ;
NET "SW<2>" LOC = "P60" ;
NET "SW<3>" LOC = "P67" ;
NET "A_FSB<10>" LOC = "P8" ;
NET "A_FSB<11>" LOC = "P9" ;
NET "A_FSB<12>" LOC = "P10" ;
NET "A_FSB<13>" LOC = "P11" ;
NET "A_FSB<14>" LOC = "P12" ;
NET "A_FSB<15>" LOC = "P13" ;
NET "A_FSB<16>" LOC = "P14" ;
NET "A_FSB<17>" LOC = "P15" ;
NET "A_FSB<18>" LOC = "P16" ;
NET "A_FSB<19>" LOC = "P17" ;
NET "A_FSB<1>" LOC = "P94" ;
NET "A_FSB<20>" LOC = "P18" ;
NET "A_FSB<21>" LOC = "P19" ;
NET "A_FSB<22>" LOC = "P20" ;
NET "A_FSB<23>" LOC = "P24" ;
NET "A_FSB<2>" LOC = "P95" ;
NET "A_FSB<3>" LOC = "P96" ;
NET "A_FSB<4>" LOC = "P97" ;
NET "A_FSB<5>" LOC = "P2" ;
NET "A_FSB<6>" LOC = "P3" ;
NET "A_FSB<7>" LOC = "P4" ;
NET "A_FSB<8>" LOC = "P6" ;
NET "A_FSB<9>" LOC = "P7" ;
NET "C20MEN" LOC = "P59" ;
NET "C25MEN" LOC = "P58" ;
NET "FCLK" LOC = "P27" ;
NET "C16M" LOC = "P22" ;
NET "C8M" LOC = "P23" ;
NET "E" LOC = "P25" ;
NET "nADoutLE0" LOC = "P85" ;
NET "nADoutLE1" LOC = "P82" ;
NET "nAoutOE" LOC = "P87" ;
NET "nAS_FSB" LOC = "P32" ;
NET "nAS_IOB" LOC = "P81" ;
NET "nBERR_FSB" LOC = "P70" ;
NET "nBERR_IOB" LOC = "P76" ;
NET "nBG_IOB" LOC = "P73" ;
NET "nBR_IOB" LOC = "P72" ;
NET "nCAS" LOC = "P36" ;
NET "nDinLE" LOC = "P86" ;
NET "nDinOE" LOC = "P90" ;
NET "nDoutOE" LOC = "P89" ;
NET "nDTACK_FSB" LOC = "P28" ;
NET "nDTACK_IOB" LOC = "P78" ;
NET "nIPL2" LOC = "P92" ;
NET "nLDS_FSB" LOC = "P30" ;
NET "nLDS_IOB" LOC = "P79" ;
NET "nOE" LOC = "P37" ;
NET "nRAMLWE" LOC = "P65" ;
NET "nRAMUWE" LOC = "P66" ;
NET "nRAS" LOC = "P64" ;
NET "nRES" LOC = "P91" ;
NET "nROMCS" LOC = "P35" ;
NET "nROMWE" LOC = "P34" ;
NET "nUDS_FSB" LOC = "P33" ;
NET "nUDS_IOB" LOC = "P80" ;
NET "nVMA_IOB" LOC = "P74" ;
NET "nVPA_FSB" LOC = "P93" ;
NET "nVPA_IOB" LOC = "P77" ;
NET "nWE_FSB" LOC = "P29" ;
NET "RA<0>" LOC = "P53" ;
NET "RA<10>" LOC = "P55" ;
NET "RA<11>" LOC = "P63" ;
NET "RA<1>" LOC = "P50" ;
NET "RA<2>" LOC = "P43" ;
NET "RA<3>" LOC = "P41" ;
NET "RA<4>" LOC = "P40" ;
NET "RA<5>" LOC = "P42" ;
NET "RA<6>" LOC = "P46" ;
NET "RA<7>" LOC = "P52" ;
NET "RA<8>" LOC = "P54" ;
NET "RA<9>" LOC = "P56" ;
NET "SW<1>" LOC = "P61" ;
NET "SW<2>" LOC = "P60" ;
NET "SW<3>" LOC = "P67" ;

83
cpld/XC95144XL/CNT.v
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@ -1,83 +0,0 @@
module CNT(
/* FSB clock and E clock inputs */
input CLK, input E,
/* Refresh request */
output reg RefReq, output RefUrg,
/* Reset, button */
output reg nRESout, input nIPL2,
/* Mac PDS bus master control outputs */
output reg AoutOE, output reg nBR_IOB);
/* E clock synchronization */
reg [1:0] Er;
wire EFall = Er[1] && !Er[0];
always @(posedge CLK) Er[1:0] <= { Er[0], E };
/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
* Refresh timer sequence
* | Timer | RefReq | RefUrg |
* |------------------------------|
* | 0 0000 | 0 | 0 |
* | 1 0001 | 0 | 0 |
* | 2 0010 | 1 | 0 |
* | 3 0011 | 1 | 0 |
* | 4 0100 | 1 | 0 |
* | 5 0101 | 1 | 0 |
* | 6 0110 | 1 | 0 |
* | 7 0111 | 1 | 0 |
* | 8 1000 | 1 | 1 |
* | 9 1001 | 1 | 1 |
* | 10 1010 | 1 | 1 |
* back to timer==0
*/
reg [3:0] Timer = 0;
reg TimerTC;
always @(posedge CLK) begin
if (EFall) begin
if (TimerTC) Timer <= 0;
else Timer <= Timer+1;
RefReq <= !(Timer==4'h0 || Timer==4'h1);
TimerTC <= Timer[3:0]==4'h9;
end
end
assign RefUrg = Timer[3];
/* Long timer counts from 0 to 8191 -- 8192 states == 115.033 ms */
reg [12:0] LTimer;
reg LTimerTC;
always @(posedge CLK) begin
if (EFall && TimerTC) begin
LTimer <= LTimer+1;
LTimerTC <= LTimer[12:0]==13'h1FFE;
end
end
reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
/* Startup sequence control */
reg [1:0] INITS = 0;
wire INITSTC = EFall && TimerTC && LTimerTC;
always @(posedge CLK) begin
case (INITS[1:0])
2'h0: begin
AoutOE <= 0; // Tristate PDS address and control
nRESout <= 0; // Hold reset low
nBR_IOB <= 0; // Default to request bus
if (INITSTC) INITS <= 1;
end 2'h1: begin
AoutOE <= 0;
nRESout <= 0;
nBR_IOB <= !(!nBR_IOB && nIPL2r); // Disable bus request if NMI pressed
if (INITSTC && nIPL2r) INITS <= 2;
end 2'h2: begin
AoutOE <= !nBR_IOB;
nRESout <= 0;
if (INITSTC) INITS <= 3;
end 2'h3: begin
nRESout <= 1; // Release reset
INITS <= 3;
end
endcase
end
endmodule

60
cpld/XC95144XL/CS.v
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@ -1,60 +0,0 @@
module CS(
/* MC68HC000 interface */
input [23:08] A, input CLK, input nRES, input nWE,
/* AS cycle detection */
input BACT,
/* Device select outputs */
output IOCS, output IOPWCS, output IACS,
output ROMCS, output ROMCS4X,
output RAMCS, output RAMCS0X, output SndRAMCSWR);
/* Overlay control */
reg nOverlay = 0; wire Overlay = !nOverlay;
reg ODCSr;
always @(posedge CLK) begin
ODCSr <= ROMCS4X && BACT;
if (!BACT) begin
if (!nRES) nOverlay <= 0;
else if (ODCSr) nOverlay <= 1;
end
end
/* ROM select signals */
assign ROMCS4X = A[23:20]==4'h4;
assign ROMCS = ((A[23:20]==4'h0) && Overlay) || ROMCS4X;
/* RAM select signals */
assign RAMCS0X = A[23:22]==2'b00;
assign RAMCS = RAMCS0X && !Overlay;
wire VidRAMCSWR64k = RAMCS && !nWE && (A[23:20]==4'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF
wire VidRAMCSWR = VidRAMCSWR64k && (
(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
(A[15:12]==4'h3) || // 4096 bytes video
(A[15:12]==4'h4) || // 4096 bytes video
(A[15:12]==4'h5) || // 4096 bytes video
(A[15:12]==4'h6) || // 4096 bytes video
(A[15:12]==4'h7) || // 3200 bytes video, 896 bytes RAM,
(A[15:12]==4'hA) || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
(A[15:12]==4'hB) || // 4096 bytes video
(A[15:12]==4'hC) || // 4096 bytes video
(A[15:12]==4'hD) || // 4096 bytes video
(A[15:12]==4'hE) || // 4096 bytes video
(A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
/* Select signals - IOB domain */
assign IACS = (A[23:20]==4'hF) && (A[19:18]==2'b11); // IACK
assign IOCS = (A[23:20]==4'hF) || // IACK
(A[23:20]==4'hE) || // VIA
(A[23:20]==4'hD) || // IWM
(A[23:20]==4'hC) || // empty / fast ROM
(A[23:20]==4'hB) || // SCC write
(A[23:20]==4'hA) || // empty
(A[23:20]==4'h9) || // SCC read/reset
(A[23:20]==4'h8) || // empty
(A[23:20]==4'h7) || // empty
(A[23:20]==4'h6) || // empty
(A[23:20]==4'h5) || // SCSI
((A[23:20]==4'h4) && Overlay) ||
VidRAMCSWR; // ROM once
assign IOPWCS = VidRAMCSWR;
endmodule

29
cpld/XC95144XL/FSB.v
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@ -1,29 +0,0 @@
module FSB(
/* MC68HC000 interface */
input FCLK, input nAS, output reg nDTACK, output reg nVPA,
/* AS cycle detection */
output BACT,
/* Ready inputs */
input ROMCS,
input RAMCS, input RAMReady,
input IOPWCS, input IOPWReady, input IONPReady,
/* Interrupt acknowledge select */
input IACS);
/* AS cycle detection */
reg ASrf = 0;
always @(negedge FCLK) begin ASrf <= !nAS; end
assign BACT = !nAS || ASrf; // BACT - bus active
/* DTACK/VPA control */
wire Ready = (RAMCS && RAMReady && !IOPWCS) ||
(RAMCS && RAMReady && IOPWCS && IOPWReady) ||
(ROMCS) || (IONPReady);
always @(posedge FCLK) nDTACK <= !(Ready && BACT && !IACS);
always @(posedge FCLK, posedge nAS) begin
if (nAS) nVPA <= 1;
else nVPA <= !(Ready && BACT && IACS);
end
endmodule

120
cpld/XC95144XL/IOBM.v
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@ -1,120 +0,0 @@
module IOBM(
/* PDS interface */
input C16M, input C8M, input E,
output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
input nDTACK, input nVPA, input nBERR, input nRES,
/* PDS address and data latch control */
input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
/* IO bus slave port interface */
input IORDREQ, input IOWRREQ, input IOLDS, input IOUDS,
output reg IOACT, output reg IODONE, output reg IOBERR);
/* C8M clock registration */
reg C8Mr; always @(posedge C16M) C8Mr <= C8M;
/* I/O request input synchronization */
reg IORDREQr; always @(posedge C16M) IORDREQr <= IORDREQ;
reg IOWRREQr; always @(posedge C16M) IOWRREQr <= IOWRREQ;
wire IOREQr = IORDREQr || IOWRREQr;
/* VPA synchronization */
reg VPAr; always @(negedge C8M) VPAr <= !nVPA;
/* E clock synchronization */
reg Er; always @(negedge C8M) begin Er <= E; end
/* E clock state */
reg [3:0] ES;
always @(negedge C8M) begin
if (!E && Er) ES <= 1;
else if (ES==0 || ES==9) ES <= 0;
else ES <= ES+1;
end
/* ETACK and VMA generation */
wire ETACK = (ES==8) && !nVMA;
always @(posedge C8M) begin
if ((ES==5) && IOACT && VPAr) nVMA <= 0;
else if(ES==0) nVMA <= 1;
end
/* DTACK and BERR synchronization */
always @(negedge C8M, posedge nASout) begin
if (nASout) begin
IODONE <= 0;
IOBERR <= 0;
end else begin
IODONE <= (!nDTACK || ETACK || !nRES);
IOBERR <= !nBERR;
end
end
/* I/O bus state */
reg [2:0] IOS = 0;
reg IOS0;
always @(posedge C16M) begin
if (IOS==0) begin
if (IOREQr && !C8Mr && AoutOE) begin // "IOS1"
IOS <= 2;
IOS0 <= 0;
end else begin // "regular" IOS0
IOS <= 0;
IOS0 <= 1;
end
IOACT <= IOREQr && AoutOE;
ALE0 <= IOREQr && AoutOE;
end else if (IOS==2) begin
IOS <= 3;
IOS0 <= 0;
IOACT <= 1;
ALE0 <= 1;
end else if (IOS==3) begin
IOS <= 4;
IOS0 <= 0;
IOACT <= 1;
ALE0 <= 1;
end else if (IOS==4) begin
IOS <= 5;
IOS0 <= 0;
IOACT <= 1;
ALE0 <= 1;
end else if (IOS==5) begin
if (!C8Mr && (IODONE || IOBERR)) begin
IOS <= 6;
IOACT <= 0;
end else begin
IOS <= 5;
IOACT <= 1;
end
IOS0 <= 0;
ALE0 <= 1;
end else if (IOS==6) begin
IOS <= 7;
IOS0 <= 0;
IOACT <= 0;
ALE0 <= 0;
end else if (IOS==7) begin
IOS <= 0;
IOS0 <= 1;
IOACT <= 0;
ALE0 <= 0;
end
end
/* PDS address and data latch control */
always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end
reg DoutOE = 0;
always @(posedge C16M) begin
DoutOE <= (IOS==0 && IOWRREQr && !C8Mr) ||
(DoutOE && (IOS==2 || IOS==3 || IOS==4 || IOS==5));
end
assign nDoutOE = !(AoutOE && (DoutOE || (IOS0 && !IOREQr)));
/* AS, DS control */
always @(negedge C16M) begin
nASout <= !((IOS==0 && IOREQr && !C8Mr) || IOS==2 || IOS==3 || IOS==4 || IOS==5);
nLDS <= !(IOLDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nLDS) || IOS==3 || IOS==4 || IOS==5));
nUDS <= !(IOUDS && ((IOS==0 && IORDREQr && !C8Mr) || (IOS==2 && !nUDS) || IOS==3 || IOS==4 || IOS==5));
end
endmodule

148
cpld/XC95144XL/IOBS.v
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@ -1,148 +0,0 @@
module IOBS(
/* MC68HC000 interface */
input CLK, input nWE, input nAS, input nLDS, input nUDS,
/* AS cycle detection */
input BACT,
/* Select signals */
input IOCS, input IOPWCS, input ROMCS,
/* FSB cycle termination outputs */
output reg IONPReady, output reg IOPWReady, output reg nBERR_FSB,
/* Read data OE control */
output nDinOE,
/* IOB master controller interface */
output reg IORDREQ, output reg IOWRREQ,
input IOACT, input IODONEin, input IOBERR,
/* FIFO primary level control */
output reg ALE0, output reg IOL0, output reg IOU0,
/* FIFO secondary level control */
output reg ALE1);
/* IOACT input synchronization */
reg IOACTr = 0; always @(posedge CLK) IOACTr <= IOACT;
/* IODTACK input synchronization */
reg IODONEr; always @(posedge CLK) IODONEr <= IODONEin;
wire IODONE = IODONEr;
/* Read data OE control */
assign nDinOE = !(!nAS && IOCS && nWE && !ROMCS);
/* I/O transfer state
* TS0 - I/O bridge idle:
* asserts IOREQ
* transitions to TS3 when BACT && IOCS && !ALE1 && !Sent
* TS3 - starting I/O transfer:
latches LDS and UDS from FSB or FIFO secondary level
transitions immediately to TS2
* TS2 - waiting for IOBM to begin:
transitions to TS1 when IOACT true
* TS1 - waiting for IOBM to finish:
* transitions to TS1 when IOACT false */
reg [1:0] TS = 0;
reg Sent = 0;
/* FIFO secondary level control */
reg Load1;
reg Clear1;
reg IORW1;
reg IOL1;
reg IOU1;
always @(posedge CLK) begin // ALE and R/W load control
// If write currently posting (TS!=0),
// I/O selected, and FIFO secondary level empty
if (BACT && IOCS && !ALE1 && !Sent && IOPWCS && TS!=0) begin
// Latch R/W now but latch address and LDS/UDS next cycle
IORW1 <= nWE;
Load1 <= 1;
end else Load1 <= 0;
end
always @(posedge CLK) begin // ALE clear control
// Make address latch transparent in cycle after TS3
// (i.e. first TS2 cycle that's not part of current write)
if (TS==3) Clear1 <= 1;
else Clear1 <= 0;
end
always @(posedge CLK) begin // LDS, UDS, ALE control
if (Load1) begin // Latch address, LDS, UDS when Load1 true
ALE1 <= 1;
IOL1 <= !nLDS;
IOU1 <= !nUDS;
end else if (Clear1) ALE1 <= 0;
end
/* FIFO primary level control */
always @(posedge CLK) begin
if (TS==0) begin
if (ALE1) begin // If FIFO secondary level occupied
// Request transfer from IOBM and latch R/W from FIFO
TS <= 3;
IORDREQ <= IORW1;
IOWRREQ <= !IORW1;
IOL0 <= IOL1;
IOU0 <= IOU1;
end else if (BACT && IOCS && !ALE1 && !Sent) begin // FSB request
// Request transfer from IOBM and latch R/W from FSB
TS <= 3;
IORDREQ <= nWE;
IOWRREQ <= !nWE;
IOL0 <= !nLDS;
IOU0 <= !nUDS;
end else begin // Otherwise stay in idle
TS <= 0;
IORDREQ <= 0;
IOWRREQ <= 0;
end
ALE0 <= 0;
end else if (TS==3) begin
TS <= 2; // Always go to TS2. Keep IORDREQ/IOWRREQ active
ALE0 <= 1; // Latch address (and data)
// Latch data strobes from FIFO or FSB as appropriate
if (ALE1) begin
IOL0 <= IOL1;
IOU0 <= IOU1;
end else begin
IOL0 <= !nLDS;
IOU0 <= !nUDS;
end
end else if (TS==2) begin
// Wait for IOACT then withdraw IOREQ and enter TS1
if (IOACTr) begin
TS <= 1;
IORDREQ <= 0;
IOWRREQ <= 0;
end else TS <= 2;
ALE0 <= 1; // Keep address latched
end else if (TS==1) begin
// Wait for IOACT low (transfer over) before going back to idle
if (!IOACTr) TS <= 0;
else TS <= 1;
IORDREQ <= 0;
IOWRREQ <= 0;
ALE0 <= 0; // Release addr latch since it's controlled by IOBM now
end
end
/* Sent control */
always @(posedge CLK) begin
if (!BACT) Sent <= 0;
else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
end
/* Nonposted ready */
always @(posedge CLK) begin
if (!BACT) IONPReady <= 0;
else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
end
/* Posted ready */
always @(posedge CLK) begin
if (!BACT) IOPWReady <= 0;
else if (Clear1 || !ALE1) IOPWReady <= 1;
end
/* BERR control */
always @(posedge CLK) begin
if (!BACT) nBERR_FSB <= 1;
else if (Sent && IOBERR) nBERR_FSB <= 0;
end
endmodule

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module RAM(
/* MC68HC000 interface */
input CLK, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS,
/* AS cycle detection */
input BACT,
/* Select and ready signals */
input RAMCS, input ROMCS, output reg RAMReady,
/* Refresh Counter Interface */
input RefReqIn, input RefUrgIn,
/* DRAM and NOR flash interface */
output [11:0] RA, output nRAS, output reg nCAS,
output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
/* BACT saved from last cycle */
reg BACTr; always @(posedge CLK) BACTr <= BACT;
/* RAM control state */
reg [2:0] RS = 0;
reg RAMEN = 0;
reg Once = 0;
reg RASEL = 0;
reg CAS = 0;
reg RASrr = 0;
reg RASrf = 0;
/* Refresh command generation */
reg RefDone; // Refresh done "remember"
always @(posedge CLK) begin
if (!RefReqIn && !RefUrgIn) RefDone <= 0;
else if (RS==4 || RS==5) RefDone <= 1;
end
wire RefReq = RefReqIn && !RefDone;
wire RefUrg = RefUrgIn && !RefDone;
/* RAM control signals */
assign nRAS = !((!nAS && RAMCS && RAMEN) || RASrr || RASrf);
assign nOE = !((!nAS && nWE)); // Shared with ROM
assign nLWE = !((!nAS && !nWE && !nLDS && RAMEN));
assign nUWE = !((!nAS && !nWE && !nUDS && RAMEN));
/* ROM control signals */
assign nROMCS = !ROMCS;
assign nROMWE = !((!nAS && !nWE));
/* RAM address mux (and ROM address on RA8) */
// RA11 doesn't do anything so both should be identical.
assign RA[11] = !RASEL ? A[19] : A[20]; // ROM address 19
assign RA[03] = !RASEL ? A[19] : A[20];
// RA10 has only row so different rows but same column.
assign RA[10] = !RASEL ? A[17] : A[07];
assign RA[02] = !RASEL ? A[16] : A[07];
// Remainder of RA bus is unpaired
assign RA[09] = !RASEL ? A[15] : A[08];
assign RA[08] = !RASEL ? A[18] : A[21]; // ROM address 18
assign RA[07] = !RASEL ? A[14] : A[06];
assign RA[06] = !RASEL ? A[13] : A[05];
assign RA[05] = !RASEL ? A[12] : A[04];
assign RA[04] = !RASEL ? A[11] : A[03];
assign RA[01] = !RASEL ? A[10] : A[02];
assign RA[00] = !RASEL ? A[09] : A[01];
wire RefFromRS0 = ((RefReq && BACT && !BACTr && !RAMCS) ||
(RefUrg && !BACT) ||
(RefUrg && BACT && !RAMEN));
wire RefFromRS2 = RefUrg;
wire RAMStart = BACT && RAMCS && RAMEN;
always @(posedge CLK) begin
case (RS[2:0])
0: begin
if (RAMStart) begin
RS <= 1;
RASEL <= 1;
CAS <= 1;
RASrr <= 1;
end else if (RefFromRS0) begin
RS <= 3;
RASEL <= 0;
CAS <= 1;
RASrr <= 0;
end else begin
RS <= 0;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
end
end 1: begin
RS <= 2;
RASEL <= 1;
CAS <= 1;
RASrr <= 0;
end 2: begin
if (RefFromRS2) begin
RS <= 3;
RASEL <= 0;
CAS <= 1;
RASrr <= 0;
end else begin
RS <= 7;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
end
end 3: begin
RS <= 4;
RASEL <= 0;
CAS <= 1;
RASrr <= 1;
end 4: begin
RS <= 5;
RASEL <= 0;
CAS <= 0;
RASrr <= 1;
end 5: begin
RS <= 6;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
end 6: begin
RS <= 7;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
end 7: begin
RS <= 0;
RASEL <= 0;
CAS <= 0;
RASrr <= 0;
end
endcase
end
always @(negedge CLK) RASrf <= RS==1;
always @(negedge CLK) nCAS <= !CAS;
/* RAM state control */
always @(posedge CLK) begin
if (RS==0 && RefFromRS0) RAMEN <= 0;
else if (RS==1) RAMEN <= 0;
else if (!BACT && RS==7) RAMEN <= 1;
else if (!BACT && RS==0) RAMEN <= 1;
else if (!Once && RS==7) RAMEN <= 1;
else if (!Once && RS==0) RAMEN <= 1; // not needed?
end
always @(posedge CLK) begin
if (!BACT) Once <= 0;
else if (RS==0 && RAMStart) Once <= 1;
end
/* RAM ready signal */
always @(posedge CLK) begin
RAMReady <= (BACT && RAMReady) || (RS==7) || (RS==0 && !RefFromRS0);
end
endmodule

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cpld/XC95144XL/WarpSE-XC95144XL.ucf
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NET "A_FSB<10>" LOC = "P8" ;
NET "A_FSB<11>" LOC = "P9" ;
NET "A_FSB<12>" LOC = "P10" ;
NET "A_FSB<13>" LOC = "P11" ;
NET "A_FSB<14>" LOC = "P12" ;
NET "A_FSB<15>" LOC = "P13" ;
NET "A_FSB<16>" LOC = "P14" ;
NET "A_FSB<17>" LOC = "P15" ;
NET "A_FSB<18>" LOC = "P16" ;
NET "A_FSB<19>" LOC = "P17" ;
NET "A_FSB<1>" LOC = "P94" ;
NET "A_FSB<20>" LOC = "P18" ;
NET "A_FSB<21>" LOC = "P19" ;
NET "A_FSB<22>" LOC = "P20" ;
NET "A_FSB<23>" LOC = "P24" ;
NET "A_FSB<2>" LOC = "P95" ;
NET "A_FSB<3>" LOC = "P96" ;
NET "A_FSB<4>" LOC = "P97" ;
NET "A_FSB<5>" LOC = "P2" ;
NET "A_FSB<6>" LOC = "P3" ;
NET "A_FSB<7>" LOC = "P4" ;
NET "A_FSB<8>" LOC = "P6" ;
NET "A_FSB<9>" LOC = "P7" ;
NET "C20MEN" LOC = "P59" ;
NET "C25MEN" LOC = "P58" ;
NET "FCLK" LOC = "P27" ;
NET "C16M" LOC = "P22" ;
NET "C8M" LOC = "P23" ;
NET "E" LOC = "P25" ;
NET "nADoutLE0" LOC = "P85" ;
NET "nADoutLE1" LOC = "P82" ;
NET "nAoutOE" LOC = "P87" ;
NET "nAS_FSB" LOC = "P32" ;
NET "nAS_IOB" LOC = "P81" ;
NET "nBERR_FSB" LOC = "P70" ;
NET "nBERR_IOB" LOC = "P76" ;
NET "nBG_IOB" LOC = "P73" ;
NET "nBR_IOB" LOC = "P72" ;
NET "nCAS" LOC = "P36" ;
NET "nDinLE" LOC = "P86" ;
NET "nDinOE" LOC = "P90" ;
NET "nDoutOE" LOC = "P89" ;
NET "nDTACK_FSB" LOC = "P28" ;
NET "nDTACK_IOB" LOC = "P78" ;
NET "nIPL2" LOC = "P92" ;
NET "nLDS_FSB" LOC = "P30" ;
NET "nLDS_IOB" LOC = "P79" ;
NET "nOE" LOC = "P37" ;
NET "nRAMLWE" LOC = "P65" ;
NET "nRAMUWE" LOC = "P66" ;
NET "nRAS" LOC = "P64" ;
NET "nRES" LOC = "P91" ;
NET "nROMCS" LOC = "P35" ;
NET "nROMWE" LOC = "P34" ;
NET "nUDS_FSB" LOC = "P33" ;
NET "nUDS_IOB" LOC = "P80" ;
NET "nVMA_IOB" LOC = "P74" ;
NET "nVPA_FSB" LOC = "P93" ;
NET "nVPA_IOB" LOC = "P77" ;
NET "nWE_FSB" LOC = "P29" ;
NET "RA<0>" LOC = "P53" ;
NET "RA<10>" LOC = "P55" ;
NET "RA<11>" LOC = "P63" ;
NET "RA<1>" LOC = "P50" ;
NET "RA<2>" LOC = "P43" ;
NET "RA<3>" LOC = "P41" ;
NET "RA<4>" LOC = "P40" ;
NET "RA<5>" LOC = "P42" ;
NET "RA<6>" LOC = "P46" ;
NET "RA<7>" LOC = "P52" ;
NET "RA<8>" LOC = "P54" ;
NET "RA<9>" LOC = "P56" ;
NET "SW<1>" LOC = "P61" ;
NET "SW<2>" LOC = "P60" ;
NET "SW<3>" LOC = "P67" ;

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module WarpSE(
input [23:1] A_FSB,
input nAS_FSB,
input nLDS_FSB,
input nUDS_FSB,
input nWE_FSB,
output nDTACK_FSB,
output nVPA_FSB,
output nBERR_FSB,
input FCLK,
input C16M,
input C8M,
input E,
input nDTACK_IOB,
input nVPA_IOB,
output nVMA_IOB,
output nAS_IOB,
output nUDS_IOB,
output nLDS_IOB,
output nBR_IOB,
input nBG_IOB,
input nBERR_IOB,
inout nRES,
input nIPL2,
output nROMCS,
output nRAMLWE,
output nRAMUWE,
output nROMWE,
output nRAS,
output nCAS,
output [11:0] RA,
output nOE,
output nADoutLE0,
output nADoutLE1,
output nAoutOE,
output nDoutOE,
output nDinOE,
output nDinLE,
input [3:1] SW,
output C20MEN,
output C25MEN);
/* FSB clock oscillator enables */
// Enable both oscillators... only mount one
assign C20MEN = 0;
assign C25MEN = 1;
/* Reset input and open-drain output */
wire nRESin = nRES;
wire nRESout;
assign nRES = !nRESout ? 1'b0 : 1'bZ;
/* AS cycle detection */
wire BACT;
/* Refresh request/ack signals */
wire RefReq, RefUrg;
/* FSB chip select signals */
wire IOCS, IOPWCS, IACS;
wire ROMCS, ROMCS4X;
wire RAMCS, RAMCS0X;
CS cs(
/* MC68HC000 interface */
A_FSB[23:08], FCLK, nRESin, nWE_FSB,
/* AS cycle detection */
BACT,
/* Device select outputs */
IOCS, IOPWCS, IACS,
ROMCS, ROMCS4X,
RAMCS, RAMCS0X);
wire RAMReady;
RAM ram(
/* MC68HC000 interface */
FCLK, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
/* AS cycle detection */
BACT,
/* Select and ready signals */
RAMCS, ROMCS, RAMReady,
/* Refresh Counter Interface */
RefReq, RefUrg,
/* DRAM and NOR flash interface */
RA[11:0], nRAS, nCAS,
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
wire IONPReady, IOPWReady;
wire IORDREQ, IOWRREQ;
wire IOL0, IOU0;
wire ALE0S, ALE0M, ALE1;
assign nADoutLE0 = ~(ALE0S || ALE0M);
assign nADoutLE1 = ~ALE1;
wire IOACT, IODONE, IOBERR;
IOBS iobs(
/* MC68HC000 interface */
FCLK, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
/* AS cycle detection */
BACT,
/* Select signals */
IOCS, IOPWCS, ROMCS,
/* FSB cycle termination outputs */
IONPReady, IOPWReady, nBERR_FSB,
/* Read data OE control */
nDinOE,
/* IOB Master Controller Interface */
IORDREQ, IOWRREQ,
IOACT, IODONE, IOBERR,
/* FIFO primary level control */
ALE0S, IOL0, IOU0,
/* FIFO secondary level control */
ALE1);
wire AoutOE;
assign nAoutOE = !AoutOE;
wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
IOBM iobm(
/* PDS interface */
C16M, C8M, E,
nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
/* PDS address and data latch control */
AoutOE, nDoutOE, ALE0M, nDinLE,
/* IO bus slave port interface */
IORDREQ, IOWRREQ, IOL0, IOU0,
IOACT, IODONE, IOBERR);
CNT cnt(
/* FSB clock and E clock inputs */
FCLK, E,
/* Refresh request */
RefReq, RefUrg,
/* Reset, button */
nRESout, nIPL2,
/* Mac PDS bus master control outputs */
AoutOE, nBR_IOB);
FSB fsb(
/* MC68HC000 interface */
FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
/* FSB cycle detection */
BACT,
/* Ready inputs */
ROMCS4X,
RAMCS0X, RAMReady,
IOPWCS, IOPWReady, IONPReady,
/* Interrupt acknowledge select */
IACS);
endmodule