put 0.7a source, .jed, etc back and recompile

2025-01-03 00:30:06 +00:00 · 2024-10-12 02:20:41 -04:00 · 2024-10-12 02:20:41 -04:00 · a1d07e308f
commit a1d07e308f
parent 44f59d8bd1
38 changed files with 3113 additions and 3104 deletions
--- a/cpld/SET.v
+++ b/cpld/SET.v
@ -18,13 +18,13 @@ module SET(
 	always @(posedge CLK) begin
 		if (!nPOR) begin
 			SlowTimeout[3:0] <= 4'hF;
-			SlowIACK <= 0;
+			SlowIACK <= 1;
 			SlowVIA  <= 1;
 			SlowIWM  <= 1;
-			SlowSCC  <= 0;
-			SlowSCSI <= 0;
+			SlowSCC  <= 1;
+			SlowSCSI <= 1;
 			SlowSnd  <= 1;
-			SlowClockGate <= 0;
+			SlowClockGate <= 1;
 		end else if (SetWRr) begin
 			SlowTimeout[3:0] <= A[11:8];
 			SlowIACK <= A[7];
--- a/cpld/XC95144XL/WarpSE.bld
+++ b/cpld/XC95144XL/WarpSE.bld
@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

-Total memory usage is 154688 kilobytes
+Total memory usage is 154368 kilobytes

 Writing NGD file "WarpSE.ngd" ...
 Total REAL time to NGDBUILD completion:  3 sec
--- a/cpld/XC95144XL/WarpSE.cmd_log
+++ b/cpld/XC95144XL/WarpSE.cmd_log
@ -1467,3 +1467,10 @@ XSLTProcess WarpSE_build.xml
 tsim -intstyle ise WarpSE WarpSE.nga 
 taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm 
 hprep6 -s IEEE1149 -n WarpSE -i WarpSE 
+xst -intstyle ise -ifn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/WarpSE.syr" 
+ngdbuild -intstyle ise -dd _ngo -uc C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd  
+cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd 
+XSLTProcess WarpSE_build.xml 
+tsim -intstyle ise WarpSE WarpSE.nga 
+taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm 
+hprep6 -s IEEE1149 -n WarpSE -i WarpSE 
--- a/cpld/XC95144XL/WarpSE.gise
+++ b/cpld/XC95144XL/WarpSE.gise
@ -70,7 +70,7 @@
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1728713769" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728713762">
+    <transform xil_pn:end_ts="1728713909" xil_pn:in_ck="1680431259208978880" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1728713902">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@ -90,7 +90,7 @@
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1728713775" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728713769">
+    <transform xil_pn:end_ts="1728713915" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1728713909">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="WarpSE.bld"/>
@ -99,7 +99,7 @@
      <outfile xil_pn:name="_ngo"/>
      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    </transform>
-    <transform xil_pn:end_ts="1728713794" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728713775">
+    <transform xil_pn:end_ts="1728713934" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1728713915">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@ -119,7 +119,7 @@
      <outfile xil_pn:name="WarpSE_html"/>
      <outfile xil_pn:name="WarpSE_pad.csv"/>
    </transform>
-    <transform xil_pn:end_ts="1728713802" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728713800">
+    <transform xil_pn:end_ts="1728713947" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1728713945">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="WarpSE.jed"/>
@ -127,6 +127,8 @@
    <transform xil_pn:end_ts="1728713802" xil_pn:in_ck="4179227257689331" xil_pn:name="TRAN_impactProgrammingTool_CPLD" xil_pn:prop_ck="-207801193714804843" xil_pn:start_ts="1728713802">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
      <outfile xil_pn:name="_impactbatch.log"/>
      <outfile xil_pn:name="ise_impact.cmd"/>
    </transform>
@ -140,7 +142,7 @@
      <outfile xil_pn:name="_impactbatch.log"/>
      <outfile xil_pn:name="ise_impact.cmd"/>
    </transform>
-    <transform xil_pn:end_ts="1728713796" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728713794">
+    <transform xil_pn:end_ts="1728713937" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1728713934">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
--- a/cpld/XC95144XL/WarpSE.jed
+++ b/cpld/XC95144XL/WarpSE.jed
@ -1,5 +1,5 @@
 Programmer Jedec Bit Map
-Date Extracted: Sat Oct 12 02:16:41 2024
+Date Extracted: Sat Oct 12 02:19:06 2024

 QF93312*
 QP100*
@ -330,7 +330,7 @@ L0013632 000000 000000 000000 000000 000001 000000 000000 000000*
 L0013680 000000 000000 000000 000000 000001 000000 000000 000000*
 L0013728 000000 000000 000000 000000 000001 000000 000000 000000*
 L0013776 000000 000000 000000 000000 000001 000000 000000 000000*
-L0013824 00000000 00000000 00000000 00000000 00011010 00000001 01001011 00000011*
+L0013824 00001000 00000000 00000000 00000000 00011010 00000001 01001011 00000011*
 L0013888 00000000 00000000 00000000 00000000 00011000 00000011 00011000 00000001*
 L0013952 00000000 00000000 00000000 00000000 00001000 00000001 00000000 00000001*
 L0014016 00000000 00000000 00000000 00000000 00000001 00000001 00010001 00000011*
@ -345,7 +345,7 @@ L0014496 000000 000000 000000 000001 000000 000000 000000 000000*
 L0014544 000000 000000 000000 000000 000000 000000 001000 000000*
 L0014592 000000 000000 000000 000000 000000 000000 001100 000000*
 L0014640 000000 000000 000000 000000 000000 000000 000000 000000*
-L0014688 00001000 00000000 11111000 01000000 00000000 00000000 00010000 00000000*
+L0014688 00000000 00000000 11111000 01000000 00000000 00000000 00010000 00000000*
 L0014752 00000000 00000000 00000000 01000000 00000000 00000000 00000011 01000010*
 L0014816 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01001010*
 L0014880 00000000 00000000 00000000 00000000 00000000 00000000 10000100 00001000*
@ -423,11 +423,11 @@ L0018960 000000 000000 000000 000000 000000 000000 000000 000000*
 L0019008 00000011 00000000 00000000 00000001 00000000 00000001 00000010 00000000*
 L0019072 00000001 00000000 00000010 00000011 00000010 00000000 00000000 00000000*
 L0019136 00000001 00000000 00000000 00000001 00000000 00000010 00000011 00000000*
-L0019200 00000000 00000000 00000000 00000001 00000000 00000010 00000000 00000010*
-L0019264 00000000 00000000 00000000 00000010 00000010 00000001 00000000 00000010*
+L0019200 00000001 00000000 00000000 00000001 00000000 00000010 00000000 00000010*
+L0019264 00000001 00000000 00000000 00000010 00000010 00000001 00000000 00000010*
 L0019328 00000001 00000000 00000001 00000011 00000010 00000010 00000000 00000010*
-L0019392 00000000 00000000 00000001 00000010 00000000 00000001 00000001 00000000*
-L0019456 00000000 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
+L0019392 00000001 00000000 00000001 00000010 00000000 00000001 00000001 00000000*
+L0019456 00000001 00000000 00000001 00000000 00000001 00000011 00000000 00000010*
 L0019520 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000*
 L0019584 000000 000000 000000 000000 000000 000000 000000 000000*
 L0019632 000000 001000 000000 000000 000000 100000 000000 000100*
@ -455,7 +455,7 @@ L0020800 00000000 00000000 00000000 00001000 00000000 00000000 00000000 00000010
 L0020864 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0020928 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0020992 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000001*
-L0021056 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0021056 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0021120 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
 L0021184 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
 L0021248 00000000 00000000 00000010 00000000 00000000 00000001 00000000 00000000*
@ -470,7 +470,7 @@ L0021664 00000000 00000000 00000000 00000000 00000000 00001000 00000011 00000010
 L0021728 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000010*
 L0021792 00000000 00000000 00000000 00000000 00000000 00001000 00000000 00000000*
 L0021856 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000*
-L0021920 00000100 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
+L0021920 00000000 00000100 00000000 00000000 00000000 00000000 00001000 00100001*
 L0021984 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0022048 00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000000*
 L0022112 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
@ -510,7 +510,7 @@ L0024000 000000 000000 000000 010000 000000 000000 000011 001000*
 L0024048 000000 000000 000000 010000 000000 000000 001011 001000*
 L0024096 000000 000000 000000 000000 000000 000000 001011 000000*
 L0024144 000000 000000 000000 000000 000000 000000 001011 000000*
-L0024192 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0024192 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0024256 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0024320 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000100*
 L0024384 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000*
@ -525,7 +525,7 @@ L0024864 000000 000000 000011 000000 000000 000000 000000 000000*
 L0024912 000000 000000 000011 000000 000000 000000 000000 000000*
 L0024960 000000 000000 000000 000000 000000 000000 000000 000000*
 L0025008 000000 000000 000001 000000 000000 000000 000000 000000*
-L0025056 00000100 00000000 00000100 00000000 00000000 00000000 00000000 00000000*
+L0025056 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000*
 L0025120 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0025184 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0025248 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
@ -995,7 +995,7 @@ L0051904 00000000 00000000 00000000 00000010 00000001 00000000 00000001 00000011
 L0051968 00000001 00000000 00000000 00000000 00000010 00000011 00000010 00000011*
 L0052032 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0052096 00000001 00000000 00000010 00000000 00000001 00001011 00000011 00000011*
-L0052160 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
+L0052160 00001000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
 L0052224 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0052288 00000000 00000000 00000000 00000000 00000000 00010000 00000000 00000000*
 L0052352 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
@ -1010,7 +1010,7 @@ L0052768 00000000 00000010 00000000 00000000 00000000 00000000 00000000 00000010
 L0052832 00000000 00000001 00000000 00000011 00000000 00000010 00000001 00000010*
 L0052896 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0052960 00000000 00000001 00000010 00000010 00000010 00000010 00000001 00000010*
-L0053024 00001000 00000000 00000000 00010000 00000000 00000000 00000000 00010000*
+L0053024 00000000 00000000 00000000 00010000 00000000 00000000 00000000 00010000*
 L0053088 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
 L0053152 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00010000*
 L0053216 00000000 00000000 00000000 00000000 01000000 00000000 00000000 00010000*
@ -1446,7 +1446,7 @@ L0077888 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000
 L0077952 00000000 00000000 00000100 00000000 00000000 00000000 00000000 00000000*
 L0078016 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078080 00000000 00000000 10000000 00000000 00000000 00000000 00000000 00000000*
-L0078144 00000000 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
+L0078144 00000100 00000000 10001000 00000000 00000000 00000000 00000000 00000000*
 L0078208 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078272 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078336 000000 000000 000000 000000 000000 000000 000000 000000*
@ -1461,7 +1461,7 @@ L0078752 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 L0078816 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078880 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0078944 00000000 00000000 00001000 00000000 00000000 00000000 00000000 00010000*
-L0079008 00000100 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
+L0079008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
 L0079072 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
 L0079136 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000*
 L0079200 000000 000000 000000 000000 000001 000000 000000 000000*
@ -1536,7 +1536,7 @@ L0083072 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 L0083136 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0083200 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0083264 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
-L0083328 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0083328 00001000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0083392 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0083456 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0083520 000000 000000 000000 000000 000000 000000 000000 000000*
@ -1551,7 +1551,7 @@ L0083936 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 L0084000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0084064 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0084128 00000000 00000000 00000000 00000000 00000000 00001000 00000000 01000000*
-L0084192 00001000 00000000 00000000 00000000 00000000 00000000 10000000 00000000*
+L0084192 00000000 00000000 00000000 00000000 00000000 00000000 10000000 00000000*
 L0084256 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0084320 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0084384 000000 000000 000000 000000 000000 000000 000000 000000*
@ -1591,7 +1591,7 @@ L0086256 000000 000000 000001 000000 000000 000000 000000 000000*
 L0086304 000000 000000 000000 000000 000000 000000 000000 000000*
 L0086352 000000 000000 000000 000000 000000 000000 000000 000000*
 L0086400 00000000 00000000 00000000 00000000 00000100 00000000 00001000 00000000*
-L0086464 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
+L0086464 00000100 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
 L0086528 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
 L0086592 00000000 00000000 00000000 00000000 00000000 00000000 00001000 00000000*
 L0086656 00000000 00000000 00000000 00000000 00000000 00000000 10000100 00000000*
@ -1606,7 +1606,7 @@ L0087120 000000 000000 000000 000000 000000 000000 000011 001000*
 L0087168 000000 000000 000000 000000 000000 000000 000011 000000*
 L0087216 000000 000000 000000 000000 000000 000000 000011 000001*
 L0087264 00000000 00001000 00000000 00000000 00000000 00000000 00000000 00000000*
-L0087328 00000100 00000000 00010000 00000000 00000000 00000000 00000000 00000000*
+L0087328 00000000 00000000 00010000 00000000 00000000 00000000 00000000 00000000*
 L0087392 00000000 00000000 00000000 00000000 00001100 00000000 00000000 01000000*
 L0087456 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00001000*
 L0087520 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00000000*
@ -1651,7 +1651,7 @@ L0089712 000000 000000 000000 000000 000000 000000 000000 000000*
 L0089760 000000 000000 000000 000000 000000 000000 000000 000000*
 L0089808 000000 000000 000000 000000 000000 000000 000000 000000*
 L0089856 00000000 00000000 00000000 10100000 00000000 00000000 00000000 00000000*
-L0089920 00000000 00000000 00000100 00000100 00000000 00000000 00010000 00000000*
+L0089920 00001000 00000000 00000100 00000100 00000000 00000000 00010000 00000000*
 L0089984 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00000000*
 L0090048 00000000 00000000 00000000 00100100 00000000 00000000 00010000 00000000*
 L0090112 00000000 00000000 00000000 00000000 00000000 00000000 00010000 00000000*
@ -1666,7 +1666,7 @@ L0090576 000000 000000 000000 000000 000000 000000 001000 000100*
 L0090624 000000 000000 000000 000010 000000 000000 001000 000000*
 L0090672 000000 000000 000000 000000 000000 000000 001000 000000*
 L0090720 00000000 00000100 10000000 00000000 00000000 00000000 10001100 00000000*
-L0090784 00001000 00000000 00000000 00000000 00000000 00000000 10100100 00000000*
+L0090784 00000000 00000000 00000000 00000000 00000000 00000000 10100100 00000000*
 L0090848 00000000 00000000 00000100 00000000 00000000 00000000 00001000 00000000*
 L0090912 00000000 00000000 01111000 00000000 00000000 00000000 00000000 00000000*
 L0090976 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
@ -1710,5 +1710,5 @@ L0093120 000000 000000 000000 000000 000000 000010 010000 000000*
 L0093168 000000 000000 000000 000000 000001 000000 000000 000000*
 L0093216 000000 000000 000000 000000 000000 000000 000000 000000*
 L0093264 000000 000000 000001 000000 000001 000000 000000 000000*
-C4A76*
-29D6
+C4C76*
+29DC
--- a/cpld/XC95144XL/WarpSE.mfd
+++ b/cpld/XC95144XL/WarpSE.mfd
@ -575,8 +575,8 @@ INPUTS | 4 | nPOR  | SlowClockGate  | set/SetWRr  | A_FSB<1>
 INPUTMC | 3 | 0 | 17 | 0 | 16 | 6 | 3
 INPUTP | 1 | 149
 EQ | 3 | 
-   SlowClockGate.D = nPOR & SlowClockGate & !set/SetWRr
-	# nPOR & A_FSB<1> & set/SetWRr;
+   !SlowClockGate.D = nPOR & !SlowClockGate & !set/SetWRr
+	# nPOR & !A_FSB<1> & set/SetWRr;
   SlowClockGate.CLK = FCLK;	// GCK
 GLOBALS | 1 | 2 | FCLK

@ -587,8 +587,8 @@ INPUTS | 4 | nPOR  | SlowIACK  | set/SetWRr  | A_FSB<7>
 INPUTMC | 3 | 0 | 17 | 0 | 15 | 6 | 3
 INPUTP | 1 | 8
 EQ | 3 | 
-   SlowIACK.D = nPOR & SlowIACK & !set/SetWRr
-	# nPOR & A_FSB<7> & set/SetWRr;
+   !SlowIACK.D = nPOR & !SlowIACK & !set/SetWRr
+	# nPOR & !A_FSB<7> & set/SetWRr;
   SlowIACK.CLK = FCLK;	// GCK
 GLOBALS | 1 | 2 | FCLK

@ -611,8 +611,8 @@ INPUTS | 4 | nPOR  | SlowSCC  | set/SetWRr  | A_FSB<4>
 INPUTMC | 3 | 0 | 17 | 0 | 13 | 6 | 3
 INPUTP | 1 | 157
 EQ | 3 | 
-   SlowSCC.D = nPOR & SlowSCC & !set/SetWRr
-	# nPOR & A_FSB<4> & set/SetWRr;
+   !SlowSCC.D = nPOR & !SlowSCC & !set/SetWRr
+	# nPOR & !A_FSB<4> & set/SetWRr;
   SlowSCC.CLK = FCLK;	// GCK
 GLOBALS | 1 | 2 | FCLK

@ -623,8 +623,8 @@ INPUTS | 4 | nPOR  | SlowSCSI  | set/SetWRr  | A_FSB<3>
 INPUTMC | 3 | 0 | 17 | 0 | 12 | 6 | 3
 INPUTP | 1 | 155
 EQ | 3 | 
-   SlowSCSI.D = nPOR & SlowSCSI & !set/SetWRr
-	# nPOR & A_FSB<3> & set/SetWRr;
+   !SlowSCSI.D = nPOR & !SlowSCSI & !set/SetWRr
+	# nPOR & !A_FSB<3> & set/SetWRr;
   SlowSCSI.CLK = FCLK;	// GCK
 GLOBALS | 1 | 2 | FCLK

--- a/cpld/XC95144XL/WarpSE.nga
+++ b/cpld/XC95144XL/WarpSE.nga
--- a/cpld/XC95144XL/WarpSE.ngc
+++ b/cpld/XC95144XL/WarpSE.ngc
--- a/cpld/XC95144XL/WarpSE.ngd
+++ b/cpld/XC95144XL/WarpSE.ngd
--- a/cpld/XC95144XL/WarpSE.ngr
+++ b/cpld/XC95144XL/WarpSE.ngr
--- a/cpld/XC95144XL/WarpSE.pad
+++ b/cpld/XC95144XL/WarpSE.pad
@ -1,7 +1,7 @@
 Release 8.1i - Fit P.20131013
 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved

-10-12-2024  2:16AM
+10-12-2024  2:18AM

 NOTE: This file is designed to be imported into a spreadsheet program
 such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
--- a/cpld/XC95144XL/WarpSE.rpt
+++ b/cpld/XC95144XL/WarpSE.rpt
@ -1,7 +1,7 @@
 
 cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
-Design Name: WarpSE                              Date: 10-12-2024,  2:16AM
+Design Name: WarpSE                              Date: 10-12-2024,  2:18AM
 Device Used: XC95144XL-10-TQ100
 Fitting Status: Successful

@ -982,24 +982,24 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
 RnW_IOB_OE <= NOT nAoutOE;

 FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
-SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(1) AND set/SetWRr));
+SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));

 FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
-SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(7) AND set/SetWRr));
+SlowIACK_D <= ((nPOR AND NOT SlowIACK AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(7) AND set/SetWRr));

 FDCPE_SlowIWM: FDCPE port map (SlowIWM,SlowIWM_D,FCLK,'0','0');
 SlowIWM_D <= ((nPOR AND NOT SlowIWM AND NOT set/SetWRr)
 	OR (nPOR AND NOT A_FSB(5) AND set/SetWRr));

 FDCPE_SlowSCC: FDCPE port map (SlowSCC,SlowSCC_D,FCLK,'0','0');
-SlowSCC_D <= ((nPOR AND SlowSCC AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(4) AND set/SetWRr));
+SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));

 FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
-SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(3) AND set/SetWRr));
+SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));

 FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
 SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
--- a/cpld/XC95144XL/WarpSE.syr
+++ b/cpld/XC95144XL/WarpSE.syr
@ -446,15 +446,15 @@ Design Statistics
 # IOs                              : 80

 Cell Usage :
-# BELS                             : 687
-#      AND2                        : 213
+# BELS                             : 691
+#      AND2                        : 209
 #      AND3                        : 26
 #      AND4                        : 13
 #      AND5                        : 3
 #      AND8                        : 2
 #      GND                         : 7
-#      INV                         : 274
-#      OR2                         : 112
+#      INV                         : 278
+#      OR2                         : 116
 #      OR3                         : 10
 #      OR4                         : 4
 #      OR5                         : 1
@ -478,7 +478,7 @@ Total CPU time to Xst completion: 5.00 secs
 
 --> 

-Total memory usage is 262688 kilobytes
+Total memory usage is 263520 kilobytes

 Number of errors   :    0 (   0 filtered)
 Number of warnings :    3 (   0 filtered)
--- a/cpld/XC95144XL/WarpSE.vm6
+++ b/cpld/XC95144XL/WarpSE.vm6
--- a/cpld/XC95144XL/WarpSE.xml
+++ b/cpld/XC95144XL/WarpSE.xml
--- a/cpld/XC95144XL/WarpSE_html/fit/ascii.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/ascii.htm
@ -3,7 +3,7 @@
 
 cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
-Design Name: WarpSE                              Date: 10-12-2024,  2:16AM
+Design Name: WarpSE                              Date: 10-12-2024,  2:18AM
 Device Used: XC95144XL-10-TQ100
 Fitting Status: Successful

@ -984,24 +984,24 @@ RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
 RnW_IOB_OE <= NOT nAoutOE;

 FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
-SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(1) AND set/SetWRr));
+SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));

 FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
-SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(7) AND set/SetWRr));
+SlowIACK_D <= ((nPOR AND NOT SlowIACK AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(7) AND set/SetWRr));

 FDCPE_SlowIWM: FDCPE port map (SlowIWM,SlowIWM_D,FCLK,'0','0');
 SlowIWM_D <= ((nPOR AND NOT SlowIWM AND NOT set/SetWRr)
 	OR (nPOR AND NOT A_FSB(5) AND set/SetWRr));

 FDCPE_SlowSCC: FDCPE port map (SlowSCC,SlowSCC_D,FCLK,'0','0');
-SlowSCC_D <= ((nPOR AND SlowSCC AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(4) AND set/SetWRr));
+SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));

 FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
-SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
-	OR (nPOR AND A_FSB(3) AND set/SetWRr));
+SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
+	OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));

 FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
 SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
--- a/cpld/XC95144XL/WarpSE_html/fit/defeqns.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/defeqns.htm
@ -218,24 +218,24 @@ FTCPE_RnW_IOB: FTCPE port map (RnW_IOB_I,RnW_IOB_T,NOT C16M,'0','0');
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RnW_IOB_OE <= NOT nAoutOE;
 </td></tr><tr><td>
 FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND A_FSB(1) AND set/SetWRr));
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowClockGate_D <= ((nPOR AND NOT SlowClockGate AND NOT set/SetWRr)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(1) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND A_FSB(7) AND set/SetWRr));
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowIACK_D <= ((nPOR AND NOT SlowIACK AND NOT set/SetWRr)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(7) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowIWM: FDCPE port map (SlowIWM,SlowIWM_D,FCLK,'0','0');
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowIWM_D <= ((nPOR AND NOT SlowIWM AND NOT set/SetWRr)
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(5) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowSCC: FDCPE port map (SlowSCC,SlowSCC_D,FCLK,'0','0');
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSCC_D <= ((nPOR AND SlowSCC AND NOT set/SetWRr)
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND A_FSB(4) AND set/SetWRr));
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSCC_D <= ((nPOR AND NOT SlowSCC AND NOT set/SetWRr)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(4) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSCSI_D <= ((nPOR AND SlowSCSI AND NOT set/SetWRr)
-<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND A_FSB(3) AND set/SetWRr));
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
+<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
 </td></tr><tr><td>
 FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
 <br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
--- a/cpld/XC95144XL/WarpSE_html/fit/eqns.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/eqns.htm
@ -4,7 +4,7 @@
      var design = "WarpSE";
      var device = "XC95144XL";
      signals = new Array("ALE0M","ALE0S","ASrf","BACTr","GA22_SPECSIG","GA23_SPECSIG","IOACT","IODONE","IOL0","IONPReady","IOREQ","IORW","IOU0","MCKE","QoSEN","RA0_SPECSIG","RA10_SPECSIG","RA11_SPECSIG","RA1_SPECSIG","RA2_SPECSIG","RA3_SPECSIG","RA4_SPECSIG","RA5_SPECSIG","RA6_SPECSIG","RA7_SPECSIG","RA8_SPECSIG","RA9_SPECSIG","RAMReady","RefReq","RefUrg","RnW_IOB","SlowClockGate","SlowIACK","SlowIWM","SlowSCC","SlowSCSI","SlowSnd","SlowTimeout0_SPECSIG","SlowTimeout1_SPECSIG","SlowTimeout2_SPECSIG","SlowTimeout3_SPECSIG","SlowVIA","cntC8Mr0_SPECSIG","cntC8Mr1_SPECSIG","cntC8Mr2_SPECSIG","cntC8Mr3_SPECSIG","cntEr0_SPECSIG","cntEr1_SPECSIG","cntIS0_SPECSIG","cntIS1_SPECSIG","cntLTimer0_SPECSIG","cntLTimer10_SPECSIG","cntLTimer11_SPECSIG","cntLTimer1_SPECSIG","cntLTimer2_SPECSIG","cntLTimer3_SPECSIG","cntLTimer4_SPECSIG","cntLTimer5_SPECSIG","cntLTimer6_SPECSIG","cntLTimer7_SPECSIG","cntLTimer8_SPECSIG","cntLTimer9_SPECSIG","cntLTimerTick_SPECSIG","cntQS0_SPECSIG","cntQS1_SPECSIG","cntQS2_SPECSIG","cntQS3_SPECSIG","cntQoSCSr_SPECSIG","cntTimer0_SPECSIG","cntTimer1_SPECSIG","cntTimer2_SPECSIG","cntTimer3_SPECSIG","cntTimerTick_SPECSIG","csOverlay_SPECSIG","iobmC8Mr_SPECSIG","iobmDoutOE_SPECSIG","iobmES0_SPECSIG","iobmES1_SPECSIG","iobmES2_SPECSIG","iobmES3_SPECSIG","iobmEr_SPECSIG","iobmIOREQr_SPECSIG","iobmIOS_FSM_FFd1_SPECSIG","iobmIOS_FSM_FFd2_SPECSIG","iobmIOS_FSM_FFd3_SPECSIG","iobmIOS_FSM_FFd4_SPECSIG","iobmIOS_FSM_FFd5_SPECSIG","iobmIOS_FSM_FFd6_SPECSIG","iobmIOS_FSM_FFd7_SPECSIG","iobmVPAr_SPECSIG","iobsClear1_SPECSIG","iobsIOACTr_SPECSIG","iobsIODONEr0_SPECSIG","iobsIODONEr1_SPECSIG","iobsIODONErf_SPECSIG","iobsIOL1_SPECSIG","iobsIORW1_SPECSIG","iobsIOU1_SPECSIG","iobsLoad1_SPECSIG","iobsSent_SPECSIG","iobsTS_FSM_FFd1_SPECSIG","iobsTS_FSM_FFd2_SPECSIG","nADoutLE0","nADoutLE1","nAS_IOB","nAoutOE","nBERR_FSB","nBR_IOB","nBR_IOBout","nCAS","nDTACK_FSB","nDinLE","nDinOE","nDoutOE","nLDS_IOB","nOE","nPOR","nRAMLWE","nRAMUWE","nRAS","nRES","nRESout","nROMOE","nROMWE","nUDS_IOB","nVMA_IOB","nVPA_FSB","ramCASEndEN_SPECSIG","ramRASEL_SPECSIG","ramRASEN_SPECSIG","ramRASrf_SPECSIG","ramRS0_SPECSIG","ramRS1_SPECSIG","ramRS2_SPECSIG","ramRefCAS_SPECSIG","ramRefDone_SPECSIG","setSetWRr_SPECSIG");
-      sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
+      sigNegs = new Array("ON","OFF","OFF","ON","OFF","OFF","ON","OFF","OFF","ON","ON","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","ON","ON","ON","ON","ON","ON","ON","ON","ON","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","ON","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","OFF","ON","OFF","ON","OFF","ON","OFF","OFF","OFF","ON","OFF","ON","ON","ON","OFF","ON","OFF","ON","ON","ON","OFF","OFF","ON","ON","OFF","OFF","ON","OFF","OFF","OFF","OFF","OFF","ON","OFF","OFF","OFF","OFF");
      sigTypes = new Array("D","D","D","D","","","D","D","D","D","D","D","D","D","D","","","","","","","","","","","","","D","D","D","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","T","T","T","T","T","T","T","T","T","T","T","T","D","D","D","T","D","D","T","T","T","T","D","T","D","D","T","D","T","T","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","D","T","D","D","T","D","D","","D","D","D","T","","D","D","D","D","","","D","D","T","","","","","D","","","D","T","D","D","D","D","D","D","T","T","D","D","D");

      
@ -276,25 +276,25 @@
          
            pterms["FB1_12_2"]=new Array("nPOR","/A_FSB2_SPECSIG","setSetWRr_SPECSIG");
          
-            pterms["FB1_13_1"]=new Array("nPOR","SlowSCSI","/setSetWRr_SPECSIG");
+            pterms["FB1_13_1"]=new Array("nPOR","/SlowSCSI","/setSetWRr_SPECSIG");
          
-            pterms["FB1_13_2"]=new Array("nPOR","A_FSB3_SPECSIG","setSetWRr_SPECSIG");
+            pterms["FB1_13_2"]=new Array("nPOR","/A_FSB3_SPECSIG","setSetWRr_SPECSIG");
          
-            pterms["FB1_14_1"]=new Array("nPOR","SlowSCC","/setSetWRr_SPECSIG");
+            pterms["FB1_14_1"]=new Array("nPOR","/SlowSCC","/setSetWRr_SPECSIG");
          
-            pterms["FB1_14_2"]=new Array("nPOR","A_FSB4_SPECSIG","setSetWRr_SPECSIG");
+            pterms["FB1_14_2"]=new Array("nPOR","/A_FSB4_SPECSIG","setSetWRr_SPECSIG");
          
            pterms["FB1_15_1"]=new Array("nPOR","/SlowIWM","/setSetWRr_SPECSIG");
          
            pterms["FB1_15_2"]=new Array("nPOR","/A_FSB5_SPECSIG","setSetWRr_SPECSIG");
          
-            pterms["FB1_16_1"]=new Array("nPOR","SlowIACK","/setSetWRr_SPECSIG");
+            pterms["FB1_16_1"]=new Array("nPOR","/SlowIACK","/setSetWRr_SPECSIG");
          
-            pterms["FB1_16_2"]=new Array("nPOR","A_FSB7_SPECSIG","setSetWRr_SPECSIG");
+            pterms["FB1_16_2"]=new Array("nPOR","/A_FSB7_SPECSIG","setSetWRr_SPECSIG");
          
-            pterms["FB1_17_1"]=new Array("nPOR","SlowClockGate","/setSetWRr_SPECSIG");
+            pterms["FB1_17_1"]=new Array("nPOR","/SlowClockGate","/setSetWRr_SPECSIG");
          
-            pterms["FB1_17_2"]=new Array("nPOR","A_FSB1_SPECSIG","setSetWRr_SPECSIG");
+            pterms["FB1_17_2"]=new Array("nPOR","/A_FSB1_SPECSIG","setSetWRr_SPECSIG");
          
            pterms["FB1_18_1"]=new Array("/nPOR","/cntC8Mr1_SPECSIG","cntC8Mr0_SPECSIG");
          
--- a/cpld/XC95144XL/WarpSE_html/fit/summary.htm
+++ b/cpld/XC95144XL/WarpSE_html/fit/summary.htm
@ -30,7 +30,7 @@
 <tr>
 <td width="40%"> <b>Date</b>
 </td>
-<td width="60%"> 10-12-2024,  2:16AM</td>
+<td width="60%"> 10-12-2024,  2:18AM</td>
 </tr>
 </table></span><br><span id="sumres" class="pgRef"><h5 align="center">RESOURCES SUMMARY</h5>
 <table align="center" width="90%" border="1" cellspacing="0" cellpadding="0">
--- a/cpld/XC95144XL/WarpSE_html/tim/timing_report.htm
+++ b/cpld/XC95144XL/WarpSE_html/tim/timing_report.htm
@ -27,7 +27,7 @@
  <TD WIDTH="65%" CLASS="cpldta_text_normal"><A HREF="Javascript:popWin('http://www.xilinx.com/literature/index.htm','800','800','test');">XC95144XL</A>, -10 (3.0)</TD>
 </TR>
 <TR>
-  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD>  <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 02:16:35 2024
+  <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD>  <TD WIDTH="65%" CLASS="cpldta_text_normal">Sat Oct 12 02:18:55 2024
 </TD>
 </TR>
 <TR>
@ -3882,7 +3882,7 @@ function AUTO_TS_F2P_BACTr_Q_to_nDinOE() {
 <SPAN CLASS="cpldta_text_normal">809</SPAN>
 <BR><SPAN CLASS="cpldta_text_normal_bold"><B>Number of Timing errors:</B></SPAN> 
 <SPAN CLASS="cpldta_text_normal">809</SPAN>
-<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 02:16:35 2024
+<BR><SPAN CLASS="cpldta_text_normal_bold"><B>Analysis Completed:</B></SPAN> <SPAN CLASS="cpldta_text_normal">Sat Oct 12 02:18:55 2024
 </SPAN>
 <HR>
 </HTML>
--- a/cpld/XC95144XL/WarpSE_ngdbuild.xrpt
+++ b/cpld/XC95144XL/WarpSE_ngdbuild.xrpt
@ -5,7 +5,7 @@
    The structure and the elements are likely to change over the next few releases.
    This means code written to parse this file will need to be revisited each subsequent release.-->

-  <application stringID="NgdBuild" timeStamp="Sat Oct 12 02:16:13 2024">
+  <application stringID="NgdBuild" timeStamp="Sat Oct 12 02:18:34 2024">
    <section stringID="User_Env">
      <table stringID="User_EnvVar">
        <column stringID="variable"/>
@ -66,7 +66,7 @@
        <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
      </section>
      <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
-        <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="213"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="209"/>
        <item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
        <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
        <item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
@ -76,24 +76,24 @@
        <item dataType="int" stringID="NGDBUILD_NUM_FDP" value="4"/>
        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="7"/>
        <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
-        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="274"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="278"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
-        <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="116"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
        <item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="21"/>
      </section>
      <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
-        <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="213"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="209"/>
        <item dataType="int" stringID="NGDBUILD_NUM_AND3" value="26"/>
        <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
        <item dataType="int" stringID="NGDBUILD_NUM_AND5" value="3"/>
        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="72"/>
        <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="43"/>
-        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="274"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="278"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="31"/>
-        <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="116"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
        <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
--- a/cpld/XC95144XL/WarpSE_pad.csv
+++ b/cpld/XC95144XL/WarpSE_pad.csv
@ -1,7 +1,7 @@
 Release 8.1i - Fit P.20131013
 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved

-10-12-2024  2:16AM
+10-12-2024  2:18AM

 NOTE: This file is designed to be imported into a spreadsheet program
 such as Microsoft Excel for viewing, printing and sorting. The comma ','
--- a/cpld/XC95144XL/WarpSE_summary.html
+++ b/cpld/XC95144XL/WarpSE_summary.html
@ -2,7 +2,7 @@
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 02:16:42)</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (10/12/2024 - 02:19:07)</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
 <TD>WarpSE.xise</TD>
@ -65,9 +65,9 @@ System Settings</A>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:16:08 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:16:14 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 02:16:27 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:18:28 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Oct 12 02:18:34 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\WarpSE.rpt'>CPLD Fitter Report (Text)</A></TD><TD>Current</TD><TD>Sat Oct 12 02:18:48 2024</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Warning'>8 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL\_xmsgs/cpldfit.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
 <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 </TABLE>
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
@ -77,5 +77,5 @@ System Settings</A>
 </TABLE>


-<br><center><b>Date Generated:</b> 10/12/2024 - 02:16:42</center>
+<br><center><b>Date Generated:</b> 10/12/2024 - 02:19:07</center>
 </BODY></HTML>
--- a/cpld/XC95144XL/WarpSE_xst.xrpt
+++ b/cpld/XC95144XL/WarpSE_xst.xrpt
@ -5,7 +5,7 @@
    The structure and the elements are likely to change over the next few releases.
    This means code written to parse this file will need to be revisited each subsequent release.-->

-  <application stringID="Xst" timeStamp="Sat Oct 12 02:16:03 2024">
+  <application stringID="Xst" timeStamp="Sat Oct 12 02:18:23 2024">
    <section stringID="User_Env">
      <table stringID="User_EnvVar">
        <column stringID="variable"/>
@ -118,13 +118,13 @@
        <item stringID="XST_IOS" value="80"/>
      </section>
      <section stringID="XST_CELL_USAGE">
-        <item dataType="int" stringID="XST_BELS" value="687">
-          <item dataType="int" stringID="XST_AND2" value="213"/>
+        <item dataType="int" stringID="XST_BELS" value="691">
+          <item dataType="int" stringID="XST_AND2" value="209"/>
          <item dataType="int" stringID="XST_AND3" value="26"/>
          <item dataType="int" stringID="XST_AND4" value="13"/>
          <item dataType="int" stringID="XST_GND" value="7"/>
-          <item dataType="int" stringID="XST_INV" value="274"/>
-          <item dataType="int" stringID="XST_OR2" value="112"/>
+          <item dataType="int" stringID="XST_INV" value="278"/>
+          <item dataType="int" stringID="XST_OR2" value="116"/>
          <item dataType="int" stringID="XST_XOR2" value="21"/>
        </item>
        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="113">
--- a/cpld/XC95144XL/_ngo/netlist.lst
+++ b/cpld/XC95144XL/_ngo/netlist.lst
@ -1,2 +1,2 @@
-C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728713768
+C:\Users\GWolf\Documents\GitHub\WarpSE\cpld\XC95144XL\WarpSE.ngc 1728713908
 OK
--- a/cpld/XC95144XL/iseconfig/WarpSE.projectmgr
+++ b/cpld/XC95144XL/iseconfig/WarpSE.projectmgr
@ -63,13 +63,13 @@
         <ClosedNode>User Constraints</ClosedNode>
      </ClosedNodes>
      <SelectedItems>
-         <SelectedItem>Manage Configuration Project (iMPACT)</SelectedItem>
+         <SelectedItem>Generate Programming File</SelectedItem>
      </SelectedItems>
      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>Manage Configuration Project (iMPACT)</CurrentItem>
+      <CurrentItem>Generate Programming File</CurrentItem>
   </ItemView>
   <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
   <CurrentView>Implementation</CurrentView>
--- a/cpld/XC95144XL/iseconfig/WarpSE.xreport
+++ b/cpld/XC95144XL/iseconfig/WarpSE.xreport
@ -1,7 +1,7 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
 <header>
-  <DateModified>2024-10-12T02:15:59</DateModified>
+  <DateModified>2024-10-12T02:18:21</DateModified>
  <ModuleName>WarpSE</ModuleName>
  <SummaryTimeStamp>2024-10-09T06:57:43</SummaryTimeStamp>
  <SavedFilePath>C:/Users/GWolf/Documents/GitHub/WarpSE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
--- a/cpld/XC95144XL/webtalk_pn.xml
+++ b/cpld/XC95144XL/webtalk_pn.xml
@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pn" timeStamp="Sat Oct 12 02:16:02 2024">
+<application name="pn" timeStamp="Sat Oct 12 02:18:22 2024">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="B70E14F6F6B943E9BF9FD5113EA04D70" type="project"/>
 <property name="ProjectIteration" value="0" type="project"/>
--- a/cpld/XC95144XL/xlnx_auto_0_xdb/cst.xbcd
+++ b/cpld/XC95144XL/xlnx_auto_0_xdb/cst.xbcd
--- a/cpld/XC95144XL/xst/work/hdllib.ref
+++ b/cpld/XC95144XL/xst/work/hdllib.ref
@ -1,8 +1,8 @@
-MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728713763
-MO CS NULL ../CS.v vlg22/_c_s.bin 1728713763
-MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728713763
-MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728713763
-MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728713763
-MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728713763
-MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728713763
-MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728713763
+MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1728713903
+MO CS NULL ../CS.v vlg22/_c_s.bin 1728713903
+MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1728713903
+MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1728713903
+MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1728713903
+MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1728713903
+MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1728713903
+MO SET NULL ../SET.v vlg48/_s_e_t.bin 1728713903
--- a/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin
+++ b/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin
--- a/cpld/XC95144XL/xst/work/vlg22/_c_s.bin
+++ b/cpld/XC95144XL/xst/work/vlg22/_c_s.bin
--- a/cpld/XC95144XL/xst/work/vlg37/_f_s_b.bin
+++ b/cpld/XC95144XL/xst/work/vlg37/_f_s_b.bin
--- a/cpld/XC95144XL/xst/work/vlg48/_s_e_t.bin
+++ b/cpld/XC95144XL/xst/work/vlg48/_s_e_t.bin
--- a/cpld/XC95144XL/xst/work/vlg52/_warp_s_e.bin
+++ b/cpld/XC95144XL/xst/work/vlg52/_warp_s_e.bin
--- a/cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin
+++ b/cpld/XC95144XL/xst/work/vlg65/_c_n_t.bin
--- a/cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin
+++ b/cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin
--- a/cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin
+++ b/cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin