From a2fc4dc4debf4cc8474d94c5045dd981bc527333 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Mon, 20 Mar 2023 01:13:11 -0400 Subject: [PATCH] Better --- cpld/CNT.v | 19 ++++---- cpld/FSB.v | 23 ++-------- cpld/IOBM.v | 4 +- cpld/IOBS.v | 6 +-- cpld/WarpSE.v | 20 ++++----- cpld/XC95144XL/WarpSE.cmd_log | 8 ++++ cpld/XC95144XL/WarpSE.gise | 2 +- cpld/XC95144XL/WarpSE.syr | 47 ++++++++++--------- cpld/XC95144XL/WarpSE_envsettings.html | 52 +++++++++++----------- cpld/XC95144XL/WarpSE_summary.html | 18 ++++---- cpld/XC95144XL/WarpSE_xst.xrpt | 20 ++++----- cpld/XC95144XL/_xmsgs/pn_parser.xmsgs | 14 +----- cpld/XC95144XL/_xmsgs/xst.xmsgs | 43 +++++++++++++----- cpld/XC95144XL/iseconfig/WarpSE.projectmgr | 10 ++--- cpld/XC95144XL/iseconfig/WarpSE.xreport | 6 +-- cpld/XC95144XL/webtalk_pn.xml | 4 +- 16 files changed, 152 insertions(+), 144 deletions(-) diff --git a/cpld/CNT.v b/cpld/CNT.v index ae9a092..984b403 100644 --- a/cpld/CNT.v +++ b/cpld/CNT.v @@ -49,8 +49,8 @@ module CNT( */ assign RefUrgent = Timer[6]; always @(posedge C8M) begin - if (Timer[3]) RefREQ <= 1; - else if (TimerTC) RefREQ <= 0; + if (Timer[3]) RefReq <= 1; + else if (TimerTC) RefReq <= 0; end /* LBACTr - LBACT synchronized to C16M clock domain */ @@ -59,7 +59,6 @@ module CNT( /* BERR generation in C8M clock domain */ reg BERRArm = 0; - reg BERRTimeout = 0; always @(posedge C8M) begin if (LBACTr && TimerTC) begin BERRArm <= 1; @@ -72,17 +71,21 @@ module CNT( /* Long timer counts from 0 to 16384 -- 16385 states == 202.888 ms */ reg [14:0] LTimer; // Long timer - wire LTimerTC <= LTimer[14]; + wire LTimerTC = LTimer[14]; always @(posedge C8M) begin if (LTimerTC) LTimer <= 0; else LTimer <= LTimer+1; end - + + /* IPL2 synchronizer */ + reg IPL2r; + always @(posedge C8M) IPL2r <= !nIPL2; + /* Startup sequence control */ reg [1:0] PORS = 0; reg Disable = 0; - reg BR_IOB = 0; assign nBR_IOB <= !BR_IOB; - assign nAoutOE <= !AoutOE; + reg BR_IOB = 0; assign nBR_IOB = !BR_IOB; + assign nAoutOE = !AoutOE; always @(posedge C8M) begin case (PORS) 0: begin @@ -93,7 +96,7 @@ module CNT( end 1: begin AoutOE <= 0; // Tristate PDS address and control nRESout <= 0; // Hold reset low - Disable <= Disable | !nIPL2; // No need to synchronize /IPL2 + Disable <= Disable | IPL2r; if (!IPL2r && LTimerTC) begin BR_IOB <= !Disable; PORS <= 2; diff --git a/cpld/FSB.v b/cpld/FSB.v index 48df912..f2441dc 100644 --- a/cpld/FSB.v +++ b/cpld/FSB.v @@ -5,8 +5,8 @@ module FSB( output BACT, output LBACT, /* Ready inputs */ input Ready0, input Ready1, input Ready2, - /* BERR inputs */ - input BERR0, input BERR1, + /* BERR input from IOB slave port */ + input IOBS_BERR, /* Interrupt acknowledge select */ input IACS); @@ -17,7 +17,6 @@ module FSB( /* LBACT - "Long BACT" */ reg [1:0] BACTCnt = 0; - reg LBACT; always @(posedge FCLK) begin if (!BACT) begin BACTCnt <= 0; @@ -46,21 +45,7 @@ module FSB( end /* BERR generation */ - reg BERR0r, BERR1r; - always @(posedge FCLK) BERR0r <= BERR0; - always @(posedge FCLK) BERR1r <= BERR1; - reg BERREN = 0; - reg BERRCNT = 0; - always @(posedge FCLK) begin - if (~BACT) begin - BERREN <= 0; - BERRCNT <= 0; - end else begin - BERRCNT <= BERRCNT+1; - BERREN <= BERRCNT==3'b111; - end - end - assign nBERR = ~(~nAS && BERREN && (BERR0r || BERR1r)); + assign nBERR = ~(~nAS && IOBS_BERR); /* DTACK/VPA control */ reg VPA; @@ -69,7 +54,7 @@ module FSB( if (~BACT) begin nDTACK <= 1; VPA <= 0; - end else if (Ready && ~BERR) begin + end else if (Ready) begin nDTACK <= IACS; VPA <= IACS; end diff --git a/cpld/IOBM.v b/cpld/IOBM.v index b17a272..7910548 100644 --- a/cpld/IOBM.v +++ b/cpld/IOBM.v @@ -107,8 +107,8 @@ module IOBM( end /* PDS address and data latch control */ - always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end - reg DoutOE = 0; assign nDoutOE <= !(AoutOE && DoutOE); + always @(negedge C16M) begin nDinLE = IOS==4 || IOS==5; end + reg DoutOE = 0; assign nDoutOE = !(AoutOE && DoutOE); always @(posedge C16M) begin DoutOE <= IOWE && (IOS==1 || IOS==2 || IOS==3 || IOS==4 || IOS==5 || IOS==6); diff --git a/cpld/IOBS.v b/cpld/IOBS.v index 1f04d72..0fdf80f 100644 --- a/cpld/IOBS.v +++ b/cpld/IOBS.v @@ -4,7 +4,7 @@ module IOBS( /* AS cycle detection */ input BACT, /* Select and ready signals */ - input IOCS, input IOPWCS, output Ready, output reg BERR, + input IOCS, input IOPWCS, output IOBS_Ready, output reg IOBS_BERR, /* Read data OE control */ output nDinOE, /* IOB Master Controller Interface */ @@ -109,9 +109,9 @@ module IOBS( BERR <= 0; end else if (Once && (PS==0 || PS==1) && ~IOACTr && IOPWReady) begin IOReady <= ~IOBERR; - BERR <= IOBERR; + IOBS_BERR <= IOBERR; end end - assign Ready = ~IOCS || IOReady || (IOPWCS && IOPWReady); + assign IOBS_Ready = ~IOCS || IOReady || (IOPWCS && IOPWReady); endmodule diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v index 75b89bb..b61fc87 100644 --- a/cpld/WarpSE.v +++ b/cpld/WarpSE.v @@ -80,7 +80,7 @@ module WarpSE( RA[11:0], nRAS, nCAS, nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE); - wire Ready_IOBS, BERR_IOBS; + wire IOBS_Ready, IOBS_BERR; wire IOREQ, IOACT, IOBERR; wire ALE0S, ALE0M, ALE1; assign nADoutLE0 = ~(ALE0S || ALE0M); @@ -92,7 +92,7 @@ module WarpSE( /* AS cycle detection, FSB BERR */ BACT, /* Select and ready signals */ - IOCS, IOPWCS, Ready_IOBS, BERR_IOBS, + IOCS, IOPWCS, IOBS_Ready, IOBS_BERR, /* Read data OE control */ nDinOE, /* IOB Master Controller Interface */ @@ -102,11 +102,12 @@ module WarpSE( /* FIFO secondary level control */ ALE1); + wire AoutOE; wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout; - assign nAS_IOB = nAoutOE ? 1'bZ : nAS_IOBout; - assign nLDS_IOB = nAoutOE ? 1'bZ : nLDS_IOBout; - assign nUDS_IOB = nAoutOE ? 1'bZ : nUDS_IOBout; - assign nVMA_IOB = nAoutOE ? 1'bZ : nVMA_IOBout; + assign nAS_IOB = AoutOE ? 1'bZ : nAS_IOBout; + assign nLDS_IOB = AoutOE ? 1'bZ : nLDS_IOBout; + assign nUDS_IOB = AoutOE ? 1'bZ : nUDS_IOBout; + assign nVMA_IOB = AoutOE ? 1'bZ : nVMA_IOBout; IOBM iobm( /* PDS interface */ CLK2X_IOB, CLK_IOB, E_IOB, @@ -119,7 +120,6 @@ module WarpSE( IOREQ, IOL0, IOU0, IORW0); wire BERRTimeout; - wire AoutOE; CNT cnt( /* C8M clock */ C8M, @@ -142,9 +142,9 @@ module WarpSE( /* AS cycle detection */ BACT, LBACT, /* Ready and IA inputs */ - Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady), - /* BERR inputs */ - (~IOCS && BERRTimeout), BERR_IOBS, + Ready_RAM, IOBS_Ready, (!SndRAMCSWR || QoSReady), + /* IOB slabe port BERR input */ + IOBS_BERR, /* Interrupt acknowledge select */ IACS); diff --git a/cpld/XC95144XL/WarpSE.cmd_log b/cpld/XC95144XL/WarpSE.cmd_log index b3ac8cd..de0c7a6 100644 --- a/cpld/XC95144XL/WarpSE.cmd_log +++ b/cpld/XC95144XL/WarpSE.cmd_log @@ -25,3 +25,11 @@ taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_rep xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr" diff --git a/cpld/XC95144XL/WarpSE.gise b/cpld/XC95144XL/WarpSE.gise index b491f79..76f2cd9 100644 --- a/cpld/XC95144XL/WarpSE.gise +++ b/cpld/XC95144XL/WarpSE.gise @@ -78,7 +78,7 @@ - + diff --git a/cpld/XC95144XL/WarpSE.syr b/cpld/XC95144XL/WarpSE.syr index 4d5b97b..5b9587b 100644 --- a/cpld/XC95144XL/WarpSE.syr +++ b/cpld/XC95144XL/WarpSE.syr @@ -1,16 +1,16 @@ -Release 14.7 - xst P.20131013 (nt) +Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp -Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.97 secs +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst -Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.98 secs +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.09 secs --> Reading design: WarpSE.prj @@ -76,36 +76,43 @@ wysiwyg : NO * HDL Compilation * ========================================================================= Compiling verilog file "../RAM.v" in library work -ERROR:HDLCompilers:28 - "../RAM.v" line 63 'BACTr' has not been declared -ERROR:HDLCompilers:26 - "../RAM.v" line 69 unexpected token: ';' -ERROR:HDLCompilers:26 - "../RAM.v" line 75 unexpected token: 'begin' -ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting ';', found ')' -ERROR:HDLCompilers:26 - "../RAM.v" line 76 unexpected token: '<=' -Module compiled -ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting 'endmodule', found '0' +ERROR:HDLCompilers:28 - "../RAM.v" line 38 'BACTr' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 96 'RefFromRS0Next' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 100 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 101 'RefFromRS0Pre' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 107 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 113 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 118 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 124 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 132 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 139 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 146 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 153 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 160 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 167 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 176 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 184 'RAMDIS1' has not been declared +ERROR:HDLCompilers:28 - "../RAM.v" line 190 'RAMDIS1' has not been declared Compiling verilog file "../IOBS.v" in library work +Module compiled Compiling verilog file "../IOBM.v" in library work Module compiled Compiling verilog file "../FSB.v" in library work Module compiled -ERROR:HDLCompilers:28 - "../FSB.v" line 59 'BERR' has not been declared +ERROR:HDLCompilers:28 - "../FSB.v" line 71 'BERR' has not been declared Compiling verilog file "../CS.v" in library work Module compiled Compiling verilog file "../CNT.v" in library work Module compiled -ERROR:HDLCompilers:28 - "../CNT.v" line 29 'RefREQ' has not been declared -ERROR:HDLCompilers:28 - "../CNT.v" line 30 'RefREQ' has not been declared -ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting ';', found '=' -Module compiled -ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting 'endmodule', found '0' Compiling verilog file "../WarpSE.v" in library work +Module compiled Module compiled Analysis of file <"WarpSE.prj"> failed. --> -Total memory usage is 190552 kilobytes +Total memory usage is 232068 kilobytes -Number of errors : 11 ( 0 filtered) +Number of errors : 18 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) diff --git a/cpld/XC95144XL/WarpSE_envsettings.html b/cpld/XC95144XL/WarpSE_envsettings.html index abdd8a2..a438b05 100644 --- a/cpld/XC95144XL/WarpSE_envsettings.html +++ b/cpld/XC95144XL/WarpSE_envsettings.html @@ -14,32 +14,32 @@ PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC -.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC +.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC Path C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt;
C:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\altera\13.0sp1\modelsim_ase\win32aloem -C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt;
C:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\altera\13.0sp1\modelsim_ase\win32aloem +C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt;
C:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\altera\13.0sp1\modelsim_ase\win32aloem XILINX C:\Xilinx\14.7\ISE_DS\ISE\ -C:\Xilinx\14.7\ISE_DS\ISE\ +C:\Xilinx\14.7\ISE_DS\ISE\ XILINX_DSP C:\Xilinx\14.7\ISE_DS\ISE -C:\Xilinx\14.7\ISE_DS\ISE +C:\Xilinx\14.7\ISE_DS\ISE XILINX_EDK C:\Xilinx\14.7\ISE_DS\EDK -C:\Xilinx\14.7\ISE_DS\EDK +C:\Xilinx\14.7\ISE_DS\EDK XILINX_PLANAHEAD C:\Xilinx\14.7\ISE_DS\PlanAhead -C:\Xilinx\14.7\ISE_DS\PlanAhead +C:\Xilinx\14.7\ISE_DS\PlanAhead @@ -186,28 +186,28 @@ Default Value --intstyle -  -ise -None +-intstyle +  +ise +None --dd -  -_ngo -None +-dd +  +_ngo +None --p -  -xc95144xl-TQ100-10 -None +-p +  +xc95144xl-TQ100-10 +None --uc -  -Z:/Warp-SE/cpld/WarpSE-XC95144XL.ucf -None +-uc +  +Z:/Warp-SE/cpld/WarpSE-XC95144XL.ucf +None @@ -223,22 +223,22 @@ CPU Architecture/Speed QEMU Virtual CPU version 2.5+/1000 MHz -QEMU Virtual CPU version 2.5+/1000 MHz +QEMU Virtual CPU version 2.5+/1000 MHz Host ZaneMacWin7 -ZaneMacWin7 +ZaneMacWin7 OS Name Microsoft Windows 7 , 32-bit -Microsoft Windows 7 , 32-bit +Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601) -Service Pack 1 (build 7601) +Service Pack 1 (build 7601) \ No newline at end of file diff --git a/cpld/XC95144XL/WarpSE_summary.html b/cpld/XC95144XL/WarpSE_summary.html index 8ca13b1..296595c 100644 --- a/cpld/XC95144XL/WarpSE_summary.html +++ b/cpld/XC95144XL/WarpSE_summary.html @@ -2,18 +2,18 @@ - + - + - + @@ -21,7 +21,7 @@ +11 Errors (11 new) @@ -44,7 +44,7 @@ @@ -66,9 +66,9 @@ System Settings - - - + + +
WarpSE Project Status (09/03/2022 - 16:22:34)
WarpSE Project Status
Project File: WarpSE.xise Parser Errors:X 2 Errors No Errors
Module Name: WarpSE Implementation State:Synthesized (Failed)Translated
Target Device:
  • Errors:
 X -11 Errors (11 new)
Product Version:ISE 14.7
Environment: - + System Settings
  • Final Timing Score:
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Sep 3 16:22:35 2022X 11 Errors (11 new)00
Translation ReportOut of DateMon Mar 28 09:45:45 2022000
CPLD Fitter Report (Text)Out of DateMon Mar 28 09:46:19 202202 Warnings (1 new)3 Infos (3 new)
Synthesis ReportCurrentSun Mar 19 19:23:24 2023X 11 Errors (11 new)00
Translation ReportCurrentSun Mar 19 19:23:24 2023000
CPLD Fitter Report (Text)CurrentSun Mar 19 19:23:24 202302 Warnings (1 new)3 Infos (3 new)
Power Report     
 
@@ -78,5 +78,5 @@ System Settings
-
Date Generated: 09/03/2022 - 17:36:27
+
Date Generated: 03/19/2023 - 20:19:43
\ No newline at end of file diff --git a/cpld/XC95144XL/WarpSE_xst.xrpt b/cpld/XC95144XL/WarpSE_xst.xrpt index 33818da..3e91863 100644 --- a/cpld/XC95144XL/WarpSE_xst.xrpt +++ b/cpld/XC95144XL/WarpSE_xst.xrpt @@ -1,18 +1,18 @@ - + - +
- + @@ -36,20 +36,16 @@
- + - + - - - - - - + +
@@ -79,7 +75,7 @@
- +
diff --git a/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs b/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs index cd75aa8..f90a5c8 100644 --- a/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs +++ b/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs @@ -8,19 +8,7 @@ -Analyzing Verilog file "Z:/Warp-SE/cpld/CNT.v" into library work - - -"Z:/Warp-SE/cpld/CNT.v" Line 127. Syntax error near "<=". - - -Analyzing Verilog file "Z:/Warp-SE/cpld/IOBM.v" into library work - - -Analyzing Verilog file "Z:/Warp-SE/cpld/RAM.v" into library work - - -Analyzing Verilog file "Z:/Warp-SE/cpld/WarpSE.v" into library work +Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/FSB.v" into library work diff --git a/cpld/XC95144XL/_xmsgs/xst.xmsgs b/cpld/XC95144XL/_xmsgs/xst.xmsgs index f576589..3ce8e0b 100644 --- a/cpld/XC95144XL/_xmsgs/xst.xmsgs +++ b/cpld/XC95144XL/_xmsgs/xst.xmsgs @@ -5,37 +5,58 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -"../RAM.v" line 63 'BACTr' has not been declared +"../RAM.v" line 38 'BACTr' has not been declared -"../RAM.v" line 69 unexpected token: ';' +"../RAM.v" line 96 'RefFromRS0Next' has not been declared -"../RAM.v" line 75 unexpected token: 'begin' +"../RAM.v" line 100 'RAMDIS1' has not been declared -"../RAM.v" line 76 expecting ';', found ')' +"../RAM.v" line 101 'RefFromRS0Pre' has not been declared -"../RAM.v" line 76 unexpected token: '<=' +"../RAM.v" line 107 'RAMDIS1' has not been declared -"../RAM.v" line 76 expecting 'endmodule', found '0' +"../RAM.v" line 113 'RAMDIS1' has not been declared -"../FSB.v" line 59 'BERR' has not been declared +"../RAM.v" line 118 'RAMDIS1' has not been declared -"../CNT.v" line 29 'RefREQ' has not been declared +"../RAM.v" line 124 'RAMDIS1' has not been declared -"../CNT.v" line 30 'RefREQ' has not been declared +"../RAM.v" line 132 'RAMDIS1' has not been declared -"../CNT.v" line 34 expecting ';', found '=' +"../RAM.v" line 139 'RAMDIS1' has not been declared -"../CNT.v" line 34 expecting 'endmodule', found '0' +"../RAM.v" line 146 'RAMDIS1' has not been declared + + +"../RAM.v" line 153 'RAMDIS1' has not been declared + + +"../RAM.v" line 160 'RAMDIS1' has not been declared + + +"../RAM.v" line 167 'RAMDIS1' has not been declared + + +"../RAM.v" line 176 'RAMDIS1' has not been declared + + +"../RAM.v" line 184 'RAMDIS1' has not been declared + + +"../RAM.v" line 190 'RAMDIS1' has not been declared + + +"../FSB.v" line 71 'BERR' has not been declared diff --git a/cpld/XC95144XL/iseconfig/WarpSE.projectmgr b/cpld/XC95144XL/iseconfig/WarpSE.projectmgr index e8178ae..513289b 100644 --- a/cpld/XC95144XL/iseconfig/WarpSE.projectmgr +++ b/cpld/XC95144XL/iseconfig/WarpSE.projectmgr @@ -10,13 +10,13 @@ /MXSE Z:|Warp-SE|cpld|WarpSE.v - WarpSE (Z:/Warp-SE/cpld/WarpSE.v) + iobm - IOBM (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBM.v) 0 0 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000d2000000020000000000000000000000000200000064ffffffff000000810000000300000002000000d20000000100000003000000000000000100000003 true - WarpSE (Z:/Warp-SE/cpld/WarpSE.v) + iobm - IOBM (C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBM.v) @@ -29,7 +29,7 @@ 0 0 - 000000ff0000000000000001000000010000000000000000000000000000000000000000000000012b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012b0000000100000000 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000 false @@ -40,7 +40,7 @@ 0 0 - 000000ff000000000000000100000000000000000100000000000000000000000000000000000002b3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004900000001000000000000009d0000000100000000000000660000000100000000000001670000000100000000 + 000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004900000001000000000000009d0000000100000000000000660000000100000000000002570000000100000000 false CNT.v @@ -52,7 +52,7 @@ 0 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 + 000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000010001000100000000000000000000000064ffffffff000000810000000000000001000003a30000000100000000 false work diff --git a/cpld/XC95144XL/iseconfig/WarpSE.xreport b/cpld/XC95144XL/iseconfig/WarpSE.xreport index 05692b8..cf3d79a 100644 --- a/cpld/XC95144XL/iseconfig/WarpSE.xreport +++ b/cpld/XC95144XL/iseconfig/WarpSE.xreport @@ -1,11 +1,11 @@
- 2022-09-03T14:17:57 + 2023-03-19T20:19:43 WarpSE Unknown - Z:/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport - Z:/Warp-SE/cpld/XC95144XL\ + C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport + C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\ 2022-03-28T09:29:43 false
diff --git a/cpld/XC95144XL/webtalk_pn.xml b/cpld/XC95144XL/webtalk_pn.xml index a5e10f5..5eb1e9b 100644 --- a/cpld/XC95144XL/webtalk_pn.xml +++ b/cpld/XC95144XL/webtalk_pn.xml @@ -3,11 +3,11 @@ - +
- +