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Fixed IOBS bugs
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parent
64acc12a9d
commit
a3c913c8c3
16
cpld/IOBS.v
16
cpld/IOBS.v
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@ -23,12 +23,10 @@ module IOBS(
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/* Read data OE control */
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/* Read data OE control */
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assign nDinOE = !(!nAS && IOCS && nWE && !ROMCS);
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assign nDinOE = !(!nAS && IOCS && nWE && !ROMCS);
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wire IOStart = BACT && IOCS && ~Once;
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/* I/O transfer state
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/* I/O transfer state
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* TS0 - I/O bridge idle:
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* TS0 - I/O bridge idle:
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* asserts IOREQ
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* asserts IOREQ
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* transitions to TS3 when IOStart true
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* transitions to TS3 when BACT && IOCS && !ALE1 && !Once true
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* TS3 - starting I/O transfer:
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* TS3 - starting I/O transfer:
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latches LDS and UDS from FSB or FIFO secondary level
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latches LDS and UDS from FSB or FIFO secondary level
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transitions immediately to TS2
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transitions immediately to TS2
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@ -48,7 +46,7 @@ module IOBS(
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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// If write currently posting (TS!=0),
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// If write currently posting (TS!=0),
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// I/O selected, and FIFO secondary level empty
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// I/O selected, and FIFO secondary level empty
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if (TS!=0 && IOStart && ~ALE1) begin
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if (TS!=0 && BACT && IOCS && !ALE1 && !Once && IOPWCS) begin
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// Latch R/W now but latch address and LDS/UDS next cycle
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// Latch R/W now but latch address and LDS/UDS next cycle
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IORW1 <= nWE;
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IORW1 <= nWE;
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Load1 <= 1;
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Load1 <= 1;
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@ -77,7 +75,7 @@ module IOBS(
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TS <= 3;
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TS <= 3;
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IOREQ <= 1;
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IOREQ <= 1;
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IORW0 <= IORW1;
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IORW0 <= IORW1;
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end else if (IOStart) begin // If I/O selected and FIFO empty
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end else if (BACT && IOCS && !ALE1 && !Once) begin // If I/O selected and FIFO empty
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// Request transfer from IOBM and latch R/W from FSB
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// Request transfer from IOBM and latch R/W from FSB
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TS <= 3;
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TS <= 3;
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IOREQ <= 1;
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IOREQ <= 1;
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@ -114,7 +112,7 @@ module IOBS(
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end else if (TS==1) begin
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end else if (TS==1) begin
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// Wait for IOACT low (transfer over) before going back to idle
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// Wait for IOACT low (transfer over) before going back to idle
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if (~IOACTr) TS <= 0;
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if (~IOACTr) TS <= 0;
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else TS <= 2;
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else TS <= 1;
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IOREQ <= 0;
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IOREQ <= 0;
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// Address latch released since it's controlled by IOBM now
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// Address latch released since it's controlled by IOBM now
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ALE0 <= 0;
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ALE0 <= 0;
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@ -124,14 +122,14 @@ module IOBS(
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/* Once, ready, BERR control */
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/* Once, ready, BERR control */
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (~BACT) Once <= 0;
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if (~BACT) Once <= 0;
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else if (IOCS && !ALE1 && (TS==0 || IOPWCS)) Once <= 1;
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else if (BACT && IOCS && !ALE1 && !Once && (TS==0 || IOPWCS)) Once <= 1;
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end
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end
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (~BACT) begin
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if (~BACT) begin
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// Deassert IOReady and /BERR when bus inactive
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// Deassert IOReady and /BERR when bus inactive
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IOReady <= 0;
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IOReady <= 0;
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nBERR_FSB <= 1;
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nBERR_FSB <= 1;
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end else if (Once && !ALE1 && (TS==0 || (TS==1 && !IOACTr))) begin
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end else if (BACT && IOCS && !IOPWCS && !ALE1 && Once && (TS==0 || (TS==1 && !IOACTr))) begin
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// If transaction submitted, FIFO second level empty,
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// If transaction submitted, FIFO second level empty,
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// and in or entering TS0, all transactions including
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// and in or entering TS0, all transactions including
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// current are complete. So terminate cycle.
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// current are complete. So terminate cycle.
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@ -139,6 +137,6 @@ module IOBS(
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nBERR_FSB <= !IOBERR;
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nBERR_FSB <= !IOBERR;
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end
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end
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end
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end
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assign IOBS_Ready = !IOCS || IOReady || (IOPWCS && !ALE1);
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assign IOBS_Ready = !IOCS || ((IOReady) || (IOPWCS && !ALE1));
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endmodule
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endmodule
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