diff --git a/cpld/CS.v b/cpld/CS.v
index a6fa5bd..edccf71 100644
--- a/cpld/CS.v
+++ b/cpld/CS.v
@@ -28,18 +28,70 @@ module CS(
 	assign RAMCS = RAMCS0X && !Overlay;
 	wire VidRAMCSWR64k = RAMCS && !nWE && (A[23:20]==4'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF
 	wire VidRAMCSWR = VidRAMCSWR64k && (
-		(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
+	    (A[15:12]==4'h2 && // 1792 bytes RAM, 2304 bytes video
+			 (A[11:8]==4'h7 ||
+			  A[11:8]==4'h8 ||
+			  A[11:8]==4'h9 ||
+			  A[11:8]==4'hA ||
+			  A[11:8]==4'hB ||
+			  A[11:8]==4'hC ||
+			  A[11:8]==4'hD ||
+			  A[11:8]==4'hE ||
+			  A[11:8]==4'hF)) ||
 		(A[15:12]==4'h3) || // 4096 bytes video
 		(A[15:12]==4'h4) || // 4096 bytes video
 		(A[15:12]==4'h5) || // 4096 bytes video
 		(A[15:12]==4'h6) || // 4096 bytes video
-		(A[15:12]==4'h7) || // 3200 bytes video, 896 bytes RAM,
-		(A[15:12]==4'hA) || // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
+		(A[15:12]==4'h7 && // 3200 bytes video, 896 bytes RAM
+			 (A[11:8]==4'h0 ||
+			  A[11:8]==4'h1 ||
+			  A[11:8]==4'h2 ||
+			  A[11:8]==4'h3 ||
+			  A[11:8]==4'h4 ||
+			  A[11:8]==4'h5 ||
+			  A[11:8]==4'h6 ||
+			  A[11:8]==4'h7 ||
+			  A[11:8]==4'h8 ||
+			  A[11:8]==4'h9 ||
+			  A[11:8]==4'hA ||
+			  A[11:8]==4'hB ||
+			 (A[11:8]==4'hC && !A[7]))) ||
+		(A[15:12]==4'hA && // 256 bytes RAM, 768 bytes sound, 768 bytes RAM, 2304 bytes video
+			(A[11:8]==4'h1 ||
+			 A[11:8]==4'h2 ||
+			 A[11:8]==4'h3 ||
+			 A[11:8]==4'h7 ||
+			 A[11:8]==4'h8 ||
+			 A[11:8]==4'h9 ||
+			 A[11:8]==4'hA ||
+			 A[11:8]==4'hB ||
+			 A[11:8]==4'hC ||
+			 A[11:8]==4'hD ||
+			 A[11:8]==4'hE ||
+			 A[11:8]==4'hF)) ||
 		(A[15:12]==4'hB) || // 4096 bytes video
 		(A[15:12]==4'hC) || // 4096 bytes video
-		(A[15:12]==4'hD) || // 4096 bytes video
 		(A[15:12]==4'hE) || // 4096 bytes video
-		(A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
+		(A[15:12]==4'hF && // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
+			(A[11:8]==4'h0 ||
+			 A[11:8]==4'h1 ||
+			 A[11:8]==4'h2 ||
+			 A[11:8]==4'h3 ||
+			 A[11:8]==4'h4 ||
+			 A[11:8]==4'h5 ||
+			 A[11:8]==4'h6 ||
+			 A[11:8]==4'h7 ||
+			 A[11:8]==4'h8 ||
+			 A[11:8]==4'h9 ||
+			 A[11:8]==4'hA ||
+			 A[11:8]==4'hB ||
+			(A[11:8]==4'hC && !A[7]) ||
+			 A[11:8]==4'hD ||
+			 A[11:8]==4'hE ||
+			 A[11:8]==4'hF));
+	assign SndRAMCSWR = VidRAMCSWR64k && (
+		((A[15:12]==4'hF) && ((A[11:8]==4'hD) || (A[11:8]==4'hE) || (A[11:8]==4'hF))) ||
+		((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
 
 	/* Select signals - IOB domain */
 	assign IACS =  (A[23:20]==4'hF) && (A[19:18]==2'b11); // IACK
@@ -54,7 +106,7 @@ module CS(
 				   (A[23:20]==4'h7) || // empty
 				   (A[23:20]==4'h6) || // empty
 				   (A[23:20]==4'h5) || // SCSI
-				  ((A[23:20]==4'h4) && Overlay) ||
-				    VidRAMCSWR; // ROM once
+				  ((A[23:20]==4'h4) && Overlay) || // ROM once
+				    VidRAMCSWR; // Write to video RAM
 	assign IOPWCS = VidRAMCSWR;
 endmodule