From a85da985edd3e09eba0cc8ada33d7549a98b7378 Mon Sep 17 00:00:00 2001
From: Zane Kaminski <zanekaminski@gmail.com>
Date: Sat, 8 Apr 2023 05:49:29 -0400
Subject: [PATCH] Fix typos in recent commits

---
 cpld/CNT.v | 20 +++++++++++---------
 cpld/CS.v  |  2 +-
 cpld/FSB.v |  2 +-
 3 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/cpld/CNT.v b/cpld/CNT.v
index 51c448b..8006349 100644
--- a/cpld/CNT.v
+++ b/cpld/CNT.v
@@ -8,7 +8,7 @@ module CNT(
 	/* Mac PDS bus master control outputs */
 	output reg AoutOE, output reg nBR_IOB,
 	/* Sound QoS */
-	input BACT, input SndRAMCSWR, output QoSReady);
+	input BACT, input SndRAMCSWR, output reg QoSReady);
 	
 	/* E clock synchronization */
 	reg [1:0] Er;
@@ -17,6 +17,9 @@ module CNT(
 	
 	/* NMI button synchronization */
 	reg nIPL2r; always @(posedge CLK) nIPL2r <= nIPL2;
+	
+	/* Startup sequence state */
+	reg [1:0] IS = 0;
 
 	/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
     *	Refresh timer sequence
@@ -57,7 +60,7 @@ module CNT(
 		if (EFall && TimerTC) begin
 			if (IS==3) begin
 				LTimer[12:10] <= 3'b000;
-				if (LTimer==0 && BACT && VidRAMCSWR) LTimer <= 1;
+				if (LTimer==0 && BACT && SndRAMCSWR) LTimer <= 1;
 				else if (LTimer==0) LTimer <= 0;
 				else LTimer[9:0] <= LTimer+1;
 			end else LTimer <= LTimer+1;
@@ -68,19 +71,18 @@ module CNT(
 	/* Sound QoS */
 	reg [3:0] WS = 0;
 	always @(posedge CLK) begin
-		if (BACT) begin
-			if (QoSReady) QoSReady <= 1;
-			else if (WS==12) QoSReady <= 1;
-			WS <= WS+1;
-		end else begin
+		if (!BACT) begin
 			if (LTimer!=0) QoSReady <= 0;
 			else QoSReady <= 1;
 			WS <= 0;
+		end else begin
+			if (QoSReady) QoSReady <= 1;
+			else if (WS==12) QoSReady <= 1;
+			WS <= WS+1;
 		end
 	end
 
-	/* Startup sequence control */
-	reg [1:0] IS = 0;
+	/* Startup sequence state control */
 	wire ISTC = EFall && TimerTC && LTimerTC;
 	always @(posedge CLK) begin
 		case (IS[1:0])
diff --git a/cpld/CS.v b/cpld/CS.v
index 0960e1b..f2ef6ba 100644
--- a/cpld/CS.v
+++ b/cpld/CS.v
@@ -95,7 +95,7 @@ module CS(
 		((A[15:12]==4'hA) && ((A[11:8]==4'h1) || (A[11:8]==4'h2) || (A[11:8]==4'h3))));
 
 	/* Select signals - IOB domain */
-	assign IACS =  A[23:16]==4'hFF; // IACK
+	assign IACS =  A[23:16]==8'hFF; // IACK
 	assign IOCS =  A[23:20]==4'hF || // IACK
 				   A[23:20]==4'hE || // VIA
 				   A[23:20]==4'hD || // IWM
diff --git a/cpld/FSB.v b/cpld/FSB.v
index e480946..7dec64a 100644
--- a/cpld/FSB.v
+++ b/cpld/FSB.v
@@ -8,7 +8,7 @@ module FSB(
 	input RAMCS, input RAMReady,
 	input IOPWCS, input IOPWReady, input IONPReady,
 	input QoSReady,
-	/* Interrupt acknowledge select */z
+	/* Interrupt acknowledge select */
 	input IACS);
 
 	/* AS cycle detection */