From a91c6c4ffbf0ad20f333d810eb53677d5d2da309 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Sat, 3 Sep 2022 21:32:05 -0400 Subject: [PATCH] New stuff --- cpld/CNT.v | 118 ++++-- cpld/CS.v | 8 +- cpld/FSB.v | 34 +- cpld/IOBM.v | 39 +- cpld/RAM.v | 101 +++-- cpld/WarpSE.v | 73 ++-- cpld/XC95144XL/WarpSE.cmd_log | 3 + cpld/XC95144XL/WarpSE.gise | 9 +- cpld/XC95144XL/WarpSE.stx | 0 cpld/XC95144XL/WarpSE.syr | 425 +-------------------- cpld/XC95144XL/WarpSE_summary.html | 21 +- cpld/XC95144XL/WarpSE_xst.xrpt | 60 +-- cpld/XC95144XL/_xmsgs/pn_parser.xmsgs | 16 +- cpld/XC95144XL/_xmsgs/xst.xmsgs | 32 +- cpld/XC95144XL/iseconfig/WarpSE.projectmgr | 4 +- cpld/XC95144XL/iseconfig/WarpSE.xreport | 6 +- cpld/XC95144XL/webtalk_pn.xml | 2 +- cpld/XC95144XL/xst/work/hdllib.ref | 10 +- cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin | Bin 20942 -> 20942 bytes cpld/XC95144XL/xst/work/vlg22/_c_s.bin | Bin 13511 -> 13528 bytes cpld/XC95144XL/xst/work/vlg37/_f_s_b.bin | Bin 7217 -> 7217 bytes cpld/XC95144XL/xst/work/vlg73/_i_o_b_m.bin | Bin 19519 -> 19519 bytes cpld/XC95144XL/xst/work/vlg79/_i_o_b_s.bin | Bin 12663 -> 12663 bytes 23 files changed, 321 insertions(+), 640 deletions(-) delete mode 100644 cpld/XC95144XL/WarpSE.stx diff --git a/cpld/CNT.v b/cpld/CNT.v index d26fff4..ffe2ae2 100644 --- a/cpld/CNT.v +++ b/cpld/CNT.v @@ -1,34 +1,104 @@ module CNT( - /* FSB clock and AS detection */ - input FCLK, input CACT, + /* C16M clock */ + input C16M, + /* FSB clock and bus active signal */ + input FCLK, input BACT, /* Refresh request */ - output RefReq, output RefUrgent, input RefAck, - /* Timeout signals */ - output reg TimeoutA, output reg TimeoutB); - - /* Refresh counter */ - reg [7:0] RefCnt = 0; - reg RefDone = 0; - assign RefReq = ~RefDone; - assign RefUrgent = RefCnt[7] && RefCnt[6] && RefCnt[5] && ~RefDone; - always @(posedge FCLK) begin - RefCnt <= RefCnt+1; - if (RefCnt==0) RefDone <= 0; - else if (RefAck) RefDone <= 1; + output reg RefReq, output RefUrgent, + /* BERR and QoS speed limit output */ + output reg BERRTimeout, output reg QoSReady, + /* Reset, switch, button */ + input [3:1] SW, input nRESin, output reg nRESout, input nIPL2, + /* Configuration outputs */ + output reg nBR_IOB, output reg FastROMEN, output reg C20MEN, output reg C25MEN); + + /* Timer counts from 0 to 11100000 (224) -- 225 states == 14.36 uS */ + reg [7:0] Timer = 0; + wire TimerTC = Timer[7:5]==3'b111; + always @(posedge C16M) Timer <= TimerTC ? 0 : Timer+1; + + /* Refresh timer outputs + * ___ _______________________________________ + * RefReq |___________| |_________ + * ___^ Timer==0 ^ Timer==17 _____________^ Timer==0 + * RefUrg |_____________________________________| |_________ + * ^ Timer==0 ^ Timer==128 ^ Timer==0 + */ + assign RefUrgent = Timer[7]; + always @(posedge C16M) begin + if (Timer[4]) RefREQ <= 1; + else if (TimerTC) RefREQ <= 0; end - /* Timeout signals */ - reg TimeoutBPre; + /* NBACT - "Narrow BACT" in FCLK clock domain */ + reg [1:0] BACTCnt = 0; + reg NBACT; always @(posedge FCLK) begin - if (~CACT) begin - TimeoutA <= 0; - TimeoutBPre <= 0; - TimeoutB <= 0; + if (!BACT) begin + BACTCnt <= 0; + NBACT <= 0; end else begin - if (RefCnt[6:0]==0) TimeoutA <= 1; - if (RefCnt==0) TimeoutBPre <= 1; - if (RefCnt==0 && TimeoutBPre) TimeoutB <= 1; + BACTCnt <= BACTCnt+1; + if (BACTCnt==2'b11 && BACT) NBACT <= 1; end end + /* NBACTr - NBACT synchronized to C16M clock domain */ + reg NBACTr; + always @(posedge C16M) NBACTr <= NBACT; + + /* BERR generation in C16M clock domain */ + reg BERRArm = 0; + reg BERRTimeout = 0; + always @(posedge C16M) begin + if (NBACTr && TimerTC) begin + if (BERRArm) BERRTimeout <= 1; + end else if (!NBACTr) begin + BERRArm <= 0; + BERRTimeout <= 0; + end + end + + /* Sound QoS */ + reg [3:0] SC; // Sound counter + always @(posedge C16M) begin + if (PORDone && TimerTC) SC <= SC+1; // SC increment + if SC[] + end + + /* IPL2 and /RESET registration */ + reg nIPL2r, nRESr; + always @(posedge C16M) begin + nIPL2r <= nIPL2; + nRESr <= nRES; + end + + /* Startup sequence control */ + reg PORDone = 0; + always @(posedge C16M) begin + if (!PORDone) begin + if (!nRESr) nRESout <= 1; + else begin + nRESout <= 0; // Re-enable reset + PORDone <= 1; // Mark POR done + // Decode buttons + if (nRESr) begin // Reset not pressed: enable WarpSE + nBR_IOB <= 0; // Request Mac bus + FastROMEN <= 1; // Fast ROM enabled + end else if (!nRES && nIPL2r) begin // Reset only: disable card + nBR_IOB <= 1; // Don't request Mac bus + FastROMEN <= 0; // Fast ROM enable is don't care + end else if (!nRES && !nIPL2r) begin // Reset+IPL2: MB ROM + nBR_IOB <= 0; // Request Mac bus + FastROMEN <= 1; // Fast ROM disabled so as to use motherboard ROM + end + end + end else if (SC[4]) nRESout <= 1; // Release reset to run + end + + // Enable both oscillators... only mount one + assign C20MEN = 1; // SW[0]; + assign C25MEN = 1; //!SW[0]; + endmodule + \ No newline at end of file diff --git a/cpld/CS.v b/cpld/CS.v index 1b2705d..b33a1a7 100644 --- a/cpld/CS.v +++ b/cpld/CS.v @@ -1,6 +1,6 @@ module CS( /* Setting input */ - input MotherboardROMEN, + input FastROMEN, /* MC68HC000 interface */ input [23:08] A, input CLK, input nRES, input nWE, /* AS cycle detection */ @@ -44,13 +44,13 @@ module CS( (A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) || (A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3))); - assign ROMCS = (A[23:20]==4'h4 && !MotherboardROMEN) || - (A[23:20]==4'h8 && MotherboardROMEN) || + assign ROMCS = (A[23:20]==4'h4 && FastROMEN) || + (A[23:20]==4'h8 && !FastROMEN) || (A[23:20]==4'h0 && Overlay); /* Select signals - IOB domain */ assign IACS = A[23:08]==16'hFFFF; // IACK - assign IOCS = (A[23:20]==4'h4 && MotherboardROMEN) || // Motherboard ROM + assign IOCS = (A[23:20]==4'h4 && !FastROMEN) || // Motherboard ROM A[23:20]==4'h5 || // SCSI A[23:20]==4'h8 || // empty A[23:20]==4'h9 || // SCC read/reset diff --git a/cpld/FSB.v b/cpld/FSB.v index c7299cc..60a71d0 100644 --- a/cpld/FSB.v +++ b/cpld/FSB.v @@ -4,7 +4,7 @@ module FSB( /* AS cycle detection */ output BACT, /* Ready inputs */ - input Ready0, input Ready1, input Ready2, input Disable, + input Ready0, input Ready1, input Ready2, /* BERR inputs */ input BERR0, input BERR1, /* Interrupt acknowledge select */ @@ -15,29 +15,39 @@ module FSB( always @(negedge FCLK) begin ASrf <= ~nAS; end assign BACT = ~nAS || ASrf; - /* Ready and BERR bypass */ + /* Ready generation and bypass */ reg Ready0r, Ready1r, Ready2r; - reg BERR0r, BERR1r; - wire Ready = ~Disable && (Ready0 || Ready0r) && - (Ready1 || Ready1r) && - (Ready2 || Ready2r); - wire BERR = (BERR0 || BERR0r || BERR1 || BERR1r); - assign nBERR = ~(~nAS && BERR); + wire Ready = (Ready0 || Ready0r) && + (Ready1 || Ready1r) && + (Ready2 || Ready2r); always @(posedge FCLK) begin if (~BACT) begin Ready0r <= 0; Ready1r <= 0; Ready2r <= 0; - BERR0r <= 0; - BERR1r <= 0; end else begin if (Ready0) Ready0r <= 1; if (Ready1) Ready1r <= 1; if (Ready2) Ready2r <= 1; - if (BERR0) BERR0r <= 1; - if (BERR1) BERR1r <= 1; end end + + /* BERR generation */ + reg BERR0r, BERR1r; + always @(posedge FCLK) BERR0r <= BERR0; + always @(posedge FCLK) BERR1r <= BERR1; + reg BERREN = 0; + reg BERRCNT = 0; + always @(posedge FCLK) begin + if (~BACT) begin + BERREN <= 0; + BERRCNT <= 0; + end else begin + BERRCNT <= BERRCNT+1; + BERREN <= BERRCNT==3'b111; + end + end + assign nBERR = ~(~nAS && BERREN && (BERR0r || BERR1r)); /* DTACK/VPA control */ reg VPA; diff --git a/cpld/IOBM.v b/cpld/IOBM.v index 9699bf8..a421197 100644 --- a/cpld/IOBM.v +++ b/cpld/IOBM.v @@ -1,7 +1,7 @@ module IOBM( /* PDS interface */ input C16M, input C8M, input E, - output nBR, output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA, + output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA, input nASin, input nBG, input nDTACK, input nVPA, input nBERR, input nRES, /* PDS address and data latch control */ output nAoutOE, output reg nDoutOE, output reg ALE0, output reg nDinLE, @@ -9,6 +9,14 @@ module IOBM( output reg IOACT, output reg IOBERR, input Park, input IOREQ, input IOLDS, input IOUDS, input IOWE); + /* Bus grant recognition */ + reg nASr; + reg BG = 0; + always @(posedge C16M) begin + nASr <= nASin; + if (nASr) BG <= nBG; + end + /* I/O bus slave port input synchronization */ reg IOREQr = 0; always @(negedge C16M) begin IOREQr <= IOREQ; end @@ -52,35 +60,14 @@ module IOBM( else if (ES==0) nVMA <= 1; end - /* Bus Request/Grant control */ - assign nBR = Park; - reg BGr0 = 0; - reg BGr1 = 0; - reg BG = 0; - always @(posedge C16M) begin - BGr0 <= ~nBG; - BGr1 <= BGr0; - if (BGr1 && nASin) BG <= 1; - else if (~BGr0) BG <= 0; - end - /* I/O bus state */ reg [2:0] IOS = 0; always @(posedge C16M) begin if (IOS==0) begin - if (IOREQr && BG) begin - if (~C8M) begin - IOS <= 1; - end else begin - IOS <= 0; - end - IOACT <= 1; - ALE0 <= 1; - end else begin - IOS <= 0; - IOACT <= 0; - ALE0 <= 0; - end + if (~C8M && IOREQr && BG) IOS <= 1; + else IOS <= 0; + IOACT <= IOREQr; + ALE0 <= IOREQr; end else if (IOS==1) begin IOS <= 2; IOACT <= 1; diff --git a/cpld/RAM.v b/cpld/RAM.v index 04f5629..a48d74f 100644 --- a/cpld/RAM.v +++ b/cpld/RAM.v @@ -6,31 +6,74 @@ module RAM( /* Select and ready signals */ input RAMCS, input ROMCS, output Ready, /* Refresh Counter Interface */ - input RefReq, input RefUrgent, output RefAck, + input RefReqIn, input RefUrgentIn, /* DRAM and NOR flash interface */ output [11:0] RA, output nRAS, output reg nCAS, output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE); /* RAM control state */ reg [2:0] RS = 0; - reg Once = 0; + reg RAMEN = 0; reg RAMReady = 0; reg RASEL = 0; // RASEL controls /CAS signal + + /* Refresh request synchronization */ + reg RefReqR; // Refresh synchronization + always @(posedge CLK) RefReqR <= RefReqIn; + reg RefReq, RefUrgent; // Refresh commands + reg RefDone; // Refresh done "remember" + always @(posedge CLK) begin + RefReq <= RefReqR && !RefDone; + RefUrgent <= RefReqR && RefUrgentIn && !RefDone; + if (!RefReqR) RefDone <= 0; + else if (RS==2 || RS==3) RefDone <= 1; // RS2 || RS3 to save 1 input + end + + /* RAM enable + */ + + /* Refresh init conditions */ + wire RAMRefFromRS0Next = RS==0 && ( + // Non-urgent refresh can start during first clock of non-RAM cycle + ( BACT && ~BACTr && ~RAMCS && RefReq) || + // Urgent refresh can start during bus idle + (~BACT && RefUrgent) || + // Urgent refresh can start during non-ram cycle + ( BACT && ~RAMCS && RefUrgent)); + wire RAMRefFromRS0Pre = RS==0 && + // Urgent refresh can start during long RAM cycle after RAM access done. + BACT && RAMCS && !RAMEN && RefUrgent; + wire RAMRefFromRS0 = RAMRefFromRS0Next || RAMRefFromRS0Pre; + // Urgent refresh cannot start when BACT and RAMCS and RAMEN, + // since /RAS has already been asserted. For this we wait for RS7. + wire RAMRefFromRS7 = RS==7 && RefUrgent; + + /* RAM access start condition */ + wire RAMStart = RS==0 && BACT && RAMCS && RAMEN; + + /* RAM enable (/AS -> /RAS) */ + always @(posedge CLK) begin + if (RS==0) begin + if (RAMRefFromRS0) RAMEN <= 0; + else if (!BACT) RAMEN <= 1; + end else if (RS==7) begin + if (RAMRefFromRS7) RAMEN <= 0; + else if (BACT) RAMEN <= 0; + else if (!BACT) RAMEN <= 1; + end + end /* Refresh state */ - reg RAMDIS1 = 0; - reg RAMDIS2 = 0; - wire RAMDIS = RAMDIS1 || RAMDIS2; - wire RAMEN = ~RAMDIS; reg RefRAS = 0; assign nROMCS = ~ROMCS; - assign nRAS = ~((~nAS && RAMCS && RAMEN && ~RefRAS /* does this add loading to these P-terms? */) || RefRAS); + assign nRAS = ~((~nAS && RAMCS && RAMEN) || RefRAS); assign nOE = ~(~nAS && nWE); assign nLWE = ~(~nAS && ~nWE && ~nLDS && RAMEN); assign nUWE = ~(~nAS && ~nWE && ~nUDS && RAMEN); assign nROMWE = ~(~nAS && ~nWE); + /* RAM address mux (and ROM address on RA8) */ assign RA[11] = A[19]; assign RA[10] = A[21]; assign RA[09] = RASEL ? A[20] : A[19]; @@ -44,35 +87,31 @@ module RAM( assign RA[01] = RASEL ? A[02] : A[11]; assign RA[00] = RASEL ? A[01] : A[10]; - always @(posedge CLK) begin - if (~BACT) Once <= 0; - else if (RS==0 && BACT && RAMCS) Once <= 1; - end - always @(posedge CLK) begin - if (~BACT) RAMDIS2 <= 0; - else if ((RS==0 && BACT && RefUrgent && Once && RAMCS) || - (RS==7 && BACT && RefUrgent && Once)) RAMDIS2 <= 1; - end + // Save BACT from last clock reg BACTr; - always @(posedge CLK) begin BACTr <= BACT; end + always @(posedge CLK) BACTr <= BACT; always @(posedge CLK) begin if (RS==0) begin - if (( BACT && RefReq && ~RAMCS && ~BACTr) || // Non-urgent refresh can start during first clock of non-RAM cycle - (~BACT && RefUrgent) || // Urgent refresh can start during bus idle - ( BACT && RefUrgent && ~RAMCS)) begin // Urgent refresh can start during non-ram cycle + // In RS0, RAM is idle and ready for new command. + if (RefFromRS0Next) begin RS <= 2; RAMReady <= 0; RASEL <= 1; RAMDIS1 <= 1; - end else if (BACT && RAMCS && ~Once) begin + end else if (RefFromRS0Pre) begin + // Urgent ref can start during long RAM cycle after access. + // Must insert one extra precharge state first by going to RS1. + RS <= 1; + RAMReady <= 0; + RASEL <= 0; + RAMDIS1 <= 1; + end else if (BACT && RAMCS && RAMEN) begin // RAM access cycle has priority over urgent refresh if RAM access already begun RS <= 5; RAMReady <= 0; RASEL <= 1; RAMDIS1 <= 0; - end else if (BACT && RAMCS && RefUrgent) begin - // Urgent refresh can start during prolonged RAM access cycle - // But we must insert one extra precharge state first. + end else if (RAMRefFromRS0Pre) begin RS <= 1; RAMReady <= 0; RASEL <= 0; @@ -86,53 +125,65 @@ module RAM( end RefRAS <= 0; end else if (RS==1) begin + // RS1 implements extra precharge time before refresh. RS <= 2; RAMReady <= 0; RASEL <= 1; RAMDIS1 <= 1; RefRAS <= 0; end else if (RS==2) begin + // Refresh RAS pulse asserted ater RS2. RS <= 3; RAMReady <= 0; RASEL <= 1; RAMDIS1 <= 1; RefRAS <= 1; end else if (RS==3) begin + // RS3 implements requisite RAS pulse width. RS <= 4; RAMReady <= 0; RASEL <= 0; RAMDIS1 <= 1; RefRAS <= 1; end else if (RS==4) begin + // RS4 implements precharge after RAM refresh. RS <= 7; RAMReady <= 0; RASEL <= 0; RAMDIS1 <= 1; RefRAS <= 0; end else if (RS==5) begin + // RS5 is first state of R/W operation RS <= 6; RAMReady <= 0; RASEL <= 1; RAMDIS1 <= 0; RefRAS <= 0; end else if (RS==6) begin + // RS6 is second state of R/W operation RS <= 7; RAMReady <= 0; RASEL <= 0; RAMDIS1 <= 0; RefRAS <= 0; end else if (RS==7) begin + // RS7 is final state of R/W or refresh operation. if (~BACT && RefUrgent) begin + // If /AS cycle terminated and urgent refresh request, + // we know /RAS has been in precharge so we can go to RS2. RS <= 2; RAMReady <= 0; RAMDIS1 <= 1; RASEL <= 1; end else if (BACT && RefUrgent) begin + // But if /AS cycle hasn't terminated and we need to refresh, + // we need to go to RS1 to add additional precharge time. RS <= 1; RAMReady <= 0; RASEL <= 0; RAMDIS1 <= 1; end else begin + // Otherwise if no urgent refresh request, go to RS0. RS <= 0; RAMReady <= 1; RASEL <= 0; @@ -143,8 +194,6 @@ module RAM( end always @(negedge CLK) begin nCAS <= ~RASEL; end - assign RefAck = RefRAS; - assign Ready = ~RAMCS || RAMReady; endmodule diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v index 49ffa5e..8b1de78 100644 --- a/cpld/WarpSE.v +++ b/cpld/WarpSE.v @@ -20,7 +20,7 @@ module WarpSE( output nBR_IOB, input nBG_IOB, input nBERR_IOB, - input nRES, + inout nRES, input nIPL2, output nROMCS, output nRAMLWE, @@ -36,27 +36,30 @@ module WarpSE( output nDoutOE, output nDinOE, output nDinLE, - input [2:0] SW, - output CLK20EN, - output CLK25EN); + input [3:1] SW, + output C20MEN, + output C25MEN); - /* DIP switches */ - assign CLK20EN = SW[0]; - assign CLK25EN = !SW[0]; - wire MotherboardROMEN = !SW[1]; + /* Reset input and open-drain output */ + wire nRESin = nRES; + wire nRESout; + assign nRES = !nRESout ? 1'b0 : 1'bZ; /* AS cycle detection */ wire BACT; /* Refresh request/ack signals */ - wire RefReq, RefUrgent, RefAck; + wire RefReq, RefUrgent; + + /* Fast ROM enable setting */ + wire FastROMEN; wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR; CS cs( /* Setting input */ - MotherboardROMEN, + FastROMEN, /* MC68HC000 interface */ - A_FSB[23:08], CLK_FSB, nRES, nWE_FSB, + A_FSB[23:08], CLK_FSB, nRESin, nWE_FSB, /* AS cycle detection */ BACT, /* Device select outputs */ @@ -71,13 +74,13 @@ module WarpSE( /* Select and ready signals */ RAMCS, ROMCS, Ready_RAM, /* Refresh Counter Interface */ - RefReq, RefUrgent, RefAck, + RefReq, RefUrgent, /* DRAM and NOR flash interface */ RA[11:0], nRAS, nCAS, nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE); wire Ready_IOBS, BERR_IOBS; - wire Park, IOREQ, IOACT, IOBERR; + wire IOREQ, IOACT, IOBERR; wire ALE0S, ALE0M, ALE1; assign nADoutLE0 = ~(ALE0S || ALE0M); assign nADoutLE1 = ~ALE1; @@ -106,38 +109,28 @@ module WarpSE( IOBM iobm( /* PDS interface */ CLK2X_IOB, CLK_IOB, E_IOB, - nBR_IOB, nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout, - nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRES, + nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout, + nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin, /* PDS address and data latch control */ nAoutOE, nDoutOE, ALE0M, nDinLE, /* IO bus slave port interface */ IOACT, IOBERR, - Park, IOREQ, IOL0, IOU0, IORW0); + IOREQ, IOL0, IOU0, IORW0); - wire TimeoutA, TimeoutB; + wire BERRTimeout, QoSReady; CNT cnt( - /* FSB clock and AS detection */ - CLK_FSB, BACT, + /* C16M clock */ + C16M, + /* FSB clock and bus active signal */ + FCLK, BACT, /* Refresh request */ - RefReq, RefUrgent, RefAck, - /* Timeout signals */ - TimeoutA, TimeoutB); - - /* Accelerator Disable Control */ - reg RESr0 = 0; - reg RESr1 = 0; - reg RESr2 = 0; - reg IPL2r0 = 0; - reg IPL2r1 = 0; - reg RESDone = 0; - reg Disable = 0; - assign Park = ~Disable; - always @(posedge CLK_FSB) begin - RESr0 <= ~nRES; RESr1 <= RESr0; RESr2 <= RESr1; - IPL2r0 <= ~nIPL2; IPL2r1 <= IPL2r0; - if ( RESr0 && RESr1 && RESr2 && ~RESDone && IPL2r0 && IPL2r1) Disable <= 1; - if (~RESr0 && ~RESr1 && RESr2) RESDone <= 1; - end + RefReq, RefUrgent, + /* BERR and QoS speed limit output */ + BERRTimeout, QoSReady, + /* Reset, switch, button */ + SW[3:1], nRESin, nRESout, nIPL2, + /* Configuration outputs */ + nBR_IOB, FastROMEN, C20MEN, C25MEN); FSB fsb( /* MC68HC000 interface */ @@ -145,9 +138,9 @@ module WarpSE( /* AS cycle detection */ BACT, /* Ready and IA inputs */ - Ready_RAM, Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA), Disable, + Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady), /* BERR inputs */ - (~SCSICS && TimeoutB), BERR_IOBS, + (~IOCS && BERRTimeout), BERR_IOBS, /* Interrupt acknowledge select */ IACS); diff --git a/cpld/XC95144XL/WarpSE.cmd_log b/cpld/XC95144XL/WarpSE.cmd_log index 55c92dc..b3ac8cd 100644 --- a/cpld/XC95144XL/WarpSE.cmd_log +++ b/cpld/XC95144XL/WarpSE.cmd_log @@ -22,3 +22,6 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt verilog -optimize speed -htmlr XSLTProcess WarpSE_build.xml tsim -intstyle ise WarpSE WarpSE.nga taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" +xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr" diff --git a/cpld/XC95144XL/WarpSE.gise b/cpld/XC95144XL/WarpSE.gise index 2550eb8..b491f79 100644 --- a/cpld/XC95144XL/WarpSE.gise +++ b/cpld/XC95144XL/WarpSE.gise @@ -78,16 +78,16 @@ - - - + + + + - @@ -103,6 +103,7 @@ + diff --git a/cpld/XC95144XL/WarpSE.stx b/cpld/XC95144XL/WarpSE.stx deleted file mode 100644 index e69de29..0000000 diff --git a/cpld/XC95144XL/WarpSE.syr b/cpld/XC95144XL/WarpSE.syr index 50a806d..4d5b97b 100644 --- a/cpld/XC95144XL/WarpSE.syr +++ b/cpld/XC95144XL/WarpSE.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.84 secs +Total CPU time to Xst completion: 0.97 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.87 secs +Total CPU time to Xst completion: 0.98 secs --> Reading design: WarpSE.prj @@ -76,423 +76,36 @@ wysiwyg : NO * HDL Compilation * ========================================================================= Compiling verilog file "../RAM.v" in library work -Compiling verilog file "../IOBS.v" in library work +ERROR:HDLCompilers:28 - "../RAM.v" line 63 'BACTr' has not been declared +ERROR:HDLCompilers:26 - "../RAM.v" line 69 unexpected token: ';' +ERROR:HDLCompilers:26 - "../RAM.v" line 75 unexpected token: 'begin' +ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting ';', found ')' +ERROR:HDLCompilers:26 - "../RAM.v" line 76 unexpected token: '<=' Module compiled +ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting 'endmodule', found '0' +Compiling verilog file "../IOBS.v" in library work Compiling verilog file "../IOBM.v" in library work Module compiled Compiling verilog file "../FSB.v" in library work Module compiled +ERROR:HDLCompilers:28 - "../FSB.v" line 59 'BERR' has not been declared Compiling verilog file "../CS.v" in library work Module compiled Compiling verilog file "../CNT.v" in library work Module compiled -Compiling verilog file "../WarpSE.v" in library work +ERROR:HDLCompilers:28 - "../CNT.v" line 29 'RefREQ' has not been declared +ERROR:HDLCompilers:28 - "../CNT.v" line 30 'RefREQ' has not been declared +ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting ';', found '=' Module compiled +ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting 'endmodule', found '0' +Compiling verilog file "../WarpSE.v" in library work Module compiled -No errors in compilation -Analysis of file <"WarpSE.prj"> succeeded. - - -========================================================================= -* Design Hierarchy Analysis * -========================================================================= -Analyzing hierarchy for module in library . - -Analyzing hierarchy for module in library . - -Analyzing hierarchy for module in library . - -Analyzing hierarchy for module in library . - -Analyzing hierarchy for module in library . - -Analyzing hierarchy for module in library . - -Analyzing hierarchy for module in library . - - -========================================================================= -* HDL Analysis * -========================================================================= -Analyzing top module . -Module is correct for synthesis. - -Analyzing module in library . -Module is correct for synthesis. - -Analyzing module in library . -Module is correct for synthesis. - -Analyzing module in library . -Module is correct for synthesis. - -Analyzing module in library . -Module is correct for synthesis. - -Analyzing module in library . -Module is correct for synthesis. - -Analyzing module in library . -Module is correct for synthesis. - - -========================================================================= -* HDL Synthesis * -========================================================================= - -Performing bidirectional port resolution... - -Synthesizing Unit . - Related source file is "../CS.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "../RAM.v". - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 18 | - | Inputs | 6 | - | Outputs | 9 | - | Clock | CLK (rising_edge) | - | Power Up State | 000 | - | Encoding | automatic | - | Implementation | automatic | - ----------------------------------------------------------------------- - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 6 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "../IOBS.v". - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 10 | - | Inputs | 5 | - | Outputs | 5 | - | Clock | CLK (rising_edge) | - | Power Up State | 00 | - | Encoding | automatic | - | Implementation | automatic | - ----------------------------------------------------------------------- - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "../IOBM.v". - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 16 | - | Inputs | 7 | - | Outputs | 8 | - | Clock | C16M (rising_edge) | - | Power Up State | 000 | - | Encoding | automatic | - | Implementation | automatic | - ----------------------------------------------------------------------- - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit up counter for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 1 Counter(s). - inferred 22 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "../CNT.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit up counter for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 1 Counter(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "../FSB.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "../WarpSE.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit tristate buffer for signal . - Found 1-bit tristate buffer for signal . - Found 1-bit tristate buffer for signal . - Found 1-bit tristate buffer for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 4 Tristate(s). -Unit synthesized. - - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# Counters : 2 - 5-bit up counter : 1 - 8-bit up counter : 1 -# Registers : 68 - 1-bit register : 68 -# Tristates : 4 - 1-bit tristate buffer : 4 - -========================================================================= - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 011 - 011 | 010 - 100 | 110 - 101 | 111 - 110 | 101 - 111 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with johnson encoding. -------------------- - State | Encoding -------------------- - 00 | 00 - 11 | 01 - 10 | 11 - 01 | 10 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with compact encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 010 | 010 - 101 | 001 - 001 | 101 - 011 | 011 - 100 | 111 - 111 | 100 - 110 | 110 -------------------- -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable. - You should achieve better results by setting this init to 1. - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# FSMs : 3 -# Counters : 2 - 5-bit up counter : 1 - 8-bit up counter : 1 -# Registers : 47 - Flip-Flops : 47 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1426 - The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE. - You should achieve better results by setting this init to 1. - -Optimizing unit ... - implementation constraint: INIT=r : RESr0 - implementation constraint: INIT=r : RESr1 - implementation constraint: INIT=r : RESr2 - implementation constraint: INIT=r : IPL2r0 - implementation constraint: INIT=r : IPL2r1 - implementation constraint: INIT=r : Disable - implementation constraint: INIT=r : RESDone - implementation constraint: INIT=r : ram/RAMReady - implementation constraint: INIT=r : ram/RASEL - implementation constraint: INIT=r : ram/RAMDIS1 - implementation constraint: INIT=r : ram/RefRAS - implementation constraint: INIT=r : ram/RAMDIS2 - implementation constraint: INIT=r : ram/Once - implementation constraint: INIT=r : iobs/IOACTr - implementation constraint: INIT=r : ram/RS_FSM_FFd1 - implementation constraint: INIT=r : iobs/Once - implementation constraint: INIT=r : cs/nOverlay0 - implementation constraint: INIT=r : cs/nOverlay1 - implementation constraint: INIT=r : iobs/PS_FSM_FFd1 - implementation constraint: INIT=r : iobs/PS_FSM_FFd2 - implementation constraint: INIT=r : iobm/ETACK - implementation constraint: INIT=r : iobm/BGr0 - implementation constraint: INIT=r : iobm/BGr1 - implementation constraint: INIT=r : iobm/BG - implementation constraint: INIT=r : iobm/IOREQr - implementation constraint: INIT=r : fsb/ASrf - implementation constraint: INIT=r : ram/RS_FSM_FFd2 - implementation constraint: INIT=r : cnt/RefDone - implementation constraint: INIT=r : cnt/RefCnt_0 - implementation constraint: INIT=r : cnt/RefCnt_1 - implementation constraint: INIT=r : cnt/RefCnt_2 - implementation constraint: INIT=r : cnt/RefCnt_3 - implementation constraint: INIT=r : cnt/RefCnt_4 - implementation constraint: INIT=r : cnt/RefCnt_5 - implementation constraint: INIT=r : cnt/RefCnt_6 - implementation constraint: INIT=r : cnt/RefCnt_7 - implementation constraint: INIT=r : ram/RS_FSM_FFd3 - implementation constraint: INIT=r : iobm/IOS_FSM_FFd1 - implementation constraint: INIT=r : iobm/IOS_FSM_FFd2 - implementation constraint: INIT=r : iobm/IOS_FSM_FFd3 - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Final Report * -========================================================================= -Final Results -RTL Top Level Output File Name : WarpSE.ngr -Top Level Output File Name : WarpSE -Output Format : NGC -Optimization Goal : Speed -Keep Hierarchy : No -Target Technology : XC9500XL CPLDs -Macro Preserve : YES -XOR Preserve : YES -Clock Enable : YES -wysiwyg : NO - -Design Statistics -# IOs : 75 - -Cell Usage : -# BELS : 596 -# AND2 : 165 -# AND3 : 25 -# AND4 : 15 -# AND5 : 3 -# AND6 : 1 -# AND7 : 1 -# AND8 : 3 -# GND : 1 -# INV : 265 -# OR2 : 98 -# OR3 : 5 -# OR4 : 1 -# VCC : 1 -# XOR2 : 12 -# FlipFlops/Latches : 89 -# FD : 60 -# FDCE : 29 -# Tri-States : 1 -# BUFE : 1 -# IO Buffers : 74 -# IBUF : 39 -# OBUF : 31 -# OBUFE : 4 -========================================================================= - - -Total REAL time to Xst completion: 39.00 secs -Total CPU time to Xst completion: 38.76 secs - +Analysis of file <"WarpSE.prj"> failed. --> -Total memory usage is 236884 kilobytes +Total memory usage is 190552 kilobytes -Number of errors : 0 ( 0 filtered) -Number of warnings : 5 ( 0 filtered) +Number of errors : 11 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) diff --git a/cpld/XC95144XL/WarpSE_summary.html b/cpld/XC95144XL/WarpSE_summary.html index 8881969..8ca13b1 100644 --- a/cpld/XC95144XL/WarpSE_summary.html +++ b/cpld/XC95144XL/WarpSE_summary.html @@ -2,30 +2,31 @@ - + - + - + +X +11 Errors (11 new) - + @@ -43,7 +44,7 @@ No Errors @@ -65,9 +66,9 @@ System Settings - - - + + +
WarpSE Project Status
WarpSE Project Status (09/03/2022 - 16:22:34)
Project File: WarpSE.xise Parser Errors: No Errors X 2 Errors
Module Name: WarpSE Implementation State:SynthesizedSynthesized (Failed)
Target Device: xc95144xl-10TQ100
  • Errors:
 -No Errors
Product Version:ISE 14.7
  • Warnings:
5 Warnings (0 new)No Warnings
Design Goal:
Environment: - + System Settings
  • Final Timing Score:
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed May 25 00:14:13 202205 Warnings (0 new)0
Translation ReportOut of DateMon Mar 28 09:45:45 2022000
CPLD Fitter Report (Text)Out of DateMon Mar 28 09:46:19 202202 Warnings (1 new)3 Infos (3 new)
Synthesis ReportCurrentSat Sep 3 16:22:35 2022X 11 Errors (11 new)00
Translation ReportOut of DateMon Mar 28 09:45:45 2022000
CPLD Fitter Report (Text)Out of DateMon Mar 28 09:46:19 202202 Warnings (1 new)3 Infos (3 new)
Power Report     
 
@@ -77,5 +78,5 @@ System Settings
-
Date Generated: 05/25/2022 - 21:10:23
+
Date Generated: 09/03/2022 - 17:36:27
\ No newline at end of file diff --git a/cpld/XC95144XL/WarpSE_xst.xrpt b/cpld/XC95144XL/WarpSE_xst.xrpt index 7a00b13..33818da 100644 --- a/cpld/XC95144XL/WarpSE_xst.xrpt +++ b/cpld/XC95144XL/WarpSE_xst.xrpt @@ -5,7 +5,7 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
@@ -78,63 +78,9 @@ -
- - - - - - - -
-
- - - - - -
-
-
-
-
-
-
-
- - - - - -
-
- -
-
- - - - - - - - - - - - - - - - - - - -
-
- - + +
diff --git a/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs b/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs index d6290ef..cd75aa8 100644 --- a/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs +++ b/cpld/XC95144XL/_xmsgs/pn_parser.xmsgs @@ -8,25 +8,19 @@ -Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/CNT.v" into library work +Analyzing Verilog file "Z:/Warp-SE/cpld/CNT.v" into library work -Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/CS.v" into library work +"Z:/Warp-SE/cpld/CNT.v" Line 127. Syntax error near "<=". -Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/FSB.v" into library work +Analyzing Verilog file "Z:/Warp-SE/cpld/IOBM.v" into library work -Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/IOBM.v" into library work +Analyzing Verilog file "Z:/Warp-SE/cpld/RAM.v" into library work -Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/IOBS.v" into library work - - -Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/RAM.v" into library work - - -Analyzing Verilog file "//192.168.64.1/Repos/Warp-SE/cpld/WarpSE.v" into library work +Analyzing Verilog file "Z:/Warp-SE/cpld/WarpSE.v" into library work diff --git a/cpld/XC95144XL/_xmsgs/xst.xmsgs b/cpld/XC95144XL/_xmsgs/xst.xmsgs index 0a93d02..f576589 100644 --- a/cpld/XC95144XL/_xmsgs/xst.xmsgs +++ b/cpld/XC95144XL/_xmsgs/xst.xmsgs @@ -5,23 +5,37 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -Input <SW<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +"../RAM.v" line 63 'BACTr' has not been declared -The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone. -You should achieve better results by setting this init to 1. +"../RAM.v" line 69 unexpected token: ';' -The value init of the FF/Latch 0 hinder the constant cleaning in the block Disable. -You should achieve better results by setting this init to 1. +"../RAM.v" line 75 unexpected token: 'begin' -The value init of the FF/Latch RESDone hinder the constant cleaning in the block WarpSE. -You should achieve better results by setting this init to 1. +"../RAM.v" line 76 expecting ';', found ')' -The value init of the FF/Latch Disable hinder the constant cleaning in the block WarpSE. -You should achieve better results by setting this init to 1. +"../RAM.v" line 76 unexpected token: '<=' + + +"../RAM.v" line 76 expecting 'endmodule', found '0' + + +"../FSB.v" line 59 'BERR' has not been declared + + +"../CNT.v" line 29 'RefREQ' has not been declared + + +"../CNT.v" line 30 'RefREQ' has not been declared + + +"../CNT.v" line 34 expecting ';', found '=' + + +"../CNT.v" line 34 expecting 'endmodule', found '0' diff --git a/cpld/XC95144XL/iseconfig/WarpSE.projectmgr b/cpld/XC95144XL/iseconfig/WarpSE.projectmgr index 394434e..e8178ae 100644 --- a/cpld/XC95144XL/iseconfig/WarpSE.projectmgr +++ b/cpld/XC95144XL/iseconfig/WarpSE.projectmgr @@ -25,13 +25,13 @@ User Constraints - Generate Timing + 0 0 000000ff0000000000000001000000010000000000000000000000000000000000000000000000012b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012b0000000100000000 false - Generate Timing + diff --git a/cpld/XC95144XL/iseconfig/WarpSE.xreport b/cpld/XC95144XL/iseconfig/WarpSE.xreport index 8a4a781..05692b8 100644 --- a/cpld/XC95144XL/iseconfig/WarpSE.xreport +++ b/cpld/XC95144XL/iseconfig/WarpSE.xreport @@ -1,11 +1,11 @@
- 2022-05-25T21:10:24 + 2022-09-03T14:17:57 WarpSE Unknown - //192.168.64.1/Repos/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport - //192.168.64.1/Repos/Warp-SE/cpld/XC95144XL\ + Z:/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport + Z:/Warp-SE/cpld/XC95144XL\ 2022-03-28T09:29:43 false
diff --git a/cpld/XC95144XL/webtalk_pn.xml b/cpld/XC95144XL/webtalk_pn.xml index 461191f..a5e10f5 100644 --- a/cpld/XC95144XL/webtalk_pn.xml +++ b/cpld/XC95144XL/webtalk_pn.xml @@ -3,7 +3,7 @@ - +
diff --git a/cpld/XC95144XL/xst/work/hdllib.ref b/cpld/XC95144XL/xst/work/hdllib.ref index e95d3b1..26515a8 100644 --- a/cpld/XC95144XL/xst/work/hdllib.ref +++ b/cpld/XC95144XL/xst/work/hdllib.ref @@ -1,8 +1,8 @@ MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1648475072 -MO CS NULL ../CS.v vlg22/_c_s.bin 1648475072 -MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1648475072 -MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1648475072 +MO CS NULL ../CS.v vlg22/_c_s.bin 1662227042 +MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1662227042 +MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1662227042 MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1648475072 -MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1648475072 -MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1648475071 +MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1662227042 +MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1662227042 MO MXSE NULL ../MXSE.v vlg15/_m_x_s_e.bin 1648473402 diff --git a/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin b/cpld/XC95144XL/xst/work/vlg14/_r_a_m.bin index 52858a95884117b920c096a1f22fd3bb1e1e3aa6..fe6eae49b1e7f05fa2f451d82cc86941ee113bea 100644 GIT binary patch delta 18 acmX@NnDN|V#tooBs-F%jh(HQ_z-UtBz diff --git a/cpld/XC95144XL/xst/work/vlg22/_c_s.bin b/cpld/XC95144XL/xst/work/vlg22/_c_s.bin index 2302e6317df5813e15e4b8b499542699df42d80f..d752e6c18097b7ce25a0d50a7068d9e679ee47de 100644 GIT binary patch delta 1191 zcmZ8gYfy|~7~MB^wcFNiZ9i%^EF&{*wQVW2iP<#xfs`@KnDwI!$!!c~7{3jgkuHxr zmE12C*^nf3Q6ZF4ZY6$ItKY^joNs%+nNQ!$+4nr>dCqy?@3QUr1Np@>#P`~n6>3_q ziJ%6xgLIlKYEoM%Qyof!n*CIxS>std?WhRSF3s7qclD~3OEOg|)l?etUrvj)?#LdM zN_+yoLG=R;0>yyu`ipC$sWgaMwB=%)a&@U<+*78T;}6K0i)O7spf>iMJh_X`+d z*$z1;$RS23-H;;2=zt+rJI1|4U&l-1hE(CDC}R^DYq^$FCHEcRKFyAIr#FB-1Rn9!0)_h?^m?x4RLT7Sc+7elbw`F#e|(zr8Pumh zv)oZ6H9~*FwY-Cr)C9EBiUhZ|1FRkBq}l}2^cJw^lX9f_HsB=9N<^Z#svw9(evPb^Wi1uzjMz$=icV$x4*KZvTmCA?wa1H z(14OiK4k;7Dlt@`M7V4Hm+NUHVByrz{Ho0rtE$VYN~>2cU7SC^K&R79p)5nmtXDdn z_yBx^q6c;Wb->v9i&K{C>Y{c-gYZ&GphI}w^?~tvF-UDe4l(E+4GPd3d~8pqmf$qu zqwEly;U{ZpQu|+JkSo|KhG;OvVHjeEO=`3vv?$gq6}c0apS*E?u;!)S&_1lShMBO| z6BZ$`s5IP!=SX-QEi=YZrZEy z%{P9f*bN+}0i=(C9R(V=o2f}3f_{W+b*fC)1IKAoO7V=-V5fjH?6PUnjnGfhuN0$l z0<4J)R;T>}STk^ueRhriEcEk}=E!a5fXmc?^i?ny;AWRYlfDG~3fJmXnQj5DQ+le? zejDr-aED!UHR)^6Z*r|pmFXM6J?ccd9jpy_z^*J!`Y!ZVuGOhBeIIy4#c9sm4lobU z$*y^t^h4-RxK^ji^kd)|>)Es