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Add back 68k clock gated slowdown

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This commit is contained in:
Zane Kaminski 2024-10-09 08:00:35 -04:00
parent bc75f67fb2
commit a9665dd8a8
2 changed files with 15 additions and 5 deletions
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12
cpld/CNT.v
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@ -8,12 +8,15 @@ module CNT(
/* Mac PDS bus master control outputs */ /* Mac PDS bus master control outputs */
output reg AoutOE, output reg nBR_IOB, output reg AoutOE, output reg nBR_IOB,
/* QoS select inputs */ /* QoS select inputs */
input nAS,
input ASrf,
input BACT, input BACT,
input QoSCS, input QoSCS,
input SndQoSCS, input SndQoSCS,
/* QoS outputs */ /* QoS outputs */
output reg QoSEN, output reg QoSEN,
output SndQoSReady); output SndQoSReady,
output reg MCKE);
/* E clock synchronization */ /* E clock synchronization */
reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E }; reg [1:0] Er; always @(posedge CLK) Er[1:0] <= { Er[0], E };
@ -21,6 +24,7 @@ module CNT(
/* C8M clock synchronization */ /* C8M clock synchronization */
reg [3:0] C8Mr; always @(posedge CLK) C8Mr[3:0] <= { C8Mr[2:0], C8M }; reg [3:0] C8Mr; always @(posedge CLK) C8Mr[3:0] <= { C8Mr[2:0], C8M };
wire C8MFall = C8Mr[1] && !C8Mr[0]; // C8M falling edge detect
/* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us /* Timer counts from 0 to 1010 (10) -- 11 states == 14.042 us
* Refresh timer sequence * Refresh timer sequence
@ -73,6 +77,12 @@ module CNT(
always @(posedge CLK) if (!BACT) QoSEN <= QS!=0; always @(posedge CLK) if (!BACT) QoSEN <= QS!=0;
assign SndQoSReady = 1; assign SndQoSReady = 1;
/* MC68k clock gating during QoS */
always @(negedge CLK, negedge nAS) begin
if (!nAS) MCKE <= 1;
else MCKE <= ASrf || !QoSEN || C8MFall;
end
/* Long timer counts from 0 to 4095. /* Long timer counts from 0 to 4095.
* 4096 states == 57.516 ms */ * 4096 states == 57.516 ms */
reg [11:0] LTimer; reg [11:0] LTimer;

8
cpld/WarpSE.v
View File

@ -41,9 +41,6 @@ module WarpSE(
output MCKE, output MCKE,
input [5:0] DBG); input [5:0] DBG);
/* MC68k clock enable */
assign MCKE = 1;
/* GA gated (translated) address output */ /* GA gated (translated) address output */
assign GA[23:22] = A_FSB[23:22]; assign GA[23:22] = A_FSB[23:22];
/*assign GA[23:22] = ( /*assign GA[23:22] = (
@ -218,12 +215,15 @@ module WarpSE(
.AoutOE(AoutOE), .AoutOE(AoutOE),
.nBR_IOB(nBR_IOBout), .nBR_IOB(nBR_IOBout),
/* QoS select inputs */ /* QoS select inputs */
.nAS(nAS_FSB),
.ASrf(ASrf),
.BACT(BACT), .BACT(BACT),
.QoSCS(QoSCS), .QoSCS(QoSCS),
.SndQoSCS(SndQoSCS), .SndQoSCS(SndQoSCS),
/* QoS outputs */ /* QoS outputs */
.QoSEN(QoSEN), .QoSEN(QoSEN),
.SndQoSReady(SndQoSReady)); .SndQoSReady(SndQoSReady),
.MCKE(MCKE));
FSB fsb( FSB fsb(
/* MC68HC000 interface */ /* MC68HC000 interface */