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Change pins to fix BERR issue

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This commit is contained in:
Zane Kaminski 2022-02-14 16:39:11 -05:00
parent 5e234b9382
commit a9b70fc4e7
1 changed files with 80 additions and 76 deletions
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cpld/MXSE.ucf
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@ -1,5 +1,4 @@
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "A_FSB[10]" LOC = "P8" ;
NET "A_FSB[11]" LOC = "P9" ;
@ -70,7 +69,12 @@ NET "RA[8]" LOC = "P54" ;
NET "RA[9]" LOC = "P56" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
#Created by Constraints Editor (xc95144xl-tq100-10) - 2022/02/07
NET "CLK_FSB" TNM_NET = CLK_FSB;
TIMESPEC TS_CLK_FSB = PERIOD "CLK_FSB" 25 MHz HIGH 50%;
NET "CLK2X_IOB" TNM_NET = CLK2X_IOB;
TIMESPEC TS_CLK2X_IOB = PERIOD "CLK2X_IOB" 15.6672 MHz HIGH 50%;
NET "CLK_IOB" TNM_NET = CLK_IOB;
TIMESPEC TS_CLK_IOB = PERIOD "CLK_IOB" 7.8336 MHz HIGH 50%;