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commit
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37
cpld/CNT.v
37
cpld/CNT.v
@ -71,53 +71,26 @@ module CNT(
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end
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end
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/* I/O QoS select register */
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reg IOQoSCSr;
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always @(posedge CLK) IOQoSCSr <= IOQoSCS;
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/* QoS select register */
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reg SndQoSCSr;
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always @(posedge CLK) SndQoSCSr <= SndQoSCS;
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reg QoSCSr;
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always @(posedge CLK) QoSCSr <= IOQoSCS || SndQoSCS;
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/* I/O QoS timer */
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reg [2:0] IOQS;
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always @(posedge CLK) begin
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if (!nRESr || (BACTr && (IOQoSCSr || SndQoSCSr))) IOQS[2:0] <= 1;
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if (!nRESr || (BACTr && QoSCSr)) IOQS[2:0] <= 1;
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else if (IOQS==0) IOQS[2:0] <= 0;
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else if (EFall && TimerTC) IOQS[2:0] <= IOQS[2] ? 0 : IOQS+1;
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end
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/* Sound QoS timer */
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reg [1:0] SndQS;
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always @(posedge CLK) begin
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if (BACTr && SndQoSCSr) SndQS[1:0] <= 1;
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else if (BACTr && IOQoSCSr) SndQS[1:0] <= 0;
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else if (SndQS==0) SndQS[1:0] <= 0;
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else if (EFall && TimerTC) SndQS[1:0] <= SndQS+1;
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end
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/* I/O QoS enable */
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always @(posedge CLK) if (!BACT) IOQoSEN <= IOQS!=0;
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/* Sound QoS enable */
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always @(posedge CLK) if (!BACT) SndQoSEN <= SndQS!=0;
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/* MC68K clock enable */
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always @(posedge CLK) MCKE <= BACT || BACTr || (IOQS==0) || C8MFall;
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/* Sound QoS wait state control */
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reg [4:0] Wait;
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always @(posedge CLK) begin
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if (!BACT) Wait <= 0;
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else Wait <= Wait+1;
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end
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/* Sound QoS ready control */
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always @(posedge CLK) begin
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if (!BACT) SndQoSReady <= !SndQoSEN;
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else if (BACTr) IOQoSCSr <= 1;
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else if (Wait==5'h1F) SndQoSReady <= 1;
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end
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/* Sound QoS removed */
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assign SndQoSReady = 1;
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/* Startup sequence state control */
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wire ISTC = EFall && TimerTC && LTimerTC;
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