-
-Some relevant timing parameters to which the bus timings were designed are as follows:
-| Parameter | Value | Description |
|---|---|---|
| tPD_CPLD | 10ns | asynchronous propagation delay |
| tCO_CPLD | 6ns | clock-to-output delay |
| tSU_CPLD | 6ns | global clock setup time |
| tRAS_DRAM | 60ns | RAS pulse width / access time |
| tASR_DRAM | 0ns | row address setup time before RAS |
| tRAH_DRAM | 10ns | row address hold time after RAS |
| tRCD_DRAM | 20ns | minimum RAS-to-CAS delay |
| tASC_DRAM | 0ns | column address setup time before CAS |
| tCAH_DRAM | 10ns | column address hold time after CAS |
| tCAS_DRAM | 20ns | CAS pulse width / access time |
| tRP_DRAM | 40ns | RAS precharge time |
| tCP_DRAM | 10ns | CAS precharge time |
| tRC_DRAM | 120ns | minimum RAS cycle time |
| tACC_ROM | 70ns | ROM access time |
| tOE_ROM | 40ns | ROM OE access time |
| tPD_573 | 20ns | 74AHCT573 propagation delay after LE or D |
| tSU_573 | 5ns | 74AHCT573 setup time before LE |
| tH_573 | 2ns | 74AHCT573 hold time after LE |
- Below I am presenting some timing diagrams showing the relevant signals for various interesting bus cycle cases.
- We are beginning with the timing of the accelerated processor bus, or the front-side bus (FSB), and proceeding on to the timing of the master port on the Mac SE bus, or the I/O Bus (IOB).
- The timing diagrams are scaled for a 25 MHz FSB clock frequency and the standard 7.8336 MHz Mac SE bus.
-
For starters, it is instructive to look at a generic MC68000 bus cycle.
@@ -836,3 +808,50 @@ document.querySelectorAll('script[type=wavedrom]').forEach(function(dgm) {