From aff6199c1c0bc002ab154f8348e4e74416e40778 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Thu, 12 Sep 2024 06:30:58 -0400 Subject: [PATCH] Update index.html --- Documentation/index.html | 103 +++++++++++++++++++++++---------------- 1 file changed, 61 insertions(+), 42 deletions(-) diff --git a/Documentation/index.html b/Documentation/index.html index 32e4f55..2478868 100644 --- a/Documentation/index.html +++ b/Documentation/index.html @@ -29,54 +29,26 @@ -

Garrett's Workshop Warp-SE 20/25 MHz 68HC000 Accelerator Documentation

- -

System Block Diagram

- - -

Relevant Timing Parameters

-

Some relevant timing parameters to which the bus timings were designed are as follows:

- - - - - - - - - - - - - - - - - - - - -
ParameterValueDescription
tPD_CPLD 10ns asynchronous propagation delay
tCO_CPLD 6ns clock-to-output delay
tSU_CPLD 6ns global clock setup time
tRAS_DRAM 60ns RAS pulse width / access time
tASR_DRAM 0ns row address setup time before RAS
tRAH_DRAM 10ns row address hold time after RAS
tRCD_DRAM 20ns minimum RAS-to-CAS delay
tASC_DRAM 0ns column address setup time before CAS
tCAH_DRAM 10ns column address hold time after CAS
tCAS_DRAM 20ns CAS pulse width / access time
tRP_DRAM 40ns RAS precharge time
tCP_DRAM 10ns CAS precharge time
tRC_DRAM 120ns minimum RAS cycle time
tACC_ROM 70ns ROM access time
tOE_ROM 40ns ROM OE access time
tPD_573 20ns 74AHCT573 propagation delay after LE or D
tSU_573 5ns 74AHCT573 setup time before LE
tH_573 2ns 74AHCT573 hold time after LE
+

Garrett's Workshop WarpSE 25 MHz 68HC000 Accelerator Documentation

-

Timing Diagrams

- Below I am presenting some timing diagrams showing the relevant signals for various interesting bus cycle cases.
- We are beginning with the timing of the accelerated processor bus, or the front-side bus (FSB), and proceeding on to the timing of the master port on the Mac SE bus, or the I/O Bus (IOB).
- The timing diagrams are scaled for a 25 MHz FSB clock frequency and the standard 7.8336 MHz Mac SE bus. -

0. Generic MC68000 bus cycle detection


For starters, it is instructive to look at a generic MC68000 bus cycle.
@@ -836,3 +808,50 @@ document.querySelectorAll('script[type=wavedrom]').forEach(function(dgm) { +', period: 2, data:[0,3,2,2,2,2,1,1,0,3,2,2,2,1,1,0], phase:-0.3}, +{name: 'IOACT', wave: '0....|1.|0....|1.|0.', phase:-0.3, period: 2}, +{name: 'IOREQ', wave: '01...|..|.....|.0|..', phase:-0.3, period: 2}, +{name: 'ALE1', wave: '1...0|..|....1|..|..', phase:-0.3, period: 2}, +{name: 'IORW1', wave: '2..0.|..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']}, +{name: 'IOLU1', wave: '2...2|..|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']}, +{name: 'ALE0', wave: '1.0..|.1|...0.|.1|..', phase:-0.3, period: 2}, +{name: 'IORW0', wave: '20...|..|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']}, +{name: 'IOLU0', wave: '2.2..|..|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']}, +{name: 'IOWRReady', wave: '1...0|..|....1|..|..', phase:-0.3, period: 2}, +]} +

+Similar to the previous case (again). This is the closest write timing allowed, even faster than MC68k can do. +

+ + + + + +