diff --git a/cpld/IOBM.v b/cpld/IOBM.v index 513dea3..e88eba0 100644 --- a/cpld/IOBM.v +++ b/cpld/IOBM.v @@ -31,8 +31,8 @@ module IOBM( /* ETACK and VMA generation */ wire ETACK = (ES==8) && !nVMA; - always @(posedge C8M) begin - if ((ES==4) && IOACT && VPAr) nVMA <= 0; + always @(negedge C8M) begin + if ((ES==3) && IOACT && VPAr) nVMA <= 0; else if (ES==0) nVMA <= 1; end diff --git a/cpld/XC95144XL/WarpSE.pad b/cpld/XC95144XL/WarpSE.pad index 7372a3b..ba68b59 100644 --- a/cpld/XC95144XL/WarpSE.pad +++ b/cpld/XC95144XL/WarpSE.pad @@ -1,7 +1,7 @@ Release 8.1i - Fit P.20131013 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved -10- 6-2024 11:04PM +10- 7-2024 4:59AM NOTE: This file is designed to be imported into a spreadsheet program such as Microsoft Excel for viewing, printing and sorting. The pipe '|' @@ -116,7 +116,7 @@ P95|A_FSB<2>|I|I/O|INPUT||||||||| P96|A_FSB<3>|I|I/O|INPUT||||||||| P97|A_FSB<4>|I|I/O|INPUT||||||||| P98|VCC||VCCINT|||||||||| -P99|RnW_IOB|O|I/O/GSR|OUTPUT||||||||| +P99|TIE||I/O/GSR|||||||||| P100|GND||GND|||||||||| To preserve the pinout above for future design iterations in diff --git a/cpld/XC95144XL/WarpSE.syr b/cpld/XC95144XL/WarpSE.syr index d9c8e80..fea2502 100644 --- a/cpld/XC95144XL/WarpSE.syr +++ b/cpld/XC95144XL/WarpSE.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs +Total CPU time to Xst completion: 0.08 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs +Total CPU time to Xst completion: 0.08 secs --> Reading design: WarpSE.prj @@ -141,6 +141,7 @@ Module is correct for synthesis. ========================================================================= Performing bidirectional port resolution... +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. Synthesizing Unit . Related source file is "../CS.v". @@ -152,8 +153,8 @@ Synthesizing Unit . Related source file is "../RAM.v". Found 8x3-bit ROM for signal . Found 1-bit register for signal . - Found 1-bit register for signal . Found 1-bit register for signal . + Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . @@ -189,7 +190,8 @@ Synthesizing Unit . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . - Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . @@ -206,19 +208,17 @@ Synthesizing Unit . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | - | Transitions | 13 | - | Inputs | 5 | + | Transitions | 12 | + | Inputs | 4 | | Outputs | 7 | | Clock | C16M (rising_edge) | | Power Up State | 000 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- - Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . - Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . @@ -228,13 +228,14 @@ Synthesizing Unit . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit up counter for signal . + Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). - inferred 15 D-type flip-flop(s). + inferred 14 D-type flip-flop(s). Unit synthesized. @@ -243,7 +244,6 @@ Synthesizing Unit . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . - Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . @@ -262,7 +262,7 @@ Synthesizing Unit . Found 4-bit up counter for signal . Summary: inferred 5 Counter(s). - inferred 11 D-type flip-flop(s). + inferred 10 D-type flip-flop(s). Unit synthesized. @@ -281,14 +281,14 @@ Synthesizing Unit . Related source file is "../WarpSE.v". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit tristate buffer for signal . +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Summary: - inferred 6 Tristate(s). + inferred 5 Tristate(s). Unit synthesized. @@ -303,13 +303,13 @@ Macro Statistics 2-bit down counter : 1 4-bit down counter : 1 4-bit up counter : 3 -# Registers : 62 - 1-bit register : 59 - 2-bit register : 1 +# Registers : 61 + 1-bit register : 57 + 2-bit register : 2 3-bit register : 1 4-bit register : 1 -# Tristates : 6 - 1-bit tristate buffer : 6 +# Tristates : 5 + 1-bit tristate buffer : 5 ========================================================================= @@ -340,6 +340,13 @@ Optimizing FSM on signal with johnson encoding. 10 | 11 01 | 10 ------------------- +WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1898 - Due to constant pushing, FF/Latch <0> is unconnected in block <0>. +WARNING:Xst:1898 - Due to constant pushing, FF/Latch <0> is unconnected in block . ========================================================================= Advanced HDL Synthesis Report @@ -353,48 +360,60 @@ Macro Statistics 2-bit down counter : 1 4-bit down counter : 1 4-bit up counter : 3 -# Registers : 47 - Flip-Flops : 47 +# Registers : 45 + Flip-Flops : 45 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . Optimizing unit ... Optimizing unit ... -Optimizing unit ... - implementation constraint: INIT=r : IOACTr - implementation constraint: INIT=r : Sent - implementation constraint: INIT=r : TS_FSM_FFd2 - implementation constraint: INIT=r : TS_FSM_FFd1 - Optimizing unit ... implementation constraint: INIT=r : ASrf Optimizing unit ... +Optimizing unit ... + implementation constraint: INIT=r : IOACTr + implementation constraint: INIT=r : TS_FSM_FFd2 + implementation constraint: INIT=r : Sent + implementation constraint: INIT=r : TS_FSM_FFd1 + Optimizing unit ... implementation constraint: INIT=s : IOS_FSM_FFd7 - implementation constraint: INIT=r : IOS_FSM_FFd6 implementation constraint: INIT=r : DoutOE + implementation constraint: INIT=r : IOS_FSM_FFd5 + implementation constraint: INIT=r : IOS_FSM_FFd6 implementation constraint: INIT=r : IOS_FSM_FFd1 implementation constraint: INIT=r : IOS_FSM_FFd2 implementation constraint: INIT=r : IOS_FSM_FFd3 implementation constraint: INIT=r : IOS_FSM_FFd4 - implementation constraint: INIT=r : IOS_FSM_FFd5 Optimizing unit ... implementation constraint: INIT=r : IS_0 implementation constraint: INIT=r : IS_1 implementation constraint: INIT=r : nPOR + implementation constraint: INIT=r : Timer_2 + implementation constraint: INIT=r : Timer_3 implementation constraint: INIT=r : Timer_0 implementation constraint: INIT=r : Timer_1 - implementation constraint: INIT=r : Timer_3 - implementation constraint: INIT=r : Timer_2 +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . ========================================================================= * Partition Report * @@ -423,45 +442,44 @@ Clock Enable : YES wysiwyg : NO Design Statistics -# IOs : 80 +# IOs : 79 Cell Usage : -# BELS : 690 -# AND2 : 203 -# AND3 : 34 -# AND4 : 11 +# BELS : 569 +# AND2 : 173 +# AND3 : 25 +# AND4 : 10 # AND5 : 3 # AND7 : 1 # AND8 : 2 # GND : 6 -# INV : 278 -# OR2 : 112 -# OR3 : 10 +# INV : 226 +# OR2 : 87 +# OR3 : 9 # OR4 : 4 # VCC : 1 -# XOR2 : 25 -# FlipFlops/Latches : 107 -# FD : 65 -# FDC : 2 -# FDCE : 38 +# XOR2 : 22 +# FlipFlops/Latches : 95 +# FD : 62 +# FDCE : 30 # FDCP : 1 -# FDP : 1 -# IO Buffers : 73 +# FDP : 2 +# IO Buffers : 72 # IBUF : 35 # IOBUFE : 1 # OBUF : 32 -# OBUFE : 5 +# OBUFE : 4 ========================================================================= Total REAL time to Xst completion: 5.00 secs -Total CPU time to Xst completion: 5.07 secs +Total CPU time to Xst completion: 4.90 secs --> -Total memory usage is 262624 kilobytes +Total memory usage is 262496 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 2 ( 0 filtered) -Number of infos : 0 ( 0 filtered) +Number of warnings : 22 ( 0 filtered) +Number of infos : 1 ( 0 filtered) diff --git a/cpld/XC95144XL/WarpSE_build.xml b/cpld/XC95144XL/WarpSE_build.xml index faa9ca6..2dba4df 100644 --- a/cpld/XC95144XL/WarpSE_build.xml +++ b/cpld/XC95144XL/WarpSE_build.xml @@ -5,7 +5,7 @@ - + diff --git a/cpld/XC95144XL/WarpSE_pad.csv b/cpld/XC95144XL/WarpSE_pad.csv index 02c2706..2312334 100644 --- a/cpld/XC95144XL/WarpSE_pad.csv +++ b/cpld/XC95144XL/WarpSE_pad.csv @@ -1,7 +1,7 @@ Release 8.1i - Fit P.20131013 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved -10- 6-2024 11:04PM +10- 7-2024 4:59AM NOTE: This file is designed to be imported into a spreadsheet program such as Microsoft Excel for viewing, printing and sorting. The comma ',' @@ -116,7 +116,7 @@ P95,A_FSB<2>,I,I/O,INPUT,,,,,,,,, P96,A_FSB<3>,I,I/O,INPUT,,,,,,,,, P97,A_FSB<4>,I,I/O,INPUT,,,,,,,,, P98,VCC,,VCCINT,,,,,,,,,, -P99,RnW_IOB,O,I/O/GSR,OUTPUT,,,,,,,,, +P99,TIE,,I/O/GSR,,,,,,,,,, P100,GND,,GND,,,,,,,,,, To preserve the pinout above for future design iterations in diff --git a/cpld/XC95144XL/WarpSE_xst.xrpt b/cpld/XC95144XL/WarpSE_xst.xrpt index 82af23c..1ca4b22 100644 --- a/cpld/XC95144XL/WarpSE_xst.xrpt +++ b/cpld/XC95144XL/WarpSE_xst.xrpt @@ -5,7 +5,7 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
@@ -81,14 +81,14 @@ - - - + + + - - + +
@@ -99,8 +99,8 @@ - - + +
@@ -117,26 +117,25 @@
- +
- - - - + + + + - - + + - + - - - - - + + + + - + @@ -144,8 +143,8 @@
- - + +