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Rename RAMReady to make it easier to eliminate later

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Zane Kaminski 2024-10-07 01:30:52 -04:00
parent 1d77155b60
commit b26d510391
1 changed files with 14 additions and 10 deletions
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24
cpld/RAM.v
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@ -7,7 +7,7 @@ module RAM(
/* Select and ready signals */ /* Select and ready signals */
input RAMCS, input RAMCS0X, input ROMCS, input ROMCS4X, input RAMCS, input RAMCS0X, input ROMCS, input ROMCS4X,
/* RAM ready output */ /* RAM ready output */
output reg RAMReady, output RAMReady,
/* Refresh Counter Interface */ /* Refresh Counter Interface */
input RefReqIn, input RefUrgIn, input RefReqIn, input RefUrgIn,
/* DRAM and NOR flash interface */ /* DRAM and NOR flash interface */
@ -31,6 +31,10 @@ module RAM(
wire RefReq = RefReqIn && !RefDone; wire RefReq = RefReqIn && !RefDone;
wire RefUrg = RefUrgIn && !RefDone; wire RefUrg = RefUrgIn && !RefDone;
/* RAM ready control */
reg RAMReadyReg;
assign RAMReady = RAMReadyReg;//!RS[2];
/* RAM control signals */ /* RAM control signals */
assign nRAS = !((!nAS && RAMCS && RASEN) || RASrf); assign nRAS = !((!nAS && RAMCS && RASEN) || RASrf);
assign nOE = 0;//!( !nAS && RAMCS && BACTr); assign nOE = 0;//!( !nAS && RAMCS && BACTr);
@ -75,31 +79,31 @@ module RAM(
RASEL <= BACT && RAMCS; RASEL <= BACT && RAMCS;
RefCAS <= RS0toRef; RefCAS <= RS0toRef;
RASEN <= !RS0toRef; RASEN <= !RS0toRef;
RAMReady <= !RS0toRef; RAMReadyReg <= !RS0toRef;
end 1: begin // RAM access end 1: begin // RAM access
if (!nDTACK || !BACT) RS <= 2; // Cycle ending if (!nDTACK || !BACT) RS <= 2; // Cycle ending
else RS <= 1; // Cycle not ending yet else RS <= 1; // Cycle not ending yet
RASEL <= 1; RASEL <= 1;
RefCAS <= 0; RefCAS <= 0;
RASEN <= nDTACK; RASEN <= nDTACK;
RAMReady <= 1; RAMReadyReg <= 1;
end 2: begin // finish RAM access end 2: begin // finish RAM access
RS <= 3; RS <= 3;
RASEL <= 0; RASEL <= 0;
RefCAS <= 0; RefCAS <= 0;
RASEN <= 0; RASEN <= 0;
RAMReady <= 1; RAMReadyReg <= 1;
end 3: begin //AS cycle complete end 3: begin //AS cycle complete
if (RefUrg) begin // Refresh RAS if (RefUrg) begin // Refresh RAS
RS <= 4; RS <= 4;
RefCAS <= 1; RefCAS <= 1;
RASEN <= 0; RASEN <= 0;
RAMReady <= 0; RAMReadyReg <= 0;
end else begin // Cycle ended so go back to idle/ready end else begin // Cycle ended so go back to idle/ready
RS <= 0; RS <= 0;
RefCAS <= 0; RefCAS <= 0;
RASEN <= 1; RASEN <= 1;
RAMReady <= 1; RAMReadyReg <= 1;
end end
RASEL <= 0; RASEL <= 0;
end 4: begin // Refresh RAS I end 4: begin // Refresh RAS I
@ -107,25 +111,25 @@ module RAM(
RASEL <= 0; RASEL <= 0;
RefCAS <= 0; RefCAS <= 0;
RASEN <= 0; RASEN <= 0;
RAMReady <= 0; RAMReadyReg <= 0;
end 5: begin // Refresh RAS II end 5: begin // Refresh RAS II
RS <= 6; RS <= 6;
RASEL <= 0; RASEL <= 0;
RefCAS <= 0; RefCAS <= 0;
RASEN <= 0; RASEN <= 0;
RAMReady <= 0; RAMReadyReg <= 0;
end 6: begin // Refresh precharge I end 6: begin // Refresh precharge I
RS <= 7; RS <= 7;
RASEL <= 0; RASEL <= 0;
RefCAS <= 0; RefCAS <= 0;
RASEN <= 0; RASEN <= 0;
RAMReady <= 0; RAMReadyReg <= 0;
end 7: begin // Reenable RAM and go to idle/ready end 7: begin // Reenable RAM and go to idle/ready
RS <= 0; RS <= 0;
RASEL <= 0; RASEL <= 0;
RefCAS <= 0; RefCAS <= 0;
RASEN <= 1; RASEN <= 1;
RAMReady <= 1; RAMReadyReg <= 1;
end end
endcase endcase
end end