diff --git a/cpld/FSB.v b/cpld/FSB.v
index 7c9c26d..fd24052 100644
--- a/cpld/FSB.v
+++ b/cpld/FSB.v
@@ -2,7 +2,7 @@ module FSB(
 	/* MC68HC000 interface */
 	input FCLK, input nAS, output reg nDTACK, output reg nVPA,
 	/* AS cycle detection */
-	output BACT, output reg BACTr,
+	output reg ASrf, output BACT, output reg BACTr,
 	/* Ready inputs */
 	input ROMCS,
 	input RAMCS, input RAMReady,
@@ -12,7 +12,6 @@ module FSB(
 	input IACS);
 
 	/* AS cycle detection */
-	reg ASrf = 0;
 	always @(negedge FCLK) begin ASrf <= !nAS; end
 	assign BACT = !nAS || ASrf; // BACT - bus active
 	always @(posedge FCLK) BACTr <= BACT;
diff --git a/cpld/WarpSE.v b/cpld/WarpSE.v
index 2422720..498023f 100644
--- a/cpld/WarpSE.v
+++ b/cpld/WarpSE.v
@@ -60,8 +60,7 @@ module WarpSE(
 	assign nRES = !nRESout ? 1'b0 : 1'bZ;
 
 	/* AS cycle detection */
-	wire BACT;
-	wire BACTr;
+	wire ASrf, BACT, BACTr;
 
 	/* Refresh request/ack signals */
 	wire RefReq, RefUrg;
@@ -233,6 +232,7 @@ module WarpSE(
 		.nDTACK(nDTACK_FSB),
 		.nVPA(nVPA_FSB),
 		/* FSB cycle detection */
+		.ASrf(ASrf),
 		.BACT(BACT),
 		.BACTr(BACTr),
 		/* Ready inputs */